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% MODIFY THE FOLLOWING TO INCLUDE THE LECTURE #, TOPIC, DATE, and YOUR NAME
\lecturetitle{17}{VLSI Physical Design 1}{24 Oct 97}{Rich Vuduc}

% INCLUDE AN OUTLINE OF THE CLASS TOPICS
\begin{itemize} 
  \item Notes regarding the homework assignment
    \begin{enumerate}
      \item Representing Delaunay triangulations
      \item Incremental Delaunay
      \item Ruppert meshing
      \item Surface approximation
    \end{enumerate}

  \item Intro to VLSI Physical Design
    \begin{enumerate}
      \item Overview of the VLSI process
      \item The role of algorithms in physical design
    \end{enumerate}

  \item Summary

  \item References
\end{itemize}

\section{Some notes regarding the homework assignment}
\noindent
Here we discuss a few implementation details that are relevant to
a few of the recent algorithms which we have
considered.

\subsection{Representing a Delaunay triangulation}
\noindent
There are a number of application-dependent approaches to storing
the mesh triangulations, such as the one shown in Figure~\ref{fig_mesh}.
Below, we discuss three possibilities:  neighbor graph, quad edge,
and triangle representations.

\begin{figure}[b]
\centerline{
\psfig{width=2in,angle=270,file=../lecture17/mesh.eps}}
\caption{A sample mesh.}
\label{fig_mesh}
\end{figure}

\subsubsection{Neighbor graph}
\noindent
In the {\em neighbor graph} representation, we treat the nodes
of the mesh as vertices in a graph, as shown in Figure~\ref{fig_neighbor}.
There, for each vertex we would store its adjacent vertices:

\begin{figure}
\centerline{
\psfig{width=2in,angle=270,file=../lecture17/neighbor.eps}
}
\caption{In the {\em neighbor graph} representation, we interpret the
triangulation as a graph and store each vertex with a list of its
neighboring vertices.}
\label{fig_neighbor}
\end{figure}

\begin{center}
\begin{tabular}{c|c}
\hline
vertex & neighbors \\
\hline
1 & \{ 2, 6, 4 \} \\
2 & \{ 1, 4, 5, 3 \} \\
3 & \{ 2, 5 \} \\
4 & \{ 1, 6, 7, 5, 2 \} \\
5 & \{ 2, 4, 7, 3 \} \\
etc. & \ldots \\
\hline
\end{tabular}
\end{center}

\noindent
It is generally helpful to keep each list of adjacent vertices
ordered (in the above example, we have stored them in counterclockwise
order, but you could use any ordering that is convenient for your
application).

\subsubsection{Quad edge}

Instead of using only vertices for our primary representation, we
could store edges instead.  One clever way to store edges is called
the {\em quad edge} data structure (Guibas and Stolfi, ACM
Trans. Graphics, 4(2), 1985)\footnote{This was the format used by
Garland and Heckbert \cite{bib_Garland} in their original work.
However, in comments to Prof. Blelloch they mentioned that this
representation was not particularly well-suited to their
application.}.  This data structure is defined along with an ``edge
algebra'' which allows one to traverse a triangulation easily.  In
this representation we keep a structure for each edge which stores the
4 adjoining edges as we travel clockwise and counter clockwise from
each endpoint of the edge.  For example in Figure~\ref{fig:quadedge}
the four edges adjoining edge 4 are 3, 8, 1 and 5, and the four edges
adjoining edge 1 are 3, 4, 5 and 2.  In fact the data structure keeps a
pointer to one of the 4 fields within each of these adjoining edges.
This makes it possible to easily circle around a vertex or an edge.
The table below shows an example of our internal representation for
the mesh shown in Figure~\ref{fig:quadedge}.  The value after the dot
represents which of the 4 entries in the edge is being pointed to.

\begin{figure}
\begin{center}
\begin{tabular}{c}
\psfig{width=2in,angle=270,file=../lecture17/quadedge.eps} 
%&\psfig{width=2in,angle=270,file=../lecture17/voroquad.eps} \\
\end{tabular}
\end{center}
\caption{
For the quad-edge format, we store each edge along
with the 4 adjoining edges (when traveling clockwise and counterclockwise).
%({\em Right}) Each edge of our quad-edge diagram of our Delaunay
%triangulation corresponds to a segment in the equivalent Voronoi diagram.
}
\label{fig:quadedge}
\end{figure}

\begin{center}
\begin{tabular}{c|l}
\hline
edge & neighboring edges \\
\hline
1 & \{ 2.0, 5.1, 4.2, 3.1 \} \\
  & \ldots\\
4 & \{ 5.0, 8.3, 3.2, 1.1 \}\\
5 & \{ 12.2, 4.3, 1.0, 6.1 \}\\
  & \ldots\\
8 & \{ 4.0, 9.1, 11.2, 3.3 \}\\
9 & \{ 10.0, 11.3, 8.0, 12.1 \}\\
  & \ldots \\
12 & \{ 6.0, 10.3, 9.2, 5.1 \}\\
  & \ldots \\
\hline
\end{tabular}
\end{center}

To circle around a vertex we start at an even field of an edge
structure (.0 or .2) and follow the pointers, and to circle around a
face (triangle) we start at an odd field (.1 or .3).  For example, to
circle around the vertex in the middle starting at edge 4 we simply
start by following 4.0 and continue around touching edges 5, 12, 9, 8
and back to 4 (more specifically 5.0, 12.2, 9.2, 8.0, 4.0).  Similarly
to circle around triangle (1,4,5) we can start from 4.3 and visit 1.1,
5.1 and back to 4.3.

The algebra on the quad-edge data structure suggested by Guibas and
Stolfi uses the three operations {\tt next}, {\tt rotate}, and
{\tt symmetric} which take a pointer and return a new pointer.  
The {\tt next} operation circles
around a vertex or triangle, the {\tt rotate} operation switches from
a vertex to a triangle (the one that shares the edge, next edge, and
vertex) or vise versa, and the {\tt symmetric} operation switches to
the vertex at the other end of the edge.
Assuming each quad-edge is an array of 4 ``pointers'' each consisting
of a pointer to another quad-edge and an index within the quad-edge,
then for a pointer {\tt (e,i)} the operations are defined as:
\begin{quote}
\tt
next(e,i) = e[i]\\
rotate(e,i) = (e, i+1)\\
symmetric(e,i) = (e, i+2)
\end{quote}
where {\tt +} is defined modulo 4.  

\subsubsection{Triangles}

Lastly, we turn to what is perhaps the most natural representation:
{\em triangles}.  With each triangle, it may be useful to store the
3 other with which it shares a side.  So, for the example shown in
Figure~\ref{fig_triangle}, our table of data might look something like:

\begin{figure}
\centerline{
\psfig{width=2in,angle=270,file=../lecture17/triangle.eps}
}
\caption{Mesh representation using triangles.  Triangle 1 shares sides
with triangles 2 and 3.}
\label{fig_triangle}
\end{figure}

\begin{center}
\begin{tabular}{c|c}
\hline
triangle & side-adjacent triangles \\
\hline
1 & \{ 3, 2, $\square$ \} \\
2 & \{ 1, 4, $\square$ \} \\
3 & \{ 6, 1, $\square$ \} \\
4 & \{ 6, 5, 2 \} \\
5 & \{ 4, $\square$, $\square$ \} \\
6 & \{ 4, 3, $\square$ \} \\
\hline
\end{tabular}
\end{center}

In addition to the neighboring triangles it is typically useful to
store the vertices of each triangle.  In this representation the
function {\tt opposite(p,T)} which given a triangle {\tt T} and a
vertex (point) {\tt p } on that triangle returns the triangle opposite that
point is often useful.   For example, in Figure~\ref{fig_triangle}
given the leftmost point and triangle 2, {\tt opposite} would
return triangle 4.

\subsection{Incremental Delaunay}

Recall that in the incremental Delaunay algorithm of previous lectures, we
are given a triangulation to which we wish to add an additional point.  The
suggested approach is based on a depth-first search style algorithm.
Figure~\ref{fig_incdel} illustrates the action of the following pseudocode
to insert a point $p$ into an existing triangulation.

\begin{quote}
\begin{minipage}{.98\textwidth}
\begin{tabbing}
{\bf function} Insert($p,R$)\\
~~~~// $p$ a point\\
~~~~// $R$ an existing triangulation \\[.08in]
~~~~$T$ = the triangle containing $p$\\
~~~~$(T_1, T_2, T_3)$ = the triangles created by splitting $T$ by $p$\\
~~~~Patch($p,T_1$)\\
~~~~Patch($p,T_2$)\\
~~~~Patch($p,T_3$)\\
{\bf end}
\end{tabbing}
\end{minipage}

\vspace{.1in}

\begin{minipage}{.98\textwidth}
\begin{tabbing}
{\bf function} Patch($p,T$)\\
~~~~$T'$ = Opposite($p,T$)\\
~~~~{\bf if} InCircle($p,T'$)\\
~~~~~~~~$(T_1,T_2) = \mbox{Flip}(T,T')$\\
~~~~~~~~Patch($p,T_1$)\\
~~~~~~~~Patch($p,T_2$)\\
{\bf end}
\end{tabbing}
\end{minipage}
\end{quote}

The function Flip flips two adjacent triangles so the crossedge changes.

\begin{figure}
\begin{center}
\begin{tabular}{cc}
\psfig{width=2in,angle=270,file=../lecture17/incdel0.eps} &
\psfig{width=2in,angle=270,file=../lecture17/incdel1.eps} \\
\psfig{width=2in,angle=270,file=../lecture17/incdel2.eps} &
\psfig{width=2in,angle=270,file=../lecture17/incdel3.eps} \\
\end{tabular}
\end{center}
\caption{
({\em Top-left}) We wish to add the point $p$ to an existing triangulation,
and $p$ happens to fall within the triangle $T$.
({\em Top-right}) Adding $p$ creates the smaller triangles $T_1$, $T_2$,
$T_3$.
({\em Bottom-left}) We consider the action of the \texttt{Patch}
subroutine at some point in the recursion for the point $p$ and some other
triangle $T$ (i.e., not necessarily the same as above).
({\em Bottom-right}) Result after executing \texttt{flip}($p$, $T'$).
}
\label{fig_incdel}
\end{figure}


\subsection{Ruppert Meshing}
\noindent
In this section we discuss two issues to consider when implementing
Ruppert's meshing algorithm \cite{bib_Ruppert}.

The first relates to how one finds encroaching points.  First, recall
that a point $p$ {\em encroaches} upon a segment $s$ if $p$ lies within
the diametrical circle defined by $s$ (see Figure~\ref{fig_encroach}).
To determine which points encroach upon $s$, it is sufficient to check
endpoints of all Delaunay edges that come out of an endpoint of the
segment.  In a practical implementation, one would probably need a
data structure that facilitates moving from point to point within
the triangulation; one possibility would be a data structure that
keeps neighboring triangles with each point.

The second issue relates to the creation of {\em phantom small angles},
which is best explained by an example.  In particular, suppose that our
input polygon is the one shown in Figure~\ref{fig_phantom} ({\em top}).
Recall that an initial step in computing the triangulation requires that
we compute the convex hull of the input polygon; this could result in the
creation of {\em phantom small angles} such as the one shown in
Figure~\ref{fig_phantom} ({\em bottom-left}).  An easy solution is to first
create a bounding box around the input polygon, as shown in
Figure~\ref{fig_phantom} ({\em bottom-right}).

\begin{figure}
\centerline{
\psfig{width=2.5in,angle=270,file=../lecture17/encroach.eps}
}
\caption{In the situation shown, we wish to see if there are any points
in the triangulation that encroach on the segment $s$ (e.g., $p$).}
\label{fig_encroach}
\end{figure}

\begin{figure}
\centerline{
\psfig{width=1in,angle=270,file=../lecture17/phantom1.eps,width=2in}}

\centerline{
\psfig{width=2in,angle=270,file=../lecture17/phantom2.eps} \\
\psfig{width=2.5in,angle=270,file=../lecture17/phantom3.eps}
}
\caption{
({\em Top}) Input polygon.
({\em Bottom-left}) Initial convex-hull computation results in creation
of tiny ``phantom small angles.''
({\em Bottom-right}) One easy solution is to placing a bounding box around the
figure, and then triangulate this new figure.
}
\label{fig_phantom}
\end{figure}

\subsection{Surface Approximation}
\noindent
One important step in the surface approximation algorithm discussed in
a previous lecture is to find the largest error in a newly added
triangle.  This requires examining every point within the triangle.
One technique for doing so might be to bound the triangle under
consideration by a rectangle first, then scan the pixels within the
triangle row- or column-wise.  For each pixel that we scan, we can
check whether or not it falls within the triangle before computing
its error.  (See Figure~\ref{fig_surf}.)
A fancier method would find the edges that border on the left and
right and only scan the horizontal lines between them.

\begin{figure}
\centerline{
\psfig{width=2in,angle=270,file=../lecture17/surf.eps}
}
\caption{In computing the error of a newly added triangle in the
surface approximation algorithm, we can bound the triangle by a box and
scan, testing whether or not the pixel lies within the triangle before
using it to compute the error.}
\label{fig_surf}
\end{figure}


\section{Intro to VLSI Physical Design Automation}
\noindent
Since the dark ages (i.e., the 1960's), a typical integrated circuit
design has grown from a hundred transistors to the millions of transistors
required by modern microprocessors.  {\em Very large scale integration}
(VLSI) refers to the process of integrating such a large number of
transistors for fabrication;  {\em VLSI physical design} is the process
of converting a circuit description into a layout.  The ability to lay out
such enormous circuits has been made possible by the intelligent application
of computer algorithms.

Here, we give a brief overview of the overall VLSI physical design process,
and show where algorithms play a key role.  We will be making a number of
references to diagrams shown in \cite{bib_Sherwani}.\footnote{In fact, most
of the material here is simply a paraphrase of material that appears in
\cite{bib_Sherwani}.}

\subsection{Overview}

The following is a high-level description of the VLSI design process.
The focus of our discussions will be on step 5 below.

\begin{enumerate}
\item \textbf{System specification}:
The first step involves the creation of a formal, high-level representation of
the system.  In this stage, we consider the desired functionality, performance,
and physical requirements of the final product.

\item \textbf{Functional design}:
In this step, we break down the system into functional sub-units, and
specify the relationships between them (for example, by generating a
timing diagram or showing the desired flow between sub-units).

\item \textbf{Logic design}:
In this process, we formalize the logical structure of our functional
design, typically by generating boolean formulas.  An interesting problem
is how to minimize such expressions, and neat algorithms like binary
decision diagrams have found applications here.  However, we will not be
discussing these.

\item \textbf{Circuit design}:
From the logic design, we next need to generate a circuit representation.
We have to consider power and speed requirements of our original design,
and often perform simulations of electrical behavior in this stage (e.g.,
through the use of PSpice software).

\item \textbf{Physical design}:
In this stage (the focus of our discussions), we must actually
lay out the circuit designs.  We must ensure that our resulting layout
conforms to the physical and geometric constraints of our system, which we
formulate as {\em design rules}.  These design rules are essentially
guidelines based on physical constraints due to limitations in the
fabrication process.

\comment{
\item \textbf{Design verification}:
Perform
{\em design rule checking}, in which we confirm that the layout does in
fact conform to the design rules specified in the previous step.
Verify the functionality of the design by circuit extraction (this
effectively reverse engineers the circuits from the layout).
}

\item \textbf{Fabrication}:
This stage is the actual physical manufacturing step, in which we prepare
the wafer and deposit/diffuse various materials onto the wafer.

\item \textbf{Packaging, testing, and debugging}:
In this stage, we test the actual manufactured and packaged chip.
\end{enumerate}

\noindent
It is important to note that this entire design process is iterative, i.e.,
there is a kind of ``feedback'' effect in which we examine the results,
perform any necessary hand-tuning, and re-run the process, continually
refining our previous results.


\subsubsection{Physical design}

We now turn our attention to the physical design cycle which will be
our focus.  The following is a brief summary of the high-level
process.  Note that the input to this process is the circuit design,
and the output will be a layout ready for the fabrication
stage.\footnote{Automation of the entire physical design process is
akin to the idea of building a ``silicon compiler.''}

\begin{enumerate}
\item \textbf{Partitioning}:
We must first break down, or {\em partition}, the input circuit into more
manageable blocks (or subcircuits, or modules).  In the partitioning
process, we must consider the size and number of blocks, as well as the
number of interconnections which will obviously affect the routing.
The set of interconnections is called a {\em netlist}.  For large
designs, the blocks may be hierarchical.

\item \textbf{Floorplanning and placement}:
In {\em floorplanning}, we consider such factors as the exact size of
the blocks generated in the previous step.  This is a computationally
difficult step, and often requires a design engineer to do this by hand.
During {\em placement}, we  position the blocks exactly as they will appear
on the chip.  We want to lay out the blocks in such a way so as to minimize
the area required to complete all the interconnections.  This is generally
an iterative process in which we lay out the blocks, and continually refine
the placements.

Furthermore, it is crucial to use a good placement strategy because the
placement essentially determines the routing (see below).

\item \textbf{Routing}:
In the {\em routing} phase, we lay out the interconnections (i.e., put down
wires) specified by the netlist that was generated in the partitioning phase
(above).  We refer to the space not occupied by blocks as the {\em routing
space}.  We partition this space into rectangular regions called
{\em channels} and {\em switchboxes}.  Our router must make the connections
using only these two types of regions, and it must do so in such a way so as
to minimize wire length.

The routing process can be divided into two phases.  In the first phase,
called {\em global routing}, in which the global router must make a list of
channels (i.e., passageways) through which to route the wire.  The next phase,
called {\em detailed routing}, completes the actual point-to-point
wiring.

Although the routing problem is computationally hard, many heuristic
algorithms have been developed.

\item \textbf{Compaction}:
In this final phase, we compress the generated layout to reduce the total
area.  A smaller area would enable us to increase the yield.
\end{enumerate}


\subsubsection{Design styles}
\noindent
Although we have taken the entire physical design process and broken it
up into smaller subproblems, we have noted that each subproblem is still
computationally hard.  To make these problems more tractable (and thus
reduce the time-to-market and increase the yield), we can further restrict
our design methodology into one of the following {\em design styles}:

\begin{enumerate}
\item \textbf{Full custom}:  We use this term to refer to a design style
which places few (if any) constraints on the physical design process.
For example, we would place no restrictions on where a block could be
placed (e.g., on a grid).  Clearly, this is the most difficult design
style to automate because of the high degree of freedom.  A {\em full custom}
approach is really only appropriate when performance must be high.  For
instance, this is the method of choice for the layout of modern
microprocessors.  An example is shown in \cite{bib_Sherwani} (Figure 1.3).

\item \textbf{Standard cell}:  In the {\em standard cell} design style, we
predesign certain functional units as standard cells, or standard blocks,
and create a {\em cell library} of ``pre-packaged'' blocks that we can then
use for placement.  Each cell is preanalyzed and pretested.  Given
that the cells are predesigned, the main challenge is the layout
and routing.  An example of a standard cell
layout is shown in \cite{bib_Sherwani} (Figure 1.4).  Notice that the blocks
are all of a similar shape and size, and that their layout is much more
regular than the layout of the full-custom design shown in
\cite{bib_Sherwani} (Figure 1.3).  Observe that in the standard cell design,
our only (roughly speaking) degree of freedom is the ability to shift
blocks to open up routing channels between placed cells.

\item \textbf{Gate arrays}:  A {\em gate array} is like a standard cell
except that all the ``cells'' are the same, and laid out in an array
form as shown in \cite{bib_Sherwani} (Figure 1.5).  The name is indicative
of the idea that the cells could be as simple as a single gate (a 3-input
NAND gate is shown).  Furthermore, the routing channels are basically
predetermined.  The advantage of the gate array style over the previous two
is its simplicity.  In particular, it is cheaper and easier to produce a
wafer based on this style.  Routing is also simplified, since we only have
to make connections and not worry about minimizing the area used.  An
example of a routed gate array for a simple logic circuit is shown in
\cite{bib_Sherwani} (Figure 1.6).

However, the cost is the rigidity imposed---we would certainly be forced to
produce larger chips and incur a performance penalty.

\item \textbf{Field programmable gate arrays}:  A {\em field programmable
gate array} (FPGA) is something in-between the gate array and standard cell.
An example is shown in \cite{bib_Sherwani} (Figure 1.7).  Each ``cell'' of a
FPGA (labeled by $B_i$ in the figure) can be viewed as a lookup table that
can be programmed.  Furthermore, there is no free region over which we do
our routing; instead, the wires are fixed, and we connect the cells by
burning in {\em fuses} (shown as squares and circles).  The figure shows
a sample logic circuit which has been partitioned into four regions.  We
construct the lookup table for each region, and this is what is programmed
into the cells of the FPGA (in this example, the four left-most cells labeled
$B_i$).  The connections appropriate fuses are burned in (shown as darkened
circles and squares).  The partitioning problem for FPGAs is different from
that of the other design styles, but the placement and routing problems are
similar to those of the gate array.
\end{enumerate}

\noindent
We summarize the various tradeoffs alluded to above as follows
\cite{bib_Sherwani} (table 1.2):

\begin{center}
\begin{tabular}{|c|c|c|c|c|}
\hline
& \multicolumn{4}{|c|}{style} \\
\hline
Area & compact & compact to moderate & moderate & large \\
\hline
Performance & high & high to moderate & moderate & low \\
\hline
Fabrication layers & all & all & routing layer & none \\
\hline
\end{tabular}
\end{center}

\noindent
In general, within a given column of the table there is a correlation
between the rows.  Moreover, the columns are roughly ordered in
decreasing cost.


\subsubsection{Transistor level}
\noindent
When we discuss algorithms in future lectures, it will be sufficient to
formulate the routing and placement problem at an abstract level.  However,
in this section, we will very briefly look at the ``small picture'' for a
little perspective.

Figure~\ref{fig_nMOStrans} shows a diagram of the vertical cross-section of
a nMOS transistor, as well as its schematic representations.  An nMOS
transistor is an example of a more general kind of transistor called a
{\em field-effect transistor}.  In such a device, we can control the flow
of current between the two terminals (labeled {\em source} and {\em drain})
by controlling the voltage applied to the non-conducting terminal called the
{\em gate}.  In particular, applying a voltage to the gate sets up an
electric field that changes the conducting properties of the region
labeled {\em channel} thereby allowing current to flow from the source to
the drain.  For a more general introduction to the basic solid-state physics
behind the operation of these devices, see \cite{bib_Kittel} and
\cite{bib_Online}.

\begin{figure}
\centerline{
\psfig{width=2.5in,file=../lecture17/fig25.eps}
}
\caption{The operation of an nMOS transistor.
(a) A vertical cross-section of a transistor
based on the $n-p-n$ junction.
(b) When a voltage has been applied to the gate, the induced electric
field alters the conducting properties of the channel, thereby allowing
current to flow.
(c) Schematic representations of the process.
[Taken from \protect\cite{bib_Sherwani} (Figure~2.5).]}
\label{fig_nMOStrans}
\end{figure}

By combining several transistors, we can construct basic logic gates such
as the NAND gate shown in Figure~\ref{fig_NAND}.  See the figure caption for
a rough description of its operation.

\begin{figure}
\centerline{
\psfig{width=2.5in,file=../lecture17/fig27.eps}
}
\caption{The layout of CMOS NAND gate ({\em left}) using four transistors,
and its schematic representation ({\em right}).  The input to the NAND
are labeled A and B, and the output is C.
The bottom two transistors are n-channel and open when their gates
are high while the top two are p-channel and open when their gates are low.
({\em Basic operation}) When A and B are both high, the channels of the
upper-two transistors are closed and the bottom two are opened, thus
enabling a connection from GND to C.  In all other cases, the channels of
at least one of the lower transistors will be closed which will break the
connection between GND and C, whereas when either channel of the upper
two transistors are open, C will be pulled up to VDD.  [Taken from
\protect\cite{bib_Sherwani} (Figure~2.7).]}
\label{fig_NAND}
\end{figure}

Finally, note that in the figure of the NAND gate, there are various
rectangular shaded regions which represent different materials.  These
materials must obey certain rules, namely, they must be of certain
dimensions and must be separated by different amounts, as shown in
Figure~\ref{fig_sizesep}.  These are the kinds of rules and constraints we
will be subject to in our automation algorithms.

\begin{figure}
\centerline{
\psfig{width=2.5in,file=../lecture17/fig210.eps}
}
\caption{Size and separation rules.  The dimensions have been characterized
in terms of the design parameter $\lambda$.  The ``.35'' of the terms
``.35 micron technology,'' et al., refer to this parameter.
[Taken from \protect\cite{bib_Sherwani} (Figure~2.10).]}
\label{fig_sizesep}
\end{figure}


\subsection{The role of algorithms}
\noindent
Algorithms have played a crucial role in the explosive growth of VLSI
technology.  Graph theory has played a particularly important part.
Here is a list of some of the many algorithms that have been applied
to VLSI physical design automation:

\begin{enumerate}
\item Graphs

\begin{itemize}
\item spanning trees
\item shortest path
\item matching
\item Steiner trees
\item maximum independent set
\item maximum clique
\end{itemize}

\item Computational geometry

\begin{itemize}
\item intersection of lines or rectangles
\end{itemize}

\item Optimization

\begin{itemize}
\item integer programming
\end{itemize}
\end{enumerate}

\noindent
These algorithms have found applications in many of the design areas
discussed in the physical design overview, namely

\begin{itemize}
\item layout
\item partitioning
\item placement
\item routing
\item compaction
\end{itemize}

\noindent
Furthermore, these algorithms are applicable in all the different design
styles (full-custom, standard cell, etc.).  We will be paying particular
attention to the routing problem.

Our overall goal will be either to minimize area given physical constraints
on our design, or to maximize functionality in a given fixed area.  We
will have to be concerned with how to:

\begin{description}
\item[minimize delays]:  In particular, we can accomplish by minimizing
wirelength and reducing capacitance (by keeping the overall layouts small).
\item[reducing the number of layers]  Increasing the number of layers
required in a design greatly increases fabrication costs.
\item[reducing the number of pins]:  Of particular concern in multi-chip
modules.
\end{description}

\noindent
All of the major designers and manufacturers of VLSI chips are investing
heavily in automation research and techniques.  However, hand-tuning still
has an important place in the design phases.

\subsection{Evolution}
\noindent
We will close by summarizing the history of development tools in
physical design automation.

\begin{center}
\begin{tabular}{|c|c|}
\hline
Year & Design Tools \\
\hline
1950-1965 & Manual design \\
\hline
1965-1975 & Layout editors \\
& Automatic routers \\
& Efficient partitioning algorithms \\
\hline
1975-1985 & Automatic placement tools \\
& Well defined phases of design of circuits \\
& Significant theoretical development in all phases \\
\hline
1985-present & Performance driven placement and routing tools\\
& (in particular, an emphasis on space and speed) \\
\hline
& Parallel algorithms for physical design \\
& Significant development in underlying graph theory \\
& (i.e., the use of theoretical results) \\
& Combinatorial optimization problems for layout \\
\hline
\end{tabular}
\end{center}


\section{Summary}
\noindent
In the first section, we gave some notes about implementation
methods for several triangulation algorithms.  In particular, we discussed
some ideas for data structure representation, with the triangle
representation seeming the most useful.

We then gave a brief overview of the entire VLSI design process, and
introduced the physical design stage in more detail.  We showed that
algorithms play an important role, our overall goal being to minimize
the layout area (to increase our chip's performance) while subject to
various constraints of our physical design (e.g., separation).


\begin{thebibliography}{00}
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1995.

\bibitem{bib_Ruppert} J. Ruppert.  ``A Delaunay refinement algorithm for
quality 2-dimensional mesh generation.''  NASA Technical Report,
RNR-94-002, January 1994.

\bibitem{bib_Sherwani} N. Sherwani.  {\em Algorithms for VLSI Physical
Design Automation}.  Kluwer, 1995.

\bibitem{bib_Kittel} C. Kittel.  {\em Introduction to Solid-State Physics}.
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\bibitem{bib_Online} On-line course notes on ``Heterojunction Devices'' from
the University of Colorado.
[\verb!http://ece-www.colorado.edu/~bart/6355.htm!]
\end{thebibliography}

