15-213 Introduction to Computer Systems
Lecture 12: Cache Memories

• Reading: Ch 6.4-6.8 (6.1-6.3); Notes
• Slides: none
• Code: none
• Concepts:
  • L1 i-cache and d-cache
  • L2 unified cache
  • Spatial locality
  • Cache hit and miss
  • Direct-mapped cache
  • Associative cache
  • Write-through and write-back
• Previous lecture: Out-of-Order Processing
• Next lecture: Linking

Notes on Lab Machines

These are a few notes about the cache characteristics of the processor used for this class, the Intel Nocona Xeon, which is a dual 3.2 GHz IA32-EM64T processor. This information was copied from the Fall 2005 instance of this course.

• L1 instruction cache: 12KB, 8-way set associative, 64 byte blocks
  1 cycle access time for cache hit
• L1 data cache: 16KB, 8-way set associative, 64 byte blocks
  so t = 37, s = 5, b = 6
  1 cycle access time for cache hit
• L2 unified cache: 1MB, 8-way set associative, 64 byte blocks
  so t = 31, s = 11, b = 6
  ~10 cycles access time for cache hit
• Main memory: 2GB
  ~50-100 cycles access time

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Frank Pfenning