Between each pair of antennas in a wireless network, there exist two channels - one in each direction. Each channel consists of one or more signal paths, and each path has a loss model, a fading model and possibly a delay associated with it. The loss model defines the large-scale path loss between the destination and source antennas. It is typically fixed when the nodes are stationary but will change when one or both of the wireless devices move. The fading model defines small-scale fading between the source and destination antennas. It consists of rapid variations in the signal strength that are the result of movement of objects in the physical environment around the two nodes, so they can occur even if the device antennas are stationary.
In the wireless network emulator, the signal propagation evaluation is emulated using channel models for both large-scale path loss and small-scale fading. These models have been developed and validated by the wireless communications community. We describe these models in more detail below. The parameters of the models can be controlled directly by the user, or, as we describe on the Emulator Control Software page, some of the parameters can be derived automatically based on the state of the emulated world model. For example, the distance between two devices can be used to determine the large-scale path lost based on the log distance model.
The signal processing HDL code on the FPGA performs the processing required by the channel models discussed above. The figure above shows a conceptual diagram of the operation of the FPGA code. Incoming signals are first sent into a delay line where one or more copies (``taps'') of the signal are pulled off after going through a programmable amount of delay. Each of these signals is then scaled by a programmable factor that incorporates the combined effect of the large-scale path loss and small-scale fading. Each outgoing signal, from the FPGA to an RF node, is then computed by summing the scaled signals from the other RF nodes. By combining multiple copies of the same input signal, but with different delays, we can emulate multipath channels. The outgoing signals are then sent to the D/A board for conversion into an RF signal.
The currently deployed system uses the above implementation, except that we only provide multi-path channels between 3 of the nodes (i.e. six channels). The other channels only support a single channel and do not have a programmable delay. The reason for this limitation is the number of multipliers on the FPGA (each path needs a multiplier). We hope to have a more flexible design in future releases. In the current system, the large-scale path loss and small-scale fading parameters are calculated on the Emulation Control Node in the channel model layer, as is described in the Emulator Control Software page.
Each channel has associated with it a Channel Model that controls the signal transfer function between transmitter and receiver.