Nanoelectronics - the Original Positronic Brain?

			   Dan Hammerstrom
		      Portland State University

The semiconductor industry has been following Moore's law for almost
30 years.  Intel is now manufacturing in their new, innovative 45 nm
process.  Transistors of this size are no longer acting like ideal
switches.  And there are other problems: power density, performance
overkill, density overkill, and the predicted end of Moore's law --
scaling will continue, though at a decreasing rate, asymptotically
approaching 22nm in 10-15 years.

Because of power and interconnect limitations, ever increasing
processor performance will need to come more from parallel execution.
However, there are still few opportunities to leverage parallelism in
volume market desktop applications - we still have not solved the
parallel computing problem.

Another serious problem is that the complexity of these systems is
growing exponentially.  How do we create a 100% guaranteed correct
design of several billion transistors?

Will we hit the complexity or parallel programming walls before
Moore's law runs out?  Can we, by moving to molecular scale
"electronics," buy time?  Is it possible?  Will nanoelectronics be
economical?  What will we do with it?  Will it enable new
applications?  Or will it be more of the same?  And most importantly,
what should the research agenda be?

Of the various problems facing the semiconductor industry, which ones
does nanotechnology solve?  It severely aggravates the design
complexity problem.  Having trouble figuring out what to do with and
how to reliably design 1 Billion transistors?  Well, we're going to
give you 1 Trillion!  The current design tools and methodologies will
not stretch that far.  But, the $64K question is, what exactly will we
use nanoelectronics for?

Radical new technologies create radical new opportunities.  What if we
could find an application space that, in addition to promising a
solution to the Intelligent Computing problem, also addressed some of
the other challenges facing the computer industry?  One that exhibited
massive parallelism, low power density -- where performance was based
on parallelism not speed, tolerance of static and dynamic faults, some
design fault tolerance, asynchrony (no clock), and be a system that
was adaptive and self-organizing.

The opportunity for this community is real and it is coming.  We need
massively parallel algorithms to drive this effort and to justify the
investment in the necessary architectures and implementation
technology.  As a group NIPS participants are better positioned to
leverage this opportunity than almost any other application domain.

In this presentation I will summarize some of the more promising nano-
electronic architectures and lay out a roadmap for the hardware
opportunities.