module testbench; reg Clk, Resetn; reg [7:0] Keyin; reg [7:0] Secin; reg Start; wire [7:0] Secout; wire Dvalid; DeCSS dut(Clk, Resetn, Keyin, Secin, Start, Secout, Dvalid); integer i; integer count; initial begin: init Clk <=5; Resetn <=0; Secin<=1; Keyin<=0; #10 Resetn <=1; #100 Start <=1; #10 Start <=0; Keyin <= 1; #10 Keyin <=2; #10 Keyin <=3; #10 Keyin <=4; #10 Keyin <=5; count=0; while(1) begin if (Dvalid) begin $display("OUTPUT=%x at time=%d", Secout, $time ); #10 Secin <= Secin+1; if (count>(32'h 800 - 32' 80)) begin $display("Done."); $finish; end count = count+1; end else #10 ; end #2000 $display("Done."); $finish; end // init // Clock Generator always @(Clk) begin: clockgenerator #5 Clk <= ~Clk; end // clock endmodule