Investigating Load Redundancy

A load can be one of the more costly instructions for a modern processor to execute, especially if there is a cache miss. Processors can now execute multiple instructions in the time it takes to fetch one word from memory, and this gap in speed is only growing larger. Superscalar processors can execute other instructions while a load is taking place, but any instruction dependent on the result of the load must stall. It is reasonable to conjecture that a small but significant number of loads are in a sense redundant, because the value read from memory was already in the register. If we could speculatively bypass the load when it was suspected to be redundant (and of course clear the pipeline later if the speculation turned out to be incorrect), this could result in a significant gain in performance.

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Click here for our milestone report in HTML. (This has been superceded by our report.)