%0 Generic %T TRW Monolithic Video A/D Converter %0 Book %D 1979 %T The 8086 Family User's Manual %0 Book %D 1988 %T Programming Parallel Processors %I Addison-Wesley %0 Book %D 1989 %T American National Standard for Information Systems Programming Language Fortran: S8(X3.9-198x) %0 Report %D 1993 %T Electrotechnical Laboraotory ETL %I Agency of Industrial Science and Technology, Ministry of International Trade and Industry %0 Edited Book %D 1993 %T Applications of Digital Image Processing XVI %B Proceedings of the Spie The International Society for Optical Engineering %V 2028 %P 14-16 %X The following topics were dealt with: image coding and compression; vision and imaging applications; restoration and enhancement; pattern recognition; architectures and simulation. %0 Edited Book %D 1994 %T Proceedings of 26th Southeastern Symposium on System Theory %B Los Alamitos, Ca, Usa: Ieee Comput. Soc. Press %I IEEE %P 5320-5 %X The following topics were dealt with: power systems; signal processing; control theory; algorithms and software; time-varying systems; modelling and simulation; radar systems and target tracking; electromagnetics; fuzzy systems; neural networks; detection and estimation; VLSI; image processing; system theory; communication networks; power distribution; optics; system identification; microprocessors and parallel processing; communications theory; control system applications;. %0 Journal Article %D 1994 %T Second International Meeting on Fully Three-Dimensional Image Reconstruction in Radiology and Nuclear Medicine %J Physics in Medicine and Biology %V 39 %N 3 %P 0031-9155 %K nuclear medicine; reconstruction algorithms comparison; medical diagnostic imaging ; 3D reconstruction algorithms; positron emission tomography; multi-slice rebinning; axial image filtering; human striation imaging ; oversampled filters; rotating positron tomographs; convolution-subtraction scatter correction method; pinhole collimation; cone-beam tomography; 3D compensation methods; SPECT; iterative reconstruction; massively parallel computers ; 3D computerized angiography; figures of merit COMPUTERISED TOMOGRAPHY; IMAGE RECONSTRUCTION; MEDICAL IMAGE PROCESSING ; RADIOISOTOPE SCANNING AND IMAGING %X The following topics were dealt with: 3D reconstruction algorithms for positron emission tomography; multi-slice rebinning and axial image filtering; statistically significant differences between algorithms; human striation imaging ; oversampled filters; rotating positron tomographs; a convolution-subtraction scatter correction method; pinhole collimation; cone-beam tomography; 3D compensation methods for SPECT; iterative reconstruction in SPECT; massively parallel computers for 3D SPECT; 3D computerized angiography; figures of merit for comparing reconstruction algorithms. %0 Edited Book %D 1994 %T IEE Colloquium on ' Parallel Architectures for Image Processing ' (Digest No.1994/135) %I IEE %C London, UK %V 60 %K TMS320C40; parallel architectures ; single chip processor; video signal processing architecture; coding; computer vision ; reconfigurable logic; parallel computing machine ; ASTRA; conceptual hierarchical image processor; optical computing; parallel image processing ; parallel volume rendering ; image data classification; transputers; produce inspection; image processing system DIGITAL SIGNAL PROCESSING CHIPS; ENCODING; IMAGE PROCESSING ; OPTICAL INFORMATION PROCESSING; PARALLEL ARCHITECTURES; TRANSPUTERS %X The following topics were dealt with: single chip video signal processing architecture for image processing ; coding and computer vision ; reconfigurable logic based parallel computing machine; ASTRA; conceptual hierarchical image processor; optical computing for parallel image processing ; parallel volume rendering; image data classification; transputers for produce inspection; and a parallel TMS320C40-based image processing system. %0 Edited Book %D 1994 %T Proceedings of SOUTHEASTCON '94 %I IEEE %C Miami, FL %P 492 %X The following topics were dealt with: bioengineering technology; multidimensional systems and signals; energy systems; optics and lasers; high speed communication networks; power electronics; modelling and simulation; neural networks; electromagnetics; circuits and systems; communications; power systems; reliability; computer networks; education; control systems; parallel and fault-tolerant systems; image processing ; digital systems; signal processing; robotics. %0 Journal Article %A Abelson, H. %A Andreae, P. %D 1980 %T Information Transfer and Area-Time Tradeoffs for VLSI Multiplication %J Communications of the ACM %V 23 %N 1 %P 20-23 %0 Conference Proceedings %A Acierno, A d' %A Stefano, C. de %A Tortorella, F. %A Vendo, M. %D 1994 %T Can a Sequential Thinning Algorithm be Parallelized %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 360-362 %0 Journal Article %A Agrawal, O.P. %A Laws, D.A. %D 1984 %T The Role of Programmable Logic in System Design %J VLSI Design %V V %N 3 %P 44-56 %0 Conference Proceedings %A Agrawal, A. %A Nekludova, L. %A Lim, W. %D 1987 %T A Parallel O(log N) Algorithm for Finding Connected Components in Planar Images %J International Conference on Parallel Processing %0 Journal Article %A Ahmed, N. %A Natarajan, T. %A Rao, K.R. %D 1974 %T Discrete Cosine Transform %J IEEE Trans. on Computers %V C-23 %N 1 %P 90-93 %0 Book %A Aho, A. %A Hopcroft, J.E. %A Ullman, J.D. %D 1975 %T The Design and Analysis of Computer Algorithms %I Addison-Wesley %C Reading, Massachusetts %0 Book %A Aho, A. V. %A Hopcroft, J. E. %A Ullman, J. D. %D 1983 %T Data Structures and Algorithms %I Addison-Wesley %0 Book %A Aho, A. V. %A Sethi, R. %A Ullman, J. D. %D 1986 %T Compilers: Principles, Techniques, and Tools %I Addison-Wesley %0 Conference Proceedings %A Ajiro, M. %A Miyata, H. %A Kan, T. %A Ono, M. %D 1993 %T Satellite image processing using cellular array processor (CAP) %J Igarss '93 %E Fujimura, S. %I IEEE %C Tokyo, Japan %P 1972-4 %X Since its successful launch in February of 1992, the Japan Earth Resources Satellite-1 (JERS-1) has been sending back high resolution images of the Earth for various studies, including the investigation of Earth resources, the preservation of environments and the observation of coastal lines. Currently, received images are processed using the Earth Resources Satellite Data Information System (ERSDIS). The ERSDIS is a high speed image processing system utilizing an extended cellular array processor as its main processing module. The extended cellular array processor (CAP), consisting of 4096 processing elements configured into a two-dimensional array, is designed to have many parallel processing optimizing capabilities targetting large-scale image processing at a high speed. This paper describes the structure of the ERSDIS and the details of the CAP design. %0 Conference Proceedings %A Akeley, K. %D 1993 %T RealityEngine graphics %J Computer Graphics Proceedings %I ACM %C Anaheim, CA %P 109-16 %K RealityEngine graphics system; rendering; texture mapped antialiased polygons; near-massively parallel ; antialiased texture mapped pixels; rendering performance; texture mapped triangles; high-end graphics workstation; real time; image generation; interactive image processing COMPUTER GRAPHIC EQUIPMENT; IMAGE PROCESSING ; PARALLEL PROCESSING; RENDERING (COMPUTER GRAPHICS); SOLID MODELLING; SYSTEMS ANALYSIS %X The RealityEngine graphics system is the first of a new generation of systems designed primarily to render texture mapped, antialiased polygons. This paper describes the architecture of the RealityEngine graphics system, then justifies some of the decisions made during its design. The implementation is near-massively parallel, employing 353 independent processors in its fullest configuration, resulting in a measured fill rate of over 240 million antialiased, texture mapped pixels per second. Rendering performance exceeds 1 million antialiased, texture mapped triangles per second. In addition to supporting the functions required of a general purpose, high-end graphics workstation, the system enables realtime, "out-the-window" image generation and interactive image processing . %0 Book %A Akl, S. G. %D 1985 %T Parallel Sorting Algorithms %I Academic Press %0 Conference Proceedings %A Alander, J. T. %D 1993 %T On robot navigation using a genetic algorithm %J Artificial Neural Nets and Genetic Algorithms. Proceedings of the International Conference %P 471-8 %X We study the possibility of using genetic algorithms in mobile robot navigation. The autonomous robot has a map of the room it moves within and some simulated sensors including range sensors to measure the distance between the robot and the other objects in the room. The location estimation method is based on minimizing the fitness function that depends on the measured data and the environment model by a genetic algorithm. The potential benefits of the genetic algorithms in this application area include robustness, parallel nature, generality, flexibility, incrementality, and simplicity. The obvious drawbacks include slow and stochastic processing. This work is a preliminary one in examining the applicability of genetic algorithms to solve computational problems of industrial and autonomous robots. In general the proposed method of finding the vector that gives the optimal fitting to the model used can be applied in may other calibration type problems as well in robotics as many other fields, too. %0 Conference Proceedings %A Albenesi, M. G. %A Ferretti, M. %A Leoni, S. %D 1994 %T A Hierarchical Compression Engine %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 391-394 %0 Journal Article %A Albert, E. %A Lukas, J. D. %A Steele, Jr., G. L. %D 1991 %T Data Parallel Computers and the FORALL Statement %J Journal of Parallel and Distributed Computing %V 13 %N 2 %P 185-192 %0 Journal Article %A Aleliunas, R. %A Rosenberg, A.L. %D 1982 %T On Embedding Rectangular Grids in Square Grids %J IEEE Transactions on Computers %V C-31 %N 9 %P 907-913 %0 Journal Article %A Ali, Z. %D 1980 %T FFT Algorithms Speed Digital-Signal Processing %J Electronic Design %V %P 111-118 %0 Conference Proceedings %A Ali, A. T. %A Dagless, E. L. %D 1990 %T Vehicle and Pedestrian Detection and Tracking %J IEE Colloquium on 'Image Analysis for Transport Applications' %P 5/1-7 %0 Conference Proceedings %A Allart, E. %A Zavidovique, B. %D 1988 %T Functional Computer for Low Level Image Processing %J 9th International Conference on Pattern Recognition %C Rome, Italy %P 830-2 %0 Conference Proceedings %A Allart, E. %A Zavidovique, B. %D 1989 %T Global Transforms in Real Time with the Functional Low Level Image Processor (FLLIP) %J 5th International Conference on Image Analysis and Processing. Progress in Image Analysis and Processing %C Positano, Italy %P 666-70 %0 Conference Proceedings %A Allen, J. R. %A Kennedy, K. %D 1984 %T Automatic Loop Interchange %J ACM SIGPLAN Symposium on Compiler Construction %C Montreal %P 233-46 %0 Conference Proceedings %A Allen, Robert %A Yasuda, Dean %A Tanimoto, Steven %A Shapiro, Linda %A Cinque, Luigi %D 1993 %T A Parallel Algorithm for Graph Matching and its MasPar Implementation %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 13-18 %0 Generic %A Alliant Computer Systems Corporation %D 1987 %T FX/Series Product Summary %0 Conference Proceedings %A Allinson, N. M. %A Howard, N. J. %A Kolcz, A. R. %A Tyrrell, A. M. %D 1994 %T Image processing applications using a novel parallel computing machine based on reconfigurable logic %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 2/1-7 %K parallel computing machine ; reconfigurable logic; Zelig; fine-grained computer; field-programmable gate arrays; binary morphology; speed-up results IMAGE PROCESSING EQUIPMENT; LOGIC ARRAYS; PARALLEL MACHINES %X Zelig is a 32 physical node fine-grained computer employing field-programmable gate arrays. Its application to the high speed implementation of various image pre-processing operations (in particular binary morphology) is described together with typical speed-up results. %0 Journal Article %A Alnuweiri, H. M. %A Kumar, V. K. P. %D 1991 %T Fast Image Labeling Using Local Operators on Mesh-Connected Computers %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 13 %N 2 %P 202-207 %0 Conference Proceedings %A Alnuweiri, Hussein M. %D 1991 %T Constant Time Image Component Labelling on a Reconfigurable Processor Array %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 565-572 %0 Conference Proceedings %A Alnuweri, H. %A Kumar, V. K. P. %D 1990 %T Optimal Image Algorithms on an Orthogonally-Connected Memory-Based Architecture %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 350-5 %0 Conference Proceedings %A Alverson, R. %A Callahan, D. %A Cummings, D. %A Koblenz, B. %A Porterfield, A. %A Smith, B. %D 1990 %T The Tera Computer System %J International Conference on Supercomputing %I ACM %C Amsterdam, Netherlands %P 1-6 %X The TERA architecture was designed with several major goals in mind. First, it needed to be suitable for very high speed implementations, i.e., admit a short clock period and be scalable to many processors. Second, it was important that the architecture be applicable to a wide spectrum of problems. A third goal was ease of compiler implementation. Although the instruction set does have a few unusual features, these do not seem to pose unduly hard problems for the code generator. The TERA architecture is derived from that of Horizon although they are highly similar multistream MIMD systems, there are many significant differences between the two designs. %0 Conference Proceedings %A Alves de Barros, Marcelo %A Akil, Mohamed %D 1994 %T Low Level Image Processing Operators on FPGA: Implementation Examples and Performance Evaluation %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 262-267 %0 Book Section %A American Microsystems Inc. %D 1980 %T Fast Fourier Transformer %B MOS Products Catalog %I American Microsystems Inc. %P 2.90 - 2.91 %0 Journal Article %A Amin, S. A. %A Evans, D. J. %D 1994 %T Systolic array design for low-level image processing %J Kybernetes %V 23 %N 1 %P 26-38 %K systolic array design; low-level image processing ; parallel algorithms ; low-level digital image processing ; gradient operator; double pipeline; system bus; Prewitt operators; Sobel operators IMAGE PROCESSING EQUIPMENT; PIPELINE PROCESSING; SYSTOLIC ARRAYS; TRANSPUTER SYSTEMS %X Systolic array designs of parallel algorithms for low-level digital image processing , and in particular the gradient operator, are described. Indicates how, to achieve high performance, a new systolic array can be designed in which all the cells in a double pipeline are interconnected to a system bus. The transputer implementation of the design is also considered and comments and conclusions that relate to the use of the systolic array on transputer networks are given. Subsequently it is shown that the systolic array design can be extended to handle the Prewitt and Sobel operators. %0 Edited Book %A Ammar, R. A. %D 1991 %T Proceedings of ISMM Symposium Parallel and Distributed Computing and Systems - II %I Acta Press %C Washington, DC, USA %P 111 %K neural networks; fault tolerance; multiprocessor interconnection; parallel architectures ; parallel algorithms ; image processing FAULT TOLERANT COMPUTING; MULTIPROCESSING SYSTEMS; MULTIPROCESSOR INTERCONNECTION NETWORKS; PARALLEL ALGORITHMS; PARALLEL ARCHITECTURES; PARALLEL PROGRAMMING %X The following topics were dealt with: neural networks, fault tolerance, multiprocessor interconnection; parallel architectures; parallel algorithms; and image processing . %0 Report %A Anderson, A. H. %D 1980 %T Restructurable VLSI Program %0 Conference Proceedings %A Anderson, Jennifer M. %A Lam, Monica S. %D 1993 %T Global Optimizations for Parallelism and Locality on Scalable Parallel Machines %J Programming Languages Design and Implementation %I ACM SIGPLAN %C Albuquerque, NM %P 112-125 %0 Conference Proceedings %A Angeniol, B. %A Treleaven, P. %D 1990 %T The Pygmalion Neural Network Programming Environment %J Advanced Neural Computers %I Air Force Office of Scientific Research %C Amsterdam, Netherlands %P 167-75 %0 Generic %A Annaratone, M. %D 1985 %T Warp Host Software Requirements and Deliverables %C Carnegie Mellon University Department of Computer Science %0 Conference Proceedings %A Annaratone, M. %A Arnould, E. %A Hsiung, P.K. %A Kung, H.T. %D 1985 %T Extending the CMU Warp Machine with a Boundary Processor %J Proceedings of SPIE Symposium, Vol. 564, Real-Time Signal Processing VIII %0 Conference Proceedings %A Annaratone, M. %A Arnould, E. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Menzilcioglu, O. %A Sarocky, K. %A Webb, J.A. %D 1986 %T Warp Architecture and Implementation %J Annual International Symposium on Computer Architecture %P 346-356 %0 Conference Proceedings %A Annaratone, M. %A Arnould, E. %A Kung, H. T. %A Menzilcioglu, O. %D 1986 %T Using Warp as a Supercomputer in Signal Processing %J Proceedings of ICASSP 86 %P 2895-2898 %0 Conference Proceedings %A Annaratone, M. %A Bitz, F. %A Clune, E. %A Kung, H. T. %A Maulik, P. %A Ribas, H. %A Tseng, P. %A Webb, J. %D 1987 %T Applications and Algorithm Partitioning on Warp %J COMPCON Spring '87 %C San Francisco, CA %P 272-275 %0 Conference Proceedings %A Annaratone, M %A Arnould, E. %A Cohn, R. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Menzilcioglu, O. %A Sarocky, K. %A Senko, J. %A Webb, J. %D 1987 %T Architecture of Warp %J COMPCON Spring '87 %C San Francisco, CA %P 264-267 %0 Conference Proceedings %A Annaratone, M. %A Bitz, F. %A Deutch, J. %A Hamey, L. %A Kung, H. T. %A Maulik, P. %A Ribas, H. %A Tseng, P. %A Webb, J. %D 1987 %T Applications Experience on Warp %J Proceedings of the 1987 National Computer Conference %I AFIPS Press %C Chicago, IL %P 149-158 %0 Conference Proceedings %A Annaratone, M %A Arnould, E. %A Cohn, R. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Menzilcioglu, O. %A Sarocky, K. %A Senko, J. %A Webb, J. %D 1987 %T Warp Architecture: From Prototype to Production %J Proceedings of the 1987 National Computer Conference %P 133-140 %0 Journal Article %A Annaratone, M. %A Arnould, E. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Menzilcioglu, O. %A Webb, J. A. %D 1987 %T The Warp Computer: Architecture, Implementation and Performance %J IEEE Transactions on Computers %V C-36 %N 12 %P 1523-1538 %0 Conference Proceedings %A Annaratone, M. %D 1988 %T Singular Value Decomposition on Warp %J SVD and SIGNAL PROCESSING Algrorithm, Applications and Architectures %0 Conference Proceedings %A Anyanwu, C. D. %A Jalowiecki, I. P. %A Krikelis, A. %D 1994 %T Evaluating ASTRA on image processing applications %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 3/1-6 %K associative string processor; image processing applications ; ASP System Testbed for Research and Applications; ASTRA; parallel processing system ; multilayer heterogeneous architecture; extendable linear array; associative processing elements; performance evaluation; vision-related benchmarks IMAGE PROCESSING EQUIPMENT; PARALLEL ARCHITECTURES; PERFORMANCE EVALUATION %X The ASP System Testbed for Research and Applications (ASTRA) is an associative processor-based parallel processing system developed for image processing applications. The machine implements a multilayer heterogeneous architecture with an extendable linear array of simple associative processing elements at its base and more powerful processors at higher levels. A model has been developed to assist in performance evaluation studies of the system on image processing applications with the aid of vision-related benchmarks. The machine and an analysis of some of the results obtained on one such benchmark are discussed in this paper. %0 Book %A Apostol, T. %D 1974 %T Mathematical Analysis %I Addison-Wesley %C Reading, Massachusetts %0 Journal Article %A Archibald, J. %A Baer, J-L. %D 1986 %T Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model %J ACM Transactions on Computer Systems %V 4 %N 4 %P 273-298 %0 Edited Book %A Arnold, D. %A Christie, R. %A Day, J. %A Roe, P. %D 1994 %T Proceedings of the 6th Australian Transputer and Occam User Group Conference. Parallel Computing and Transputers %I Ios Press %C Amsterdam, Netherlands %P 383 %X The following topics were dealt with: concurrent programming; graphics and image processing ; parallel algorithms; parallel applications; robotics and control; and software tools. %0 Conference Proceedings %A Arnould, E. %A Kung, H.T. %A Menzilcioglu, O. %A Sarocky, K. %D 1985 %T A Systolic Array Computer %J Proceedings of 1985 IEEE International Conference on Acoustics, Speech and Signal Processing %P 232-235 %0 Conference Proceedings %A Arnould, E. A. %A Bitz, F. J. %A Cooper, E. C. %A Kung, H. T. %A Sansom, R. %A Steenkiste, P. A. %D 1989 %T The Design of Nectar: A Network Backplane for Heterogeneous Multicomputers %J Proceedings of Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS III) %0 Journal Article %A Athas, W. C. %A Seitz, C. L. %D 1988 %T Multicomputers: Message-Passing Concurrent Computers %J Computer %V 21 %N 8 %P 9-24 %0 Conference Proceedings %A Atkinson, J. %A Hobson, C. A. %A Kshirsagar, S. %A Lilley, F. %A Pearson, J. D. %D 1993 %T Computer vision methods for the three-dimensional measurement of manufactured parts %J Computer Vision for Industry %I SPIE %C Munich, Germany %P 24-25 %K three-dimensional measurement; non-contact system; surface shape measurement; manufactured parts; coherent optical system; parallel processing hardware ; structured lighting; multi-stripe fringe pattern; parallel image processing system ; TMS320C40; MIMD message passing architecture; EISA bus; host interface; data acquisition; reliability; robustness AUTOMATIC OPTICAL INSPECTION; COMPUTER VISION ; PARALLEL ARCHITECTURES; SPATIAL VARIABLES MEASUREMENT %X Describes a non-contact system for surface shape measurement of manufactured parts. The technique consists of a coherent optical system combined with powerful parallel processing hardware, thus allowing rapid inspection rates to be realised. A 'structured lighting system is employed involving the projection of a multi-stripe fringe pattern onto the object surface thus enabling three dimensional data to be obtained. Phase measuring techniques are applied in order to increase accuracy and resolution. A comparison is made between two different phase measuring methodologies. These techniques require computationally intensive algorithms and processing of large amounts of image data. Image processing hardware should be fast enough to achieve results within a reasonable time scale. A parallel image processing system has been designed for such applications based on the Texas Instruments digital signal processor type TMS320C40. The system is based on MIMD message passing architecture and uses an EISA bus for the host interface. The issues of speed of data acquisition and processing, reliability and robustness of the technique and accuracy are discussed. %0 Journal Article %A Aubusson, R. C. %A Catt, I. %D 1978 %T Wafer Scale IntegrationA Fault Tolerant Procedure %J IEEE Journal of Solid-State Circuits %V SC-13 %N 3 %P 339-344 %0 Conference Proceedings %A Avila, J. %A Kuekes, P. %D 1983 %T One-Gigaflop VLSI Systolic Processor %J Proceedings of SPIE Symposium, Vol. 431, Real-Time Signal Processing VI %P 159-165 %0 Conference Proceedings %A Ayache, N. %A Hansen, C. %D 1988 %T Rectification of images for binocular and trinocular stereovision %J Proceedings of the Ninth International Conference on Pattern Recognition %C Rome, Italy %P 11-16 %0 Journal Article %A Azcarraga, A. %A Paugam-Moisy, H. %A Puzenat, D. %D 1994 %T An incremental neural classifier on a MIMD parallel computer %J Ifip Transactions A %V 44 %P 13-22 %X MIMD computers are among the best parallel architectures available. They are easily scalable with numerous processors and have potentially huge computing power. One area of application for such computers is the field of neural networks. The article presents a study, and two parallel implementations, of a specific neural incremental classifier of visual patterns. This neural network is incremental in that network units are created whenever the classifier is not able to recognize correctly a pattern. The dynamic nature of the model renders the parallel algorithms rather complex. %0 Conference Proceedings %A strand, Erik %A stršm, Anders %D 1994 %T A Single Chip Multi-Function Sensor System for Wood Inspection %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 300-304 %0 Book %A Baase, S. %D 1988 %T Computer Algorithms: Introduction to Design and Analysis, Second Edition %I Addison-Wesley %0 Book Section %A Baer, J.-L. %D 1980 %T Computer Systems Architecture 7 %I Computer Science Press %S Digital System Design Series %0 Conference Proceedings %A Baig, M. S. %A Alexandridis, N. A. %A El-Ghazawi, T. A. %D 1991 %T A highly reconfigurable multiple SIMD/MIMD architecture %J Proceedings of the Fourth Ismm/iasted International Conference Parallel and Distributed Computing and Systems %E Ammar, R. A. %I Acta Press %C Washington, DC %P 35-6 %K reconfigurable; multiple SIMD/MIMD; MSIMD/MIMD; architecture; partitionable broadcasting interconnection network; high performance; performance/cost MULTIPROCESSOR INTERCONNECTION NETWORKS; PARALLEL ARCHITECTURES; PERFORMANCE EVALUATION %X Many partitionable SIMD/MIMD architectures were introduced in order to provide high performance for engineering and scientific applications, such as image processing . Such systems are referred to as Multiple SIMD/MIMD, MSIMD/MIMD, computers. The authors present a new MSIMD/MIMD architecture and an analytical study comparing it with its existing competitors. The high performance exhibited by this system is attributed to its partitioning flexibility. The system avoids the inherent rigidity in the existing systems through the use of a general purpose computing element and a partitionable broadcasting interconnection network. This network allows dynamic (run time) assignment of the role of processing element or control unit to each of the general purpose computing elements. Analytical models for the proposed system as well as for its comparables are developed. It is shown that the proposed architecture presents a significantly better performance/cost tradeoff when compared with the existing MSIMD/MIMD systems. %0 Journal Article %A Bal, H. E. %A Steiner, J. G. %A Tanenbaum, A. S. %D 1989 %T Programming Languages for Distributed Computing Systems %J Computing Surveys %V 21 %N 3 %P 261-322 %0 Book %A Ballard, D. H. %A Brown, D.M. %D 1982 %T Computer Vision %I Prentice-Hall %0 Journal Article %A Ballard, D. H. %D 1991 %T Animate Vision %J Artificial Intelligence %V 48 %N 1 %P 57-86 %0 Edited Book %A Baozong, Yuan %D 1993 %T Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation %I IEEE %C Beijing, China %V 5 %P 1206 %K advanced processor architecture; multimedia; parallel processing ; distributed systems; multiprocessing systems; object-oriented software; databases; programming languages; computation theory; network design; VLSI design; artificial intelligence; CAD/CAM; neural nets; image processing ; pattern recognition; telecommunication; spread spectrum communication; mobile radio; LAN; B-ISDN; speech coding; image communication; optical communication; DSP; stability analysis; CIM; robotics; optimal control; robust control; fuzzy control; intelligent control; adaptive control; power system control; energy management; power system dynamics; relay protection; voltage control; power system planning; high voltage techniques; motor drives ARTIFICIAL INTELLIGENCE; CIRCUIT CAD; COMPUTER SCIENCE; CONTROL ENGINEERING; POWER SYSTEMS; SIGNAL PROCESSING; TELECOMMUNICATION %X The following topics were dealt with: advanced processor architecture; multimedia and applications; parallel processing; distributed systems; multiprocessing systems; object-oriented software; databases; programming languages; computation theory; network design; VLSI design; artificial intelligence; CAD/CAM; neural nets; image processing ; pattern recognition; telecommunication; spread spectrum communication; mobile radio; LAN; B-ISDN; speech coding; image communication; optical communication; DSP; stability analysis; CIM; robotics; optimal control; robust control; fuzzy control; intelligent control; adaptive control; power system control; energy management; power system dynamics; relay protection; voltage control; power system planning; high voltage techniques; and motor drives. %0 Journal Article %A Barbacci, M.R. %D 1981 %T Instruction Set Processor Specifications (ISPS): The Notation and Its Application %J IEEE Transactions on Computers %V C-30 %N 1 %P 24-40 %0 Journal Article %A Barnard, S. T. %A Fischler, M. A. %D 1982 %T Computational stereo %J Computing Surveys %V 14 %N 4 %P 554-572 %0 Journal Article %A Barnard, E. %D 1988 %T Optimal error diffuction for computer-generated holograms %J Journal of the Optical Society of America (A) %V 5 %N 11 %P 1803-17 %0 Conference Proceedings %A Barnard, S. %D 1990 %T Recent Progress in CYCLOPS: A System for Stereo Cartography %J Image Understanding Workshop %I Defense Advanced Research Projects Agency %C Pittsburgh, PA %P 449-55 %0 Book %A Barnum, A.A. %A Knapp, M.A. (editors) %D 1963 %T Proceedings of the 1962 Workshop on Computer Organization %I Spartan Books, Inc. %0 Conference Proceedings %A Baron, Thierry %A Levine, Martin D. %A Yeshurun, Yehecekel %D 1994 %T Exploring with a Foveated Robot Eye System %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 377-380 %0 Conference Proceedings %A Barton, E. %A Roweth, D. %D 1988 %T The Computing Surface %J International Specialist Seminar on the Design and Application of Parallel Digital Processors %C Lisbon, Portugal %P 139-42 %0 Conference Proceedings %A Basille, J. L. %A Houatra, D. %A Padiou, G. %D 1993 %T A high-level MIMD programming tool for image understanding algorithms %J Proceedings Tencon '93 %E Baozong, Yuan %I IEEE %C Beijing, China %6 5 %P 898-901 %X Image understanding algorithms involve different parallel architectures. Among them, there is MIMD computers for the purpose of executing complex algorithms. Unfortunately, programming such computers is difficult. A high-level MIMD programming tool based on the Linda programming paradigm is presented which can be used to implement parallel image understanding algorithms easily and efficiently. We describe the implementation of this software on a message passing multicomputer. The overhead of the primitives and the experiences with two well known problems are presented for providing an idea of the practicability of the system. %0 Conference Proceedings %A Baskett, F. %D 1981 %T Designing a VLSI Processor - Aids and Architectures %J VLSI Systems and Computations %P 20 %0 Journal Article %A Bastiaens, K. %A Lemahieu, I. %A Desmedt, P. %D 1994 %T On the use of a multi-threaded operating system for an efficient parallel implementation of the ML-EM algorithm for PET image reconstruction %J Ifip Transactions A %V 44 %P 31-9 %X Multi-threaded operating systems were introduced in the quest to reduce the overhead caused by task manipulation and synchronization. An example is the recently introduced Solaris 2.2 multi-threaded operating system. In this paper, a parallel application in the domain of positron emission tomography (PET) image reconstruction is presented, for which a successful use of the multi-threaded approach has led to an implementation, with a nearly linear speedup, of the maximum likelihood expectation maximalization (ML-EM) algorithm. %0 Conference Proceedings %A Bastiaens, K. %A Lemahieu, I. %D 1994 %T A parallel implementation of the ML-EM reconstruction algorithm for PET images in a visual language %J Hybrid Image and Signal Processing IV %I SPIE %C Orlando, FL %P 176-83 %X Due to its iterative nature, the execution of the maximum likelihood expectation maximization (ML-EM) reconstruction algorithm requires a long computation time. To overcome this problem multiprocessor machines could be used. In this paper a parallel implementation of the algorithm for positron emission tomography (PET) images is presented. To cope with the difficulties involved with parallel programming a programming environment based on a visual language has been used. %0 Journal Article %A Batcher, K.E. %D 1968 %T Sorting Networks and Their Applications %J 1968 Spring Joint Computer Conference %V 32 %P 307-314 %0 Journal Article %A Batcher, K. E. %D 1980 %T Design of a Massively Parallel Processor %J IEEE Transactions on Computing %V C-29 %P 836-840 %0 Journal Article %A Batcher, K.E. %D 1982 %T Bit-serial Parallel Processing Systems %J IEEE Trans. Computer %V C-31 %N 5 %P 377-384 %0 Journal Article %A Baudet, G. %A Stevenson, D. %D 1978 %T Optimal Sorting Algorithms for Parallel Computers %J IEEE Transactions on Computers %V C-27 %N 1 %P 84-87 %0 Journal Article %A Baudet, G. %A Brent, R.P. %A Kung, H.T. %D 1980 %T parallel Execution of a Sequence of Tasks on an Asynchronous Multiprocessor %J The Australian Computer Journal %V 12 %P 105-112 %0 Conference Proceedings %A Baudet, G.M. %D 1981 %T On the Area Required by VLSI Circuits %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 100-107 %0 Journal Article %A Bauer, M. A. %A Feeney, S. T. %A Gargantini, I. %D 1994 %T Parallel 3-D filling with octrees %J Journal of Parallel and Distributed Computing %V 22 %N 1 %P 121-8 %X There are a number of different algorithms which attempt to perform the reconstruction of a volume representation (filling) of an object given some level of border representation for the object. These algorithms usually fall into two main categories: connectivity labeling, which digitizes polygons in space and fills the corresponding enclosed volumes, and filling by quadrants or octants which finds the interior of a previously digitized border. An algorithm in the second category presented by Atkinson, Gargantini and Walsh (1986) encodes information within the border elements of an object indicating in which direction the outer normal points at that point on the edge (for 2-D objects) or surface (for 3-D objects) of the object. This paper described a parallel algorithm that has been developed based on this approach using the shared memory, multiprocessor model and reports on its implementation. %0 Journal Article %A Baum, Daniel R. %A Winget, James M. %D 1990 %T Real Time Radiosity Through Parallel Processing and Hardware Accelaration %J Computer Graphics %V 24 %N 2 %P 67-75 %0 Conference Proceedings %A Baxter, B. %A Cox, G. %A Gross, T. %A Kung, H. T. %A O'Hallaron, D. %A Peterson, C. %A Webb, J. %A Wiley, P. %D 1990 %T Building Blocks for a New Generation of Application-Specific Computing Systems %J International Conference on Application Specific Array Processors %C Princeton, NJ %0 Journal Article %A Bayer, R. %A Haerder, T. %D 1978 %T Preplanning of Disk Merges %J Computing %V 21 %N 1 %P 1-16 %0 Generic %A BBN Laboratories %D 1985 %T The Uniform System Approach to Programming the Butterfly Parallel Processor %7 1 %9 Computer manual %0 Generic %A BBN Laboratories %D 1986 %T Butterfly Parallel Processor Overview %9 BBN Advanced Computers Inc. %0 Conference Proceedings %A Beke %A Herman %A Sansen, Willy %D 1979 %T CALMOS: A Portable Software System for the Automatic and Interactive Layout of MOS LSI %J Sixteenth Design Automation Conference %0 Report %A Belloch, G. E. %D 1992 %T A Nested Data-Parallel Language %I Carnegie Mellon University, School of Computer Science %R CMU-CS-92-103 %0 Generic %A Bentley, J.L. %A Ottmann, T. %A Widmayer, P. %T The complexity of manipulating hierarchically defined sets of rectangles %0 Conference Proceedings %A Bentley, J.L. %A Kung, H.T. %D 1979 %T A Tree Machine for Searching Problems %J Proceedings of 1979 International Conference on Parallel Processing %P 257-266 %0 Journal Article %A Bentley, J.L. %D 1980 %T A Parallel Algorithm for Constructing Minimum Spanning Trees %J Journal of Algorithms %V 1 %P 51-59 %0 Journal Article %A Bentley, J.L. %A Wood, D. %D 1980 %T An Optimal Worst-Case Algorithm for Reporting Intersections of Rectangles %J IEEE Transactions on Computers %V C-29 %0 Conference Proceedings %A Bentley, J.L. %A Haken, D. %A Hon, R. %D 1980 %T Fast Geometric Algorithms for VLSI Tasks %J COMPCON Spring '80 %0 Report %A Bentley, J.L. %A Haken, D. %A R.W., Hon %D 1980 %T Statistics on VLSI Designs %0 Conference Proceedings %A Bentley, J.L. %A Ottmann, T. %D 1981 %T The complexity of manipulating hierarchically defined sets of rectangles %J Tenth Symposium on Mathematical Foundations of Computer Science %0 Journal Article %A Bentley, J.L. %A Kung, H.T. %D 1983 %T An Introduction to Systolic Algorithms and Architectures %J Naval Research Reviews %V XXXV %N Two %P 3-16 %0 Journal Article %A Bentley, J. %D 1986 %T Little Languages %J Communications of the ACM %V 29 %N 8 %P 711-21 %0 Journal Article %A Berglend, Glenn D. %D 1969 %T Fast Fourier Transform Hardware Implementations - an Overview %J IEEE Transactions on Audio Electroacoustics %V AU-17 %P 104-108 %0 Conference Proceedings %A Bernard, T. %A Garda, P. %A Reichart, A. %A Zavidovique, B. %A Devos, F. %D 1988 %T Design of a Half-toning Integrated Circuit Based on Analog Quadratic Minimization by Non Linear Multistage Switched Capacitor Network %J IEEE International Symposium on Circuits and Systems %C Espoo, Finland %P 1217-20 %0 Report %A Bertero, M. %A Poggio, T. %A Torre, V. %D 1987 %T Ill-posed problems in early vision %I Artificial Intelligence Laboratory, Massachusetts Institute of Technology %R 924 %0 Conference Proceedings %A Bhandarkar, Suchendra M. %A Arabnia, Hamid R. %D 1994 %T Parallelizations of Computer Vision Algorithms on a Reconfigurable Multiprocessor %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 240-244 %0 Conference Proceedings %A Bigiliardo, M. %A Furnari, M. Mango %T Vision Analysis: A Testbed for Structured Parallelism Programming %J PF-ISCP RT.4 ??? %C Spain? %0 Conference Proceedings %A Bilardi, G. %A Pracchi, M. %A Preparata, F.P. %D 1981 %T A Critique and an Appraisal of VLSI Models of Computation %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 81-88 %0 Conference Proceedings %A Bimbo, A. Del %A Nesi, P. %D 1993 %T Optical Flow Estimation on the Connection-Machine CM-2 %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 267-274 %0 Conference Proceedings %A Binacardi, A. %A Rubini, A. %D 1994 %T PACCO - A New Approach for an Effective I.P. Environment %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 395-398 %0 Book %A Bindo, K. %D 1978 %T Monte Carlo Methods in Statistical Physics %I Spring-Verlag %0 Conference Proceedings %A Bischof, H. %A Kropatsch, W. G. %D 1993 %T Neural networks versus image pyramids %J Artificial Neural Nets and Genetic Algorithms. Proceedings of the International Conference %P 145-53 %X Neural networks and image pyramids are massively parallel processing structures. In this paper, we exploit the similarities as well as the differences between these structures. The general goal is to exchange knowledge between these two fields. After introducing the basic concepts of neural networks and image pyramids we give a translation table of the vocabulary used in image pyramids and those used in neural networks. Image pyramids which store and process numerical information (e.g. grey values of pixels) are very similar to neural networks. Therefore we concentrate on 'symbolic pyramids'. The main idea is to replace a cell of the pyramid by a small neural network, in order to represent and process symbolic information. We consider local as well as distributed representations for symbolic information. In particular we present a neural implementation of the 2*2/2 curve pyramid. We derive some general rules for implementing symbolic pyramids by neural networks. Finally we briefly discuss the role of learning in image pyramids. %0 Conference Proceedings %A Bischof, Horst %A Bertin, Etienne %A Bertolino, Pascal %D 1994 %T Voronoi Pyramids and Hopfield Networks %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 330-333 %0 Conference Proceedings %A Bisiani, B. %A Foster, M.J. %A Kung, H.T. %A Oflazer, K. %D 1982 %T MISE: Machine for In-System Evaluation of Custom VLSI Chips for Real-Time Systems %J Proceedings of Real-Time Systems Symposium %P 211-220 %0 Journal Article %A Biswas, P. K. %A Chatterji, B. N. %D 1994 %T Surface description in range images-a parallel approach %J Indian Journal of Pure and Applied Mathematics %V 25 %N 1-2 %P 205-30 %K range images; surface description; parallel rule based system ; structural shape; 3-D objects approach; mathematical analysis; qualitative reasoning; special purpose shared memory architecture %X This paper describes a parallel rule based system which obtains a structural shape from range images. The system uses a hierarchical description of 3-D objects approach to obtain higher level surface description from lower level ones. Instead of a detailed mathematical analysis, qualitative reasoning by rule based deduction is used to obtain the surface description. The rule bases are also hierarchical. A special purpose shared memory architecture is suggested which supports parallel application of rules. %0 Journal Article %A Bitz, F. %A Kung, H. T. %D 1988 %T Path planning on the Warp computer: using a linear systolic array in dynamic programming %J International Journal of Computer Mathematics %V 25 %N 3-4 %0 Conference Proceedings %A Blackmer, J. %A Frank, G. %A Kuekes, P. %D 1981 %T A 200 Million Operations per Second (MOPS) Systolic Processor %J Proceedings of SPIE Symposium, Vol. 298, Real-Time Signal Processing IV %P 10-18 %0 Conference Proceedings %A Blank, T. %D 1990 %T The MASPAR MP-1 Architecture %J Thirty-Fifth IEEE Computer Society International Conference - Compcon Spring 90 %C San Francisco, CA %P 20-4 %0 Report %A Blankenship, P.E. %D 1981 %T Restructurable VLSI Program %0 Journal Article %A Blelloch, G. %D 1989 %T Scans as Primitive Parallel Operations %J IEEE Transactions on Computers %V 38 %N 11 %P 1526-1538 %0 Personal Communication %A Blelloch, G. %D 1990 %X Commented that the best algorithm for connected components on the Connection Machine (2) was based on scans and simply propagating labels in multiple directions, not anything fancy. %0 Book %A Blelloch, G. %D 1990 %T Vector Models for Data-Parallel Computing %I MIT Press %0 Conference Proceedings %A Blelloch, G. %A Chatterjee, S. %D 1990 %T VCODE: A data-parallel intermediate language %J IThird Symposium on the Frontiers of Massively Parallel Computing %P 471-80 %0 Journal Article %A Blelloch, G. E. %A W., Sabot G. %D 1990 %T Compiling collection-oriented languages onto massively parallel computers %J Journal of Parallel and Distributed Computing %V 8 %N 2 %P 119-34 %0 Journal Article %A Blelloch, Guy E. %A Hardwick, Jonathan C. %A Sipelstein, Jay %D 1994 %T Implementation of a Portable Nested Data-Parallel Language. %J Journal of parallel and distributed computing %V 21 %N 1 %P 4-14 %0 Journal Article %A Bojanczyk, A. %A Brent, R.P. %A Kung, H.T. %D 1984 %T Numerically Stable Solution of Dense Systems of Linear Equations Using Mesh-Connected Processors %J SIAM Journal on Scientific and Statistical Computing %V 5 %N 1 %P 95-104 %0 Journal Article %A Bolles, R. C. %A Horaud, P. %D 1986 %T 3DPO: A Three-Dimensional Part Orientation System %J International Journal of Robotics Research %V 5 %N 3 %P 3-26 %0 Report %A Bonneau, R.J. %D 1973 %T A Class of Finite Computation Structures Supporting the Fast Fourier Transform %0 Conference Proceedings %A Bono, C. M. %A Webb, J. A. %D 1988 %T Object Recognition on a Systolic Array %J Third International Conference on Supercomputing %E Kartashev, Lana Kartashev and Steven %I International Supercomputing Institute, Inc. %C Boston, MA %0 Report %A Bono, C. M. %A Webb, J. A. %D 1988 %T Object Recognition on a Systolic Array %I Robotics Institute, Carnegie Mellon University %8 1987 %R CMU-RI-TR-87-21 %0 Conference Proceedings %A Borkar, S. %A Cohn, R. %A Cox, G. %A Gleason, S. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Moore, B. %A Peterson, C. %A Pieper, J. %A Rankin, L. %A Tseng, P. S. %A Sutton, J. %A Urbanski, J. %A Webb, J. %D 1988 %T iWarp: An Integrated Solution to High-Speed Parallel Computing %J Proceedings of Supercomputing '88 %C Orlando, Florida %P 330-339 %0 Conference Proceedings %A Borkar, S. %A al., et %D 1990 %T Supporting Systolic and Memory Communication in iWarp %J 17th Annual International Symposium on Computer Architecture %C Seattle, Washington %0 Conference Proceedings %A Borkar, S. %A Cohn, R. %A Cox, G. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Levine, M. %A Moore, B. %A Peterson, C. %A Susman, J. %A Sutton, J. %A Urbanski, J. %A Webb, Jon A. %D 1990 %T Supporting Systolic and Memory Communication in iWarp %J 17th International Symposium on Computer Architecture %C Seattle, WA %0 Conference Proceedings %A Borodin, A. %A von zur Gathen, J. %A Hopcroft, J. %D 1982 %T Fast Parallel Matrix and GCD Computations %J Proceedings of the 23rd Annual Symposium on Foundations of Computer Science %P 65-71 %0 Conference Proceedings %A Boulanger, P. %A Blais, F. %D 1993 %T Range image segmentation, free space determination, and position estimate for a mobile vehicle %J Mobile Robots VII. %I SPIE %C Boston, MA %P 444-55 %X Two processing methods using range data are shown to perform different navigation tasks for a mobile vehicle. The first, a low-level processing method based on mathematical morphology, computes in real time, the free space and is used for collision avoidance. A parallel between this method and polar histogram techniques is drawn. The second method, based on a hierarchical segmentation technique, can extract a multiple resolution description of the range data produced by the sensor. This segmentation is used to describe the immediate environment of the vehicle using simple geometrical primitives, refine the vehicle position estimate, and create a detailed representation of the immediate environment of the vehicle. Experimental results using the BIRIS range sensor are shown. %0 Conference Proceedings %A Bourdon, O. %A Medioni, G. %D 1990 %T Object Recognition Using Geometric Hashing on the Connection Machine %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 596-600 %0 Conference Proceedings %A Bove, V. M. Jr %D 1993 %T Hardware and software implications of representing scenes as data %J Icassp %I IEEE %C Minneapolis, MN %6 5 %P 121-4 %X Digital video is often perceived as valuable for reasons of data compression and robustness against noise, but it is less often considered that a fairly complex computational device mediates between the stored or transmitted bit stream and the display. The author explores some of the possibilities inherent in the source-to-display decoupling made possible in a digital video system, and examines the implications for both the digital video representation and the decoding device. The essential idea is to use the computation involved in both creating and decoding the bit stream to decouple the origination of the imagery from its ultimate viewing. A general-purpose CPU was combined with several specialized coprocessors and a full crosspoint switch, allowing both pipelining and parallel processing to take place between the communications channel and the display. This architecture has been realized in the Cheops Imaging System described by the author and J.A. Watlington (Proc. SPIE-Int. Soc. Opt. Eng., vol. 1605, p. 886-93 of 1991) which comprises a hardware and software architecture for processing image sequence data and structured scene representations in real time. %0 Book %A Bowen, B.A. %A Brown, W.R. %D 1982 %T Signal Processing and Signal Processors %I Prentice-Hall, Inc. %C Englewood Cliffs, New Jersey %V 1 %0 Conference Proceedings %A Box, B. %D 1994 %T Field programmable gate array based reconfigurable preprocessor %J Proceedings Ieee Workshop on FPGAs for Custom Computing Machines %E Buell, D.A. %E Pocek, K.L. %I IEEE Computer Society Press %C Napa Valley, CA %P 40-8 %X Custom hardware implementations of preprocessors are seldom reusable, flexible enough to allow algorithm exploration or quickly realized. The Configurable Hardware Algorithm Mappable Preprocessor (CHAMP) technology is a solution to these problems. Recent developments in FPGA hardware and software have made a reconfigurable preprocessor with custom hardware performance but generic hardware flexibility possible. The key advancements are larger, faster RAM and electrically erasable devices, routers with deadline timers, and synthesis tools which can work with user-definable macros. Ongoing work in the areas of partitioning, synthesis, placement, packaging and compilation will make reconfigurable preprocessors more powerful. The present CHAMP implementation is based on Xilinx FPGAs. Its architecture consists of multiple reconfigurable processing elements connected through both a ring network and a global crossbar network. It is packaged as a VME 6U*160 slave board with two high-speed reconfigurable parallel interfaces. In order to allow development at the algorithm level while retaining preprocessor performance, off-the-shelf development tools have been integrated with a custom library of macros as part of the CHAMP design process. As a verification of the CHAMP technology, an advanced IR missile warning application was mapped onto the CHAMP architecture achieving greater than 1 billion operations/sec of real-time throughput while utilizing 75% of the CHAMP board's processing resources. %0 Journal Article %A Boyer, R. S. %A Moore, J. S. %D 1977 %T A Fast String Searching Algorithm %J Communications of the ACM %V 20 %N 10 %P 762 %0 Journal Article %A Bozkus, Zeki %A Choudhary, Alok %A Fox, Geoffrey %D 1994 %T Compiling Fortran 90D/HPF for Distributed Memory MIMD Computers %J Journal of parallel and distributed computing %V 21 %N 1 %P 15-26 %0 Conference Proceedings %A Brady, M. %A Brint, A. %A Dickson, W. %A Foulkes, P. %A McIvor, A. %A Scott, G. %D 1988 %T Vision and the Oxford AGV %J Image Processing '88 %C London, UK %0 Book Section %A Brady, M. %A Scott, G. %D 1988 %T Parallel Algorithms for Shape Representation %B Parallel Architectures and Computer Vision %E Page, I. %I Oxford Science %P 97-118 %0 Conference Proceedings %A Brady, M. L. %A Yong, W. %D 1992 %T Fast parallel discrete approximation algorithms for the radon transform %J Spaa '92. 4th Annual Acm Symposium on Parallel Algorithms and Architectures %I ACM %C San Diego, CA %P 91-9 %X Addresses fast parallel methods for the computation of the radon (Hough) transform (RT). The RT of an image is a set of projections of the image taken at different angles. Its computation is extremely important in image processing and computer vision, for problems such as pattern recognition and reconstruction of CAT scan images. We present a unique new method for combining partial results which allows us to construct a parallel algorithm which computes an approximation to the RT in O(log N) time for an N*N input array, using O(N/sup 2/) processors. This is a lower processor-time product than all previous techniques. The method appears to be quite simple and practical. In addition, this algorithm appears to be quite well-suited to implementation on strict SIMD array-type computers. We discuss SIMD- parallel mappings of the algorithm for mesh, butterfly, and hypercube architectures. %0 Journal Article %A Brent, R. P. %D 1970 %T On the addition of binary numbers %J IEEE Transactions on Computers %V C-19 %P 758-759 %0 Conference Proceedings %A Brent, R.P. %D 1976 %T The Complexity of Multiple-precision Arithmetic %J The Complexity of Computational Problem Solving %E Anderssen, R.S. and Brent, R.P. %C Brisbane, Australia %P 126-165 %0 Conference Proceedings %A Brent, R.P. %D 1976 %T Analysis of the Binary Euclidean Algorithm %J New Directions and Recent Results in Algorithms and Complexity %E Traub, J.F. %I Academic Press %P 321-355 %0 Journal Article %A Brent, R.P. %D 1980 %T An Improved Monte Carlo Factorization Algorithm %J BIT %V 20 %P 176-184 %0 Journal Article %A Brent, R.P. %A Kung, H.T. %D 1980 %T On the Area of Binary Tree Layouts %J Information Processing Letters %V 11 %N 1 %P 46-48 %0 Conference Proceedings %A Brent, R.P. %A Kung, H.T. %D 1980 %T The Chip Complexity of Binary Arithmetic %J Proceedings of the Twelfth Annual ACM Symposium on Theory of Computing %P 190-200 %0 Journal Article %A Brent, R.P. %A Gustavson, F.G. %A Yun, D.Y.Y. %D 1980 %T Fast Solution of Toeplitz Systems of Equations and Computation of Pade Approximants %J Journal of Algorithms %V 1 %N 3 %P 259-295 %0 Journal Article %A Brent, R.P. %A Kung, H.T. %D 1981 %T The Area-Time Complexity of Binary Multiplication %J Journal of the ACM %V 28 %N 3 %P 521-534 %0 Journal Article %A Brent, R.P. %A Pollard, J.M. %D 1981 %T Factorization of the Eighth Fermat Number %J Math. Comp. %V 36 %P 627-630 %0 Journal Article %A Brent, R.P. %A Kung, H.T. %D 1982 %T A Regular Layout for Parallel Adders %J IEEE Transactions on Computers %V C-31 %N 3 %P 260-264 %0 Report %A Brent, R.P. %A Kung, H.T. %D 1982 %T Systolic VLSI Arrays for Integer GCD Computation %0 Report %A Brent, R.P. %A Luk, F.T. %D 1982 %T A Systolic Architecture for Almost Linear-Time Solution of the Symmetric Eigenvalue Problem %0 Report %A Brent, R.P. %A Luk, F.T. %D 1982 %T A Systolic Architecture for the Singular Value Decomposition %0 Journal Article %A Brent, R.P. %A Luk, F.T. %D 1983 %T A Systolic Array for the Linear-Time Solution of Toeplitz Systems of Equations %J Journal of VLSI and Computer Systems %V 1 %N 1 %P 1-22 %0 Conference Proceedings %A Brent, R.P. , Kung, H.T. %A Luk, F.T. %D 1983 %T Some Linear-Time Algorithms for Systolic Arrays %J Proceedings of the IFIP 9th World Computer Congress %E Mason, R. %P 865-876 %0 Conference Proceedings %A Brent, R.P. %A Luk, F.T. %A Van Loan, C. %D 1983 %T Computation of the Generalized Singular Value Decomposition Using Mesh-Connected Processors %J Proceedings of SPIE Symposium, Vol. 431, Real-Time Signal Processing VI %P 66-71 %0 Journal Article %A Brent, R.P. %A Kung, H.T. %D 1984 %T Systolic VLSI Arrays for Polynomial GCD Computation %J IEEE Transactions on Computers %V C-33 %N 8 %P 731-736 %0 Book %A Brigham, E. %D 1974 %T The Fast Fourier Transform %I Prentice Hall %C Englewood Cliffs, New Jersey %0 Conference Proceedings %A Bromley, K. %A Symanski, J.J. %A Speiser, J.M. %A Whitehouse, H.J. %D 1981 %T Systolic Array Processor Developments %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 273-284 %0 Conference Proceedings %A Bromley, M. %A Heller, S. %A McNerney, T. %A Steele, G., Jr. %D 1991 %T Fortran at Ten Gigaflops: The Connection Machine Convolution Compiler %J ACM SIGPLAN '91 Conference on Programming Language Design and Implementation %C Toronto, Canada %P 145-54 %0 Journal Article %A Bronson, E. C. %A Casavant, T. L. %A Jamieson, L. H. %D 1990 %T Experimental Application-Driven Architecture Analysis of an SIMD/MIMD Parallel Processing System %J Transacation on Parallel and Distributed Systems %V 1 %P 195-205 %0 Journal Article %A Brooks, Rodney A. %D 1986 %T A Robust Layered Control System for a Mobile Robot %J IEEE Journal of Robotics and Automation %V RA-2 %N 1 %P 14-23 %0 Conference Proceedings %A Brown, D.J. %A Rivest, R.L. %D 1981 %T New Lower Bounds for Channel Width %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 178-185 %0 Conference Proceedings %A Brown, Christopher M. %D 1988 %T Parallel Vision with the Butterfly Computer %J Third International Conference on Supercomputing %C Boston, MA %P 54-68 %0 Personal Communication %A Brown, Christopher %D 1994 %T Personal Communication. Comments on active vision and parallel systems. %8 February 23 %9 Electronic mail %0 Journal Article %A Brown, J. %A Crookes, D. %D 1994 %T A high level language for parallel image processing %J Image and Vision Computing %V 12 %N 2 %P 67-79 %X Most published research in the field of parallel image processing has tended to be in the areas of parallel architectures and parallel algorithms. Work on the development of software tools such as languages has generally been less extensive. This paper describes some research which is intended to redress the balance a little, by describing I-BOL-an application-specific high level programming language intended for implementing low-level image processing applications on parallel architectures. In particular, I-BOL has been designed to be capable of implementation on distributed memory parallel machines such as transputer networks. This paper introduces the core concepts of I-BOL: its view of an image as a set of tuples; user-defined neighbourhood functions; and I-BOL's facilities for recursive image processing. Solutions to a number of example problems illustrate particular aspects of the notation, including the distance transform, histogram equalization and the Hough transform. Some consideration is given to the parallel aspects of the current implementation of I-BOL on a pipeline of transputers. A few performance measurements are quoted, giving execution times for the chosen examples on various sizes of transputer work. %0 Generic %A Browning, S. %T Algorithms for the Tree Machine %0 Conference Proceedings %A Bruegge, B. %A Chang, C. %A Cohn, R. %A Gross, T. %A Lam, M. %A Lieu, P. %A Noaman, A. %A Yam, D. %D 1987 %T Programming Warp %J COMPCON Spring '87 %P 268-271 %0 Conference Proceedings %A Bruegge, B. %A Chang, C. %A Cohn, R. %A Gross, T. %A Lam, M. %A Lieu, P. %A Noaman, A. %A Yam, D. %D 1987 %T The Warp Programming Environment %J Proceedings of the 1987 National Computer Conference %P 141-148 %0 Conference Proceedings %A Bruegge, B. %A Gross, T. %D 1988 %T An Integrated Environment for Development and Execution of Real-Time Programs %J Conference Proceedings of 1988 International Conference on Supercomputing %I ACM %C St. Malo, France %P 153-162 %0 Conference Proceedings %A Brunzema, Martin %A Burmeiste, Horst %A Gerogiannis, Dimitris %D 1994 %T Parallelization of an Image Analysis Application: Problems, Results and a Solution Framework %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 406-411 %0 Conference Proceedings %A Brzakovic, D. %A Vujovic, N. %D 1994 %T Development Environment for Designing and Testing Inspection Systems %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 366-369 %0 Conference Proceedings %A Bucher, I. Y. %D 1983 %T The computational speed of supercomputers %J ACM SIGMETRICS Conference on Measurement and Modelling of Computer Systems %0 Journal Article %A Buell, D. A. %A Carlson, D. A. %A Chow, Y.-C. %A Culik, K. %A Deo, N. %A Finkel, R. %A Houstis, E. N. %A Jacobson, E. M. %A Kedem, Z. M. %A Kowalik, J. S. %A Kuekes, P. J. %A Martin, J. L. %A Michael, G. A. %A Ostlund, N. S. %A Potter, J. %A Pardhan, D. K. %A Quinn, M. J. %A Stewart, G. S. %A Stout, Q. F. %A Watson, L. %A Webb, J. %D 1988 %T Parallel algorithms and architectures: report of a workshop %J The Journal of Supercomputing %V 1 %P 301-325 %0 Journal Article %A Bulthoff, H. %A Little, J. %A Poggio, T. %D 1989 %T A Parallel Algorithm for Real-time Computation of Optical Flow %J Nature %V 337 %N 6207 %P 549-53 %0 Conference Proceedings %A Burt, P. J. %A van der Wal, G. S. %D 1987 %T Iconic Image Analysis with the Pyramid Vision Machine (PVM) %J 1987 Workshop on Computer Architecture for Pattern Analysis and Machine Intelligence %C Seattle, WA %P 137-44 %0 Conference Proceedings %A Burt, P. J. %A van der Wal, G. S. %D 1990 %T An Architecture for Multiresolution, Focal, Image Analysis %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 305-11 %0 Journal Article %A Butler, C. S. %A Miller, M. I. %A Miller, T. R. %A Wallis, J. W. %D 1994 %T Massively parallel computers for 3D single-photon-emission computed tomography %J Physics in Medicine and Biology %V 39 %N 3 %P 575-82 %K massively parallel computers ; 3D single photon emission computed tomography; expectation-maximization algorithm; maximum-likelihood estimates; maximum a posteriori estimates; SPECT; 3D reconstruction; computational complexity; 16,000 processor MasPar machine; Siemens Orbiter rotating camera; nuclear medicine; medical diagnostic imaging COMPUTERISED TOMOGRAPHY; IMAGE RECONSTRUCTION; MEDICAL IMAGE PROCESSING ; PARALLEL ALGORITHMS; RADIOISOTOPE SCANNING AND IMAGING %X Since the introduction of the expectation-maximization (EM) algorithm for generating maximum-likelihood (ML) and maximum a posteriori (MAP) estimates in emission tomography, there have been many investigators applying the ML method. However, almost all of the previous work has been restricted to two-dimensional (2D) reconstructions. The major focus and contribution of this paper is to demonstrate a fully three-dimensional (3D) implementation of the MAP method for single-photon-emission computed tomography (SPECT). The 3D reconstruction exhibits an improvement in resolution when compared to the generation of the series of separate 2D slice reconstructions. As has been noted, the iterative EM algorithm for 2D reconstruction is highly computational; the 3D algorithm is far worse. To accommodate the computational complexity, the authors have extended their previous work in the 2D arena and demonstrate an implementation on the class of massively parallel processors of the 3D algorithm. Using a 16,000 processor MasPar machine, the algorithm is demonstrated to execute at 1.24 S/EM iteration for the entire 64*64*64 cube of 64 planar measurements obtained from the Siemens Orbiter rotating camera operating in the high-resolution mode. %0 Book Section %A Buxton, B. F. %A Buxton, H. %A Kashko, A. %D 1988 %T Optimization Regularization and Simulated Annealing in Low-Level Computer Vision %B Parallel Architectures and Computer Vision %E Page, I. %I Oxford Science %P 1-18 %0 Conference Proceedings %A Buzbee, B. %A Golub, G. %A Howell, J. %D 1977 %T Vectorization for the CRAY-1 of Some Methods for Solving Elliptic Difference Equations %J High Speed Computer and Algorithm Organization %E Kuck, D. J., Lawrie, D. H. and Sameh, A. H. %I Academic Press %0 Conference Proceedings %A BŸker, Ulrich %A Martsching, BŠrbel %D 1994 %T A Communication Module for Parallel Image Analysis on the Transputer Image Processing System %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 327-329 %0 Conference Proceedings %A Camahort, Emilio %A Chakravarty, Indranil %D 1993 %T Inegrating Volume Data Analysis and Rendering on Distributed Memory Architectures %J Parallel Rendering Symposium %C San Jose, CA %P 89-96 %0 Journal Article %A Canny, J. %D 1986 %T A Computational Approach to Edge Detection %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 6 %N 6 %P 679-98 %0 Conference Proceedings %A Cantoni, V. %A Griffini, A. %A Lombardi, L. %D 1989 %T Stereo Vision in Multi-Resolution %J 5th International Conference on Image Analysis and Processing. Progress in Image Analysis and Processing %I World Scientific %C Positano, Italy %P 706-13 %0 Journal Article %A Cantoni, V. %A di Gesu, V. %A Ferretti, M. %A Levialdi, S. %A Negrini, R. %A Stefannelli, R. %D 1991 %T The PAPIA System %J Journal of VLSI Signal Processing %V 2 %N 4 %P 195-217 %0 Conference Proceedings %A Cantoni, V. %A Lombardi, L. %A Cinque, L. %A Levialdi, S. %A Guerra, C. %D 1994 %T Recognizing 2D Objects by a Multi-Resolution Approach %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 310-316 %0 Conference Proceedings %A Cappello, P.R. %A K., Steiglitz %D 1981 %T Digital Signal Processing Applications of Systolic Algorithms %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 245-254 %0 Conference Proceedings %A Carlsohn, M. F. %D 1992 %T Near real-time pattern recognition in a special purpose computer with parallel architecture %J Real Time Computing. Proceedings of the Nato Advanced Study Institute %E Halang, W.A. %E Stoyenko, A.D. %C Sint Maarten, Dutch Antilles %P 676-7 %K real-time pattern recognition; special purpose computer; parallel architecture ; image pattern recognition; features; object classification; computational complexity; time consumption; segmentation method; feature extraction FEATURE EXTRACTION; IMAGE PROCESSING EQUIPMENT; IMAGE RECOGNITION; IMAGE SEGMENTATION; PARALLEL ARCHITECTURES; REAL-TIME SYSTEMS; SPECIAL PURPOSE COMPUTERS %X In computer vision the term real-time possesses some uncertainty, because of the demands defined by standard camera sensors and the requirements of the processes under inspection sometimes differ by orders of magnitude. In image pattern recognition, the segmentation of interesting image objects from their image background and the characterization of the object properties by their features are the prerequisites for an object classification. Both process steps are usually of great computational complexity and time consumption, respectively. Consequently, processing in video real-time is only possible by a supporting computer architecture. The presented system is a hybrid hard- and software implementation of a region based and scan line-oriented segmentation method including an inherent feature extraction. A set of concurrent single processes are mapped onto an appropriate parallel processor architecture. %0 Report %A Cater, J. E. %A Sullivan, F. J. M. %D 1981 %T Processing architecture for sonobuoy thinned random array %0 Journal Article %A Caulfield, H.J. %A Rhodes, W.T. %A Foster, M.J. %A Horvitz, S. %D 1981 %T Optical Implementation of Systolic Array Processing %J Optics Communications %V 40 %N 2 %P 86-90 %0 Book %A Cavanagh, J.J.F. %D 1984 %T Digital Computer Arithmetic: Design and Implementation %I McGraw-Hill %C New York %0 Journal Article %A Cecchini, R. %A Bimbo, A. Del %D 1993 %T A Programming Environment for Imaging Applications %J Pattern Recognition Letters %V %P 877-881 %0 Conference Proceedings %A Chakrabarti, C. %A Ja Ja , J. F. %D 1990 %T A Parallel Algorithm for Template Matching on an SIMD Mesh Connected Computer %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 362-7 %0 Conference Proceedings %A Chalmers, Alan G. %A Paddon, Derek J. %D 1991 %T Parallel Processing of Pregressive Refinement Radiosity Methods %J Second Euorgraphics Workshop on Rendering %C Barcelona, Spain %0 Conference Proceedings %A Champeau, J. %A Le Pape, L. %A Pottier, B. %A Rubini, S. %A Gautrin, E. %A Perraudeau, L. %D 1994 %T Flexible parallel FPGA-based architectures with ArMen %J Proceedings of the Twenty Seventh Hawaii Internation Conference on System Sciences %E Mudge, T.N. %E Shriver, B.D. %I IEEE Comput. Soc. Press %C Wailea, HI %P 105-13 %K flexible parallel FPGA-based architectures ; ArMen; parallel machine ; global coprocessors; cellular automata; image processing ; industrial control; MADMACS pattern generator CELLULAR AUTOMATA; IMAGE PROCESSING ; LOGIC ARRAYS; PARALLEL ARCHITECTURES; PARALLEL MACHINES %X ArMen is a parallel machine in which each node is coupled to an FPGA ring. The underlying idea is to complement an MIMD architecture with global coprocessors providing extra control and processing properties. The use of regular hardware patterns such as cellular automata or pipelines allows high level definitions of the coprocessors. The results are fast prototyping possibilities for specific applications such as image processing or industrial control. Basic realizations are described. Changing from an FPGA technology to a VLSI one provider benefits with respect to cost and performance, without any effort at the specification level. The MADMACS pattern generator can be used to fold several FPGA configurations into the same VLSI circuit. %0 Conference Proceedings %A Chan, K. L. %A Tsui, W. M. %A Chan, H. Y. %A Wong, H. Y. %A Lai, H. C. %D 1993 %T Parallelising image processing algorithms %J Proceedings Tencon '93 %E Baozong, Yuan %I IEEE %C Beijing, China %6 5 %P 942-4 %X Multiprocessor machines provide increased computational power and memory capacity that can be used to achieve tasks involving large amounts of data, such as imaging . With multiprocessor machines, many sophisticated operations on image data can be accomplished within reasonable time constraints. In order to efficiently utilize multiprocessor machines, conventional image processing algorithms have to be parallelised. The design of parallel algorithms takes into account many considerations, e.g. interprocessor communication, load balancing, task division, task placement, scalability, network topology, etc. In this paper, the performance of some image processing algorithms running on a loosely-coupled multiprocessor machine is evaluated. The machine consists of a PC host computer and a multiprocessor network consisting of a number of transputers. The configuration of this transputer network is under software control and so different parallelisations of a particular algorithm can be tested on a particular network topology. Three image processing algorithms were selected for parallelisation. They are the Sobel edge operation, the fast Fourier transform and the Hough transform. Parallelism is achieved in various approaches, such as partitioning of tasks or partitioning of data. For a particular network configuration, the performance of different parallelisation approaches for each algorithm was assessed, based on the parallel processing time, overhead time, communication-to-computation ratio, efficiency, etc. %0 Journal Article %A Chanda, B. %A Haralick, R. M. %D 1994 %T Studies on properties of digital objects using mathematical morphology %J Indian Journal of Pure and Applied Mathematics %V 25 %N 1-2 %P 181-203 %K digital objects; mathematical morphology; geometric properties; connectivity; convexity; morphological operations; connectivity number; parallel machines ; image analysis; computer vision ; digital convexity %X Studies the geometric properties like connectivity and convexity of digital objects in terms of mathematical morphology. A new definition of digital convexity is suggested. Connectivity and convexity of digital objects obtained through morphological operations are investigated in the light of this new definition. The paper also presents some morphological algorithms for computing topological properties like connectivity number and genus. Operations are simpler, faster and can be implemented on parallel machines. %0 Generic %A Chang, T.L. %A Fisher, P. David %T Mixed Systolic Arrays: A Reconfigurable Multiprocessor Structure %0 Journal Article %A Charlesworth, A. E. %D 1981 %T An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family %J Computer %V 14 %P 18-27 %0 Conference Proceedings %A Chatterjee, S. %A Blelloch, G. E. %A Zagha, M. %D 1990 %T Scan Primitives for Vector Computers %J Supercomputing '90 %C Los Alamitos, CA %P 666-75 %0 Conference Proceedings %A Chatterjee, S. %A Blelloch, G. %A Fisher, A. %D 1991 %T Size and Access Inference for Data-Parallel Programs %J ACM SIGPLAN '91 Conference on Programming Language Design and Implementation %C Toronto, Canada %P 130-44 %0 Thesis %A Chatterjee, S. %D 1991 %T Compiling Data-Parallel Programs for Efficient Execution on Shared-Memory Multicomputers %I Carnegie Mellon University %8 October %0 Journal Article %A Chaudhary, V. %A Aggarwal, J. K. %D 1993 %T A Generalized Scheme for Mapping Parallel Algorithms %J IEEE Transactions on Parallel and Distributed Systems %V 4 %P 328-346 %0 Conference Proceedings %A Chazelle, B.M. %A Monier, L.M. %D 1981 %T A Model of Computation for VLSI with Related Complexity Results %J Proceedings of the 13th Annual ACM Symposium on the Theory of Computing %P 318-325 %0 Conference Proceedings %A Chazelle, B.M. %A Monier, L.M. %D 1981 %T Optimality in VLSI %J First International Conference on Very Large Scale Integration %P 269-278 %0 Conference Proceedings %A Chazelle, B.M. %A Monier, L.M. %D 1981 %T Unbounded Hardware is Equivalent to Deterministic Turing Machines %J First conference on Foundations of Software Technology and Theoretical Computer Science %0 Conference Proceedings %A Chazelle, B.M. %A Monier, L.M. %D 1981 %T Towards More Realistic Models of Computation for VLSI %J Proceedings of the Second Caltech VLSI Conference %0 Report %A Chazelle %A Bernard %D 1982 %T An Improved Algorithm for the Fixed-Radius Neighbor Problem %0 Report %A Chazelle %A Bernard %D 1982 %T Computational Geometry on a Systolic Chip %0 Report %A Chazelle %A Bernard %D 1982 %T The Bottom-Left Bin-Packing Heuristic: An Efficient Implementation %0 Report %A Chazelle %A Bernard %D 1982 %T The Polygon Containment Problem %0 Journal Article %A Chen, W.H. %A Smith, C.H. %A Fralick, S.C. %D 1977 %T A Fast Computational Algorithm for Discrete Cosine Transform %J IEEE Trans. on Communications %V COM-25 %P 1004-1009 %0 Conference Proceedings %A Chen, T.C. %A Lum, V.Y. %A Tung, C. %D 1978 %T The Rebound Sorter: An Efficient Sort Engine for Large Files %J Proceedings of the 4th International Conference on Very Large Data Bases %P 312-318 %0 Conference Proceedings %A Chen, M.C. %A Mead, C.A. %D 1983 %T A Hierarchical Simulator Based on Formal Semantics %J Proceedings of the Third Caltech Conference on Very Large Scale Integration %E Bryant, R. %I Computer Science Press, Inc. %P 207-223 %0 Generic %A Chen, M. %D 1986 %T Talk given at the ONR 1986 Workshop on Systolic Processing %0 Conference Proceedings %A Chen, K. %A Danielsson, P.-E. %A Astroem, A. %D 1990 %T PASIC. A Sensor/Processor Array for Computer Vision %J Application Specific Array Processors %C Princeton, N. J. %P 352-66 %0 Conference Proceedings %A Chen, J.-S. %A Medioni, G. %D 1990 %T Parallel Multiscale Stereo Matching using Adaptive Smoothing %J Computer Vision - ECCV 90: First European Conference on Computer Vision %C Antibes, France %P 99-103 %0 Conference Proceedings %A Chen, Ling Tony %A Davis, Larry S. %D 1991 %T Parallel Processing of Image Contours %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 169-176 %0 Conference Proceedings %A Chen, C. M. %A Lee, S. Y. %A Cho, Z. H. %D 1992 %T 3D PET image reconstruction on a mesh connected multiprocessor %J Conference Record of the IEEE Nuclear Science Symposium and Medical Imaging Conference %I IEEE %C Orlando, FL %P 915-17 %K wrapped-around 2D mesh system; positron emission tomography; nuclear medicine; iterative reconstruction; medical diagnostic imaging ; 3D PET image reconstruction; mesh connected multiprocessor; practical parallel system ; highly efficient parallel algorithms ; medical environment; parallel GTTR algorithm ; EM algorithm; data partitioning; partition-by-view; communication patterns COMPUTERISED TOMOGRAPHY; IMAGE RECONSTRUCTION; MEDICAL IMAGE PROCESSING ; PARALLEL ALGORITHMS; PARALLEL PROCESSING; RADIOISOTOPE SCANNING AND IMAGING %X The authors describe a practical parallel system and highly efficient parallel algorithms for 3-D PET (positron emission tomography) image reconstruction. The proposed parallel system, a wrapped-around 2-D mesh system, is compact enough for the medical environment and scalable for various PET sizes. This system is capable of performing both analytic and iterative reconstructions efficiently. The authors use the GTTR and EM (expectation maximization) algorithms for the analytic and iterative approaches, respectively. For the parallel GTTR algorithm, a wrapped-around 2-D mesh communication pattern is proposed. For parallelization of the EM algorithm, a new task and data partitioning scheme, called partition-by-view, has been developed. The partition-by-view scheme is more efficient than schemes proposed previously since some communication can be overlapped with computation by using a new communication pattern, called the multiple ring. Both communication patterns can be embedded in a wrapped-around 2-D mesh. The parallel GTTR algorithm and the partition-by-view scheme have been implemented using image sizes of 64*64*64 and 40*40*16, respectively. High efficiency, i.e., greater than 90%, has been achieved for most of the cases tested. %0 Journal Article %A Chen, C.-M. %A Lee, S.-Y. %D 1994 %T On Parallelizing the EM Algorithm for PET Image Reconstruction. %J IEEE transactions on parallel and distributed systems %V 5 %N 8 %P 860-873 %0 Journal Article %A Chen, Chung-Ming %D 1994 %T An inhomogeneous partitioning based parallel EM algorithm for 3D PET image reconstruction %J Biomedical Engineering, Applications Basis Communications %V 6 %N 1 %P 34-40 %X One of the problems which prevents PET from being widely used is the long processing time required for reconstruction of a PET image. While the expectation-maximization (EM) reconstruction guarantees to converge to an image with the maximum likelihood, it takes much more time than its counterpart, i.e. the analytic algorithms, e.g. the filtered backprojection algorithm. To make true 3D PET practical the authors present a new parallel EM algorithm for 3D image reconstruction. The proposed parallel EM algorithm is more efficient than others in that it minimizes data sharing overhead by replicating shared data optimally and overlapping integration and broadcasting of shared data with computation. In theory, the authors show that the maximal improvement achievable by the proposed parallel EM algorithm over a parallel EM algorithm using a homogeneous partitioning scheme with the same group size is at least 50%. %0 Conference Proceedings %A Chen, Sarit %A Ginosar, Ran %D 1994 %T Adaptive Sensitivity CCD Image Sensor %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 363-365 %0 Conference Proceedings %A Cheng, Y. %A Jensen, J. R. %A Huntsberger, T. L. %A Huntsberger, B. A. %D 1994 %T Hypercube algorithm for image component labeling %J Proceedings of the Scalable High Performance Computing Conference %I IEEE Computer Society Press %C Knoxville, TN %P 259-62 %K hypercube algorithm; image component labeling; connected regions; digitized image; image analysis; computer vision ; higher level image operations; parallel algorithm ; component labeling algorithm; parallelized hybrid; sequential algorithms; nCUBE/10 hypercube system; time complexity; storage utilization COMPUTER VISION ; DISTRIBUTED MEMORY SYSTEMS; HYPERCUBE NETWORKS; IMAGE PROCESSING ; PARALLEL ALGORITHMS %X Labeling the connected regions of a digitized image is a fundamental computation in image analysis and computer vision . By assigning a unique label to each connected region, higher level image operations can identify, extract, and process different connected regions separately. Because of its primary importance, the problem has attracted research in developing parallel algorithms. Most of the research has been theoretical in nature, with notable exceptions. We present a new component labeling algorithm that is a parallelized hybrid of the sequential algorithms of R.M. Haralick and L.G. Shapiro (1979) and A. Rosenfeld, J. Pfaltz (1966). Experimental studies on the nCUBE/10 hypercube system at the University of South Carolina show that the algorithm has a relatively efficient balance of time complexity and storage utilization. %0 Conference Proceedings %A Chiang, A.M. %D 1981 %T A New CCD Parallel Processing Architecture %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 408-415 %0 Generic %A Choudhary, Alok N. %A narahari, Bhagirath %A Nicol, David M. %A Simha, Rahul %T Optimal Processor Assignment for Series-Parallel Pipelined Computations %0 Book %A Choudhary, A. N. %A Patel, J. H. %D 1990 %T Parallel Architectures and Parallel Algorithms for Integrated Vision Systems %I Kluwer Academic %0 Journal Article %A Choudhary, A. N. %A Patel, J. H. %A Ahuja, N. %D 1993 %T NETRA: A Hierarchical and Partitionable Architecture for Computer Vision %J IEEE Transactions on Parallel and Distributed Systems %V %P 1092-1104 %0 Journal Article %A Choudhary, A. N. %A Narahari, B. %A Nicol, D. M. %A Simha, R. %D 1994 %T Optimal processor assignment for a class of pipelined computations %J Ieee Transactions on Parallel and Distributed Systems %V 5 %N 4 %P 439-45 %K pipelined computations; multitasked parallel architectures ; processor assignment problem; data dependencies; series-parallel partial order ; computer vision ; parallel analysis ; data sets; task structure; series-parallel task system ; series analysis PARALLEL ARCHITECTURES; PIPELINE PROCESSING; RESOURCE ALLOCATION %X The availability of large-scale multitasked parallel architectures introduces the following processor assignment problem. We are given a long sequence of data sets, each of which is to undergo processing by a collection of tasks whose intertask data dependencies form a series- parallel partial order. Each individual task is potentially parallelizable, with a known experimentally determined execution signature. Recognizing that data sets can be pipelined through the task structure, the problem is to find a "good" assignment of processors to tasks. Two objectives interest us: minimal response time per data set, given a throughput requirement, and maximal throughput, given a response time requirement. Our approach is to decompose a series- parallel task system into its essential "serial" and " parallel " components; our problem admits the independent solution and recomposition of each such component. We provide algorithms for the series analysis, and use an algorithm due to Krishnamurti and Ma for the parallel analysis. For a p processor system and a series- parallel precedence graph with n constituent tasks, we give a O(np/sup 2/) algorithm that finds the optimal assignment (over a broad class of assignments) for the response time optimization problem; we find the assignment optimizing the constrained throughput in O(np/sup 2/ log p) time. These techniques are applied to a task system in computer vision . %0 Conference Proceedings %A Chow, E. %A Madan, H. %A Peterson, J. %A Grunwald, D. %A Reed, D. %D 1988 %T Hyperswitch Network for the Hypercube Computer %J Conference Proceedings of the 15th Annual International Symposium on Computer Architecture %P 90-99 %0 Conference Proceedings %A Chuang, H. Y. H. %A Ling Chen, (. ). %A Ching, Chung Li %D 1993 %T A scalable VLSI parallel pipelined architecture for discrete wavelet transform %J Machine Vision Applications, Architectures, and Systems Integration II %I SPIE %C Boston, MA %P 7-9 %K scalable VLSI parallel pipelined architecture ; 1D discrete wavelet transform; signal analysis; image analysis; high frequency components; time resolution; low frequency components; localized contributions; multiscale analysis; parallel pipelined array processor ; multiple levels; speedup IMAGE PROCESSING ; IMAGE PROCESSING EQUIPMENT; PARALLEL ARCHITECTURES; PIPELINE PROCESSING; RECONFIGURABLE ARCHITECTURES; VLSI; WAVELET TRANSFORMS %X The discrete wavelet transform (DWT) provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a signal or an image into localized contributions for multiscale analysis. This paper presents a parallel pipelined array processor for 1D DWTs. Unlike other VLSI DWT processors, which processes signal data sequentially in a pipeline, this array processor can process all data in a signal segment in parallel and successive segments in the same pipeline which computes the multiple levels (octaves) of the DWT. The speedup is linearly proportional to the width of the array (or the size of a segment), and thus the architecture is scalable. %0 Journal Article %A Chung, Ming Chen %A Soo-Young Lee %D 1994 %T On parallelizing the EM algorithm for PET image reconstruction %J Ieee Transactions on Parallel and Distributed Systems %V 5 %N 8 %P 860-73 %X The expectation maximization (EM) algorithm is one of the most suitable iterative methods for positron emission tomography (PET) image reconstruction; however, it requires a long computation time and an enormous amount of memory space. To overcome these problems, we present two classes of highly efficient parallelization schemes: homogeneous and inhomogeneous partitionings. The essential difference between these two classes is that the inhomogeneous partitioning schemes may partially overlap the communication with computation by deliberate exploitation of the inherent data access pattern with a multiple-ring communication pattern. In theory, the inhomogeneous partitioning schemes may outperform the homogeneous partitioning schemes. However, the latter require a simpler communication pattern. In an attempt to estimate the achievable performance and to analyze the performance degradation factors without actual implementation, we have derived efficiency prediction formulas for closely estimating the performance for the proposed parallelization schemes. We propose new integration and broadcasting algorithms for hypercube, ring, and n-D mesh topologies, which are more efficient than the conventional algorithms when the link setup time is relatively negligible. The concept of the proposed task and data partitioning schemes, the integration and broadcasting algorithms, and the efficiency estimation methods can be applied to many other problems that are rich in data parallelism, but without balanced exclusive partitioning. %0 Journal Article %A Clark, J.H. %D 1980 %T A VLSI Geometry Processor for Graphics %J Computer %V 13 %N 7 %0 Journal Article %A Clark, J.H. %D 1982 %T The Geometry Engine: A VLSI Geometry System for Graphics %J Computer Graphics %V 16 %N 3 %P 127-133 %0 Conference Proceedings %A Clark, D. W. %D 1987 %T Pipelining and Performance in the VAX 8800 Processor %J Proceedings of Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II) %P 173-177 %0 Book %A Clark, A. %D 1991 %T Image Processing and Interchange (IPI), Part 1: Overview, Architecture, Profiles, Conformance; Working Draft %0 Book Section %A Clementi, E %A Chin, S. %A Corongiu, G. %A Detrich, J. H. %A Dupuis, M. %A Folsom, D. %A Lie, G. C. %A Logan, D. %A Sonnad, V. %D 1988 %T Supercomputing and Super Computers: for Science and Engineering in General and for Chemistry and Biosciences in Particular %B Biological and Artificial Intelligence Systems %I ESCOM Science Publishers B.V. %P 319-424 %0 Conference Proceedings %A Clermont, P. %A Merigot, A. %D 1987 %T Real Time Synchronization in a Multi-SIMD Massively Parallel Machine %J 1987 Workshop on Computer Architecture for Pattern Analysis and Machine Intelligence %C Seattle, WA %P 131-6 %0 Book Section %A Cloud, E. L. %D 1991 %T Geometric Arithmetic Parallel Processor: Architecture and Implementation %B Parallel Architectures and Algorithms for Image Understanding %I Academic Press %P 279-305 %0 Report %A Clune, E. %A Crisman, J. D. %A Klinker, G. J. %A Webb, J. A. %D 1987 %T Implementation and Performance of a Complex Vision System on a Systolic Array Machine %I Robotics Institute, Carnegie Mellon University %R CMU-RI-TR-87-16 %0 Conference Proceedings %A Clune, E. %A Crisman, J. D. %A Klinker, G. J. %A Webb, J. A. %D 1988 %T Implementation and Performance of a Complex Vision System on a Systolic Array Machine %J Future Generations Computer Systems %P 15-19 %0 Book %A Codd, E.F. %D 1968 %T Cellular Automata %I Academic Press %C New York %0 Journal Article %A Cohen, D. %D 1976 %T Simplified Control of FFT Hardware %J IEEE Transactions on Acoustics, Speech, and Signal Processing %V AU-24 %P 577-579 %0 Report %A Cohen, D. %D 1978 %T Mathematical Approach to Computational Networks %0 Conference Proceedings %A Cohen, D. %A Tyree, V.C. %D 1979 %T VLSI System for SAR Processing %J Proceedings of Conference on Very Large Scale Integration: Architecture, Design, Fabrication %0 Conference Proceedings %A Cohen, D. %A Lewicki, G. %D 1981 %T MOSIS -- The ARPA Silicon Broker %J Proceedings of the Second Caltech Conference on VLSI %0 Conference Proceedings %A Cohn, R. %A Kung, H. T. %A Menzilcioglu, O. %A Song, S. %D 1988 %T A Highly Reconfigurable Array of Powerful Processors %J SPIE Symposium, Vol. 975, Advanced Algorithms and Architectures for Signal Processing III %0 Conference Proceedings %A Cohn, R. %A Kung, H. T. %A Menzilcioglu, O. %A Song, S. W. %D 1988 %T A Highly Reconfigurable Array of Powerful Processors %J Proceedings of SPIE Symposium, Vol. 975, Advanced Algorithms and Architectures for Signal Processing III %P 336-343 %0 Conference Proceedings %A Cohn, R. %A Gross, T. %A Lam, M. %A Tseng, P. S. %D 1989 %T Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor %J Proceedings of Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS III) %0 Thesis %A Coletti, Neil Boyd %D 1983 %T Image processing on MPP-like arrays %I University of Illinois at Urbana-Champaign %9 Ph.D. %X Covers all the stages in the NASA thematic mapper algorithm -- determining warp, warp, etc. %0 Journal Article %A Collette, T. %A Essafi, H. %A Juvin, D. %A Kaiser, J. %D 1994 %T SYMPATIX: a SIMD computer performing the low and intermediate levels of image processing %J Future Generation Computer Systems %V 10 %N 1 %P 3-13 %K SYMPATIX; SIMD computer; image processing ; interconnection network; open intelligent network; SYMPTI2; hardware description language; VHDL IMAGE PROCESSING ; PARALLEL PROCESSING; PERFORMANCE EVALUATION %X This SIMD processor based system performs with a good efficiency the low level image processing operations, but this efficiency is drastically cut when handling an intermediate level class of algorithms. This study emphasises the drawbacks encountered to perform such operations. The main one is the interconnection between processors. So, a new interconnection network, called the open intelligent network, is proposed and added to SYMPTI2 to form SYMPATIX. This network allows irregular transfers of data between the different processing elements of the new system. Furthermore, this network allows the efficient interconnection of specific modules. The architecture is evaluated on representative algorithms of image processing . A behavioural model of SYMPATIX is described using a hardware description language, the VHDL. The SIMD computer efficiency has been considerably upgraded for the low and intermediate levels of image processing . Furthermore its application area is extended. The last part of the paper describes the performance obtained with simulations. %0 Book Section %A Condon, J.H. %A Thompson, K. %D 1982 %T Belle Chess Hardware %B Advances in Computer Chess 3 %E Clarke, M.R.B. %I Pergamon Press %P 45-54 %S Pergamon Chess Series %0 Journal Article %A Conway, L. %A A., Bell %A Newell, M.E. %D 1980 %T MPC79: The Large-Scale Demonstration of a New Way to Create Systems in Silicon %J LAMBDA %V 1 %N 2 %P 10-19 %0 Journal Article %A Cook, S.A. %A Sethi, R. %D 1976 %T Storage Requirements for Deterministic Polynomial Time Recognizable Languages %J J. Comp. and Sys. Sci. %V 13 %P 25-37 %0 Journal Article %A Copty, Nawal %A Ranka, Sanjay %A Fox, Geoffrey %D 1994 %T A Data Parallel Algorithm for Solving the Region Growing Problem on the Connection Machine %J Journal of parallel and distributed computing %V 21 %N 1 %P 160- %0 Conference Proceedings %A Corrie, Brian %A Mackerras, Paul %D 1993 %T Parallel Volume Rendering and Data Coherence %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, CA %P 23-26 %0 Conference Proceedings %A Corry, A. %A Patel, K. %D 1983 %T A CMOS/SOS VLSI Correlator %J Proceedings of 1983 International Symposium on VLSI Technology, Systems and Applications %P 134-137 %0 Conference Proceedings %A Cova, G. %A Griffini, A. %A Lombardi, L. %D 1989 %T Object Recognition Strategy in a Multi-Resolution System %J 5th International Conference on Image Analysis and Processing. Progress in Image Analysis and Processing %I World Scientific %C Positano, Italiy %P 729-33 %0 Generic %A Cox, G. %D 1991 %T Directions for iWarp Technology %C iWarp Forum, Hyatt Regency, Crystal City, Maryland %8 September 11, 1991 %9 Lecture %0 Conference Proceedings %A Cox, Michael %A Hanrahan, Pat %D 1993 %T Pixel Merging for Object-Parallel Rendering: A Distributed Network Snooping Algorithm %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, CA %P 49-56 %0 Journal Article %A Crisman, J. D. %A Webb, J. A. %D 1991 %T The Warp Machine on Navlab %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 13 %N 5 %P 451-65 %0 Book Section %A Crisman, J. D. %A Webb, J. A. %D 1991 %T The Warp Machine on Navlab %B Vision and Navigation: The Carnegie Mellon Navlab %E Thorpe, C. %I Kluwer %0 Conference Proceedings %A Crockett, Thomas W. %A Orloff, Tobias %D 1993 %T A MIMD Rendering Algorithm for Distributed Memory Architectures %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, CA %P 35-42 %0 Journal Article %A Crookes, D. %A Morrow, P. J. %A Scott, N. S. %A Kilpatrick, P. L. %D 1987 %T Notes on Implementing a Language for transputer Networks %J Microprocessing and Microprogramming %V 21 %P 558-66 %0 Report %A Crooks, P. %A Herrott, R. H. %D 1993 %T Language Constructs for Data Partitioning and Distribution %I Department of Computer Science, Queen's University of Belfast %0 Conference Proceedings %A Crowther, W. %A Goodham, J. %A Starr, E. %A Thomas, R. %A Milliken, W. %A Blackaden, T. %D 1985 %T Performance Measurements on a 128-Node Butterfly Parallel Processor %J International Conference on Parallel Processing %P 531-40 %0 Conference Proceedings %A Cuhadar, A. %A Downton, A. C. %D 1994 %T Scalable Parallel Processing Design for Real Time Handwritten OCR %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 339-341 %0 Journal Article %A Curd, J.R. %A Kirkham, C.C. %A Watson, I. %D 1985 %T The Manchester Prototype Dataflow Computer %J Communications of the ACM %V 28 %N 1 %P 34-52 %0 Journal Article %A Cypher, R. %A Sanz, J. %A Snyder, L. %D 1990 %T Algorithms for Image Component Labelling on SIMD Mesh-Connected Computer %J IEEE Transactions on Computers %V 39 %N 2 %P 276-81 %0 Conference Proceedings %A Cytron, R. %D 1986 %T Doacross: Beyond Vectorization for Multiprocessors %J 1986 International Conference on Parallel Processing %C St. Charles, Illinois %P 836-844 %0 Conference Proceedings %A ‚apin, Tolga K. %A Aykanat, Cevdet %A …zgŸ, BŸlent %D 1993 %T Progressive Refinement Radiosity on Ring-Connected Multicomputers %J Parallel Rendering Symposium %C San Jose, CA %P 71-76 %0 Conference Proceedings %A Dacic, S. %A Frecaut, J. M. %A Zavidovique, B. %D 1990 %T Software Environment for Complex Machine Programming %J COMPEURO '90:1990 IEEE International Conference on Computer Systems and Software Engineering %C Tel-Aviv, Israel %P 312-9 %0 Journal Article %A Dally, W. J. %A Seitz, C. L. %D 1986 %T The Torus Routing Chip %J Distributed Computing %V 1 %N 4 %P 187-196 %0 Book %A Dally %A J., William %D 1987 %T A VLSI Architecture for Concurrent Data Structures %I Kluwer Academic Publishers %0 Journal Article %A Dally, W.J. %A Seitz, C.L. %D 1987 %T Deadlock-Free Message Routing in Multiprocessor Interconnection Networks %J IEEE Transactions on Computers %V C-36 %N 5 %P 547-553 %0 Conference Proceedings %A Damianakis, Adam C. %A Orphanoudakis, Stelios C. %D 1991 %T The Influence of Image Content and Architectural Features on the Performance of Parallel Implementations %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 573-580 %0 Conference Proceedings %A Danielsson, P.-E. %A Lindskog, B. %A Segerstrom, J. %D 1988 %T PICAP3-A Coarse-Grain Linear SIMD-Array %J IAPR Workshop on Computer Vision: Special Hardware and Industrial Applications %C Tokyo, Japan %0 Journal Article %A Davidson, S. %A Landskov, D. %A Shriver, B.D. %A Mallett, P.W. %D 1981 %T Some Experiments in Local Microcode Compaction for Horizontal Machines %J IEEE Trans. on Computers %V C-30 %N 7 %P 460 - 477 %0 Conference Proceedings %A Deguchi, K. %A Tago, K. %A Morishita, I. %D 1990 %T Integrated Parallel Image Processings on a Pipelined MIMD Multi-Processor System PSM %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 442-4 %0 Journal Article %A Delingette, H. %A Hebert, M. %A Ikeuchi, K. %D 1992 %T Shape represenation and image segmentation using deformable surfaces %J Image and Vision Computing %V 10 %N 3 %P 132-144 %0 Conference Proceedings %A Delosme, J.-M. %A Ipsen, I. C. F %D 1986 %T Design Methodology for Systolic Arrays %J Proceedings of SPIE Symposium, Vol. 696, Advanced Algorithms and Architectures for Signal Processing %C San Diego, California %P 245-259 %0 Conference Proceedings %A Denneau, M. %D 1982 %T The Yorktown Simulation Engine %J Proceedings of the 19th Design Automation Conference %P 55-59 %0 Report %A Deutch, J. %A Maulik, P. C. %A Mosur, R. %A Printz, H. %A Ribas, H. %A Senko, J. %A Tseng, P. S. %A Webb, J. A. %A Wu, I-C. %D 1987 %T Performance of Warp on the DARPA Architecture Benchmarks %I Computer Science Department, Carnegie-Mellon University %R CMU-CS-87-148 %0 Conference Proceedings %A Deutch, J. %A Maulik, P. C. %A Mosur, R. %A Printz, H. %A Ribas, H. %A Senko, J. %A Tseng, P. S. %A Webb, J. A. %A Wu, I-C. %D 1988 %T Performance of Warp on the DARPA Architecture Benchmarks %J International Conference on Parallel Processing for Computer Vision and Display %C Leeds, England %0 Generic %A Dew, P. %A Chang, C.H. %D 1984 %T Passive Navigation by a Robot on the CMU Warp Machine %0 Conference Proceedings %A Dew, P. M. %A Wang, H. %D 1988 %T Data Parallelism and the Processor Farm Model for Image Processing and Synthesis on a transputer Array %J SPIE Symposium 977, Real Time Signal Processing XI %P 212-20 %0 Conference Proceedings %A Dew, P. M. %A Wang, H. %A Webb, J. A. %D 1989 %T APPLY: Machine independent image processing language and its implementation on a meiko computing surface %J Fifth Alvey Vision Conference %C Reading, England %0 Journal Article %A Dhond, U R %A Aggarwal, J K %D 1989 %T Structure from stereo - A review %J IEEE Transactions on Systems, Man, and Cybernetics %V 19 %N 6 %P 1489-1510 %0 Journal Article %A Dhond, U. R. %A Aggarwal, J. K. %D 1989 %T Structure from stereo - A review %J IEEE Transactions on Systems, Man, and Cybernetics %V 19 %N 6 %P 1489-1510 %0 Conference Proceedings %A Di Sciasco, E. %A Guzzardi, R. %A Marino, D. %D 1992 %T Proposal of a real time reconstruction processor for 3-D positron emission tomography %J Conference Record of the IEEE Nuclear Science Symposium and Medical Imaging Conference %I IEEE %C Orlando, FL %P 921-3 %K 3D positron emission tomography; single-instruction multiple-data parallel line processor ; nuclear medicine; medical diagnostic imaging ; real time reconstruction processor; bit-serial approach; application-specific integrated circuit; reconstruction processing time; address-encoding time; SILOS II simulator; 256 ns COMPUTERISED TOMOGRAPHY; IMAGE RECONSTRUCTION; MEDICAL IMAGE PROCESSING ; RADIOISOTOPE SCANNING AND IMAGING ; REAL-TIME SYSTEMS %X A specialized real-time reconstruction processor for three-dimensional positron emission tomography is proposed. It is based on an expandible SIMD (single-instruction multiple-data) parallel line processor. It is completely parallel and pipelined, and it is based on a bit-serial approach. The architecture, extremely suitable for ASIC (application-specific integrated circuit) implementation, has been designed to be compatible with existing tomograph prototypes, but it is easily scalable towards foreseen new solutions. The reconstruction processing time of the single coincidence line is of the order of the address-encoding time (at present 256 ns). The silicon design, in the SOLO 2030+41 environment with ES2 standard cells, is in progress, and it has been validated by simulations performed using the SILOS II simulator. %0 Conference Proceedings %A Diamantaras, K. %A Chihoub, A. %A Zawadski, A. %D 1993 %T Scalable architectures for image processing %J Machine Vision Applications, Architectures, and Systems Integration II %I SPIE %C Boston, MA %P 7-9 %K scalable architectures; image processing ; real time processing; parallel architectures ; low-level vision; 1-D array; wrap-around; 2-D array; ring; torus; hypercube; convolution; mathematical morphology; Fourier transform; topologies; histogram; image translation; rotation; zooming; edge-enhancement operators; SES/workbench simulation package; interconnection topology DIGITAL SIMULATION; FILTERING AND PREDICTION THEORY; FOURIER TRANSFORMS; IMAGE PROCESSING ; MATHEMATICAL MORPHOLOGY; PARALLEL ARCHITECTURES; SOFTWARE PACKAGES; TOPOLOGY %X In recent years scalable parallel architectures have emerged as a cost-efficient solution to addressing the problem of ever-increasing computational demands. Such architectures provide the flexibility of increasing the performance while preserving the substantial investment in the software and hardware of a given machine. The authors propose to present the results of their investigation of the scalability of a selected number of low-level vision operations on three topologies: (a) 1-D array with wrap-around (ring) (b) 2-D array with wrap-around (torus), and (c) the hypercube. In particular the authors present the scalability results of the following algorithms: convolution, mathematical morphology, Fourier transform, DCT, histogram, image translation, rotation, zooming, edge-enhancement operators (e.g. Canny, Sobel, Kirsch, Nevatia-Babu), median filtering, point-wise operations (e.g. thresholding, dithering) on the three topologies. In addition, the authors present preliminary results of the design of a scalable parallel processor that performs optimally (performance increases linearly or close to linear in terms of the number of processing elements in the machine) on these operators. The authors' study consists of three phases: mapping the algorithms on the three topologies, simulating the execution of these algorithms, and design of the array. The authors mapping follows the standard methodology proposed for the design of systolic arrays, since their application domain is very specific and the selected algorithms very regular. After the mapping is done the authors simulate the algorithms using the SES/workbench simulation package which allows them to collect statistics on the execution time and efficiency of their mappings and evaluate the performance of the three topologies in their application domain using different array and problem sizes. For each algorithm and topology the range of scalability is determined as a function of image size. In the design phase the authors propose an SIMD array with 2-D torus interconnection topology as a cost-efficient solution to the scalable implementation of the selected algorithms. Considerations entering the design phase are performance as determined by simulations, cost of implementation, and ease of scaling the machine size. %0 Journal Article %A Dijkstra, E. %D 1959 %T A note on two problems in connexion with graphs %J Numerische Mathematik %V 1 %P 269-71 %0 Report %A Dinda, Peter %A Gross, Thomas %A O'Hallaron, David %A Segall, Edward %A Stichnoth, James %A Subhlok, Jaspal %A Webb, Jon %A Yang, Bwolen %D 1994 %T The CMU Task Parallel Program Suite %I Computer Science Department, Carnegie Mellon University %8 March %9 Technical Report %R CMU-CS-94-131 %0 Conference Proceedings %A Director, S.W. %A Parker, A.C. %A Siewiorek, D.P. %A Thomas, D.E. %D 1982 %T A Design Methodology and Computer Aids for Digital VLSI Systems %J CMU Computer Science Research Review 1980-81 %I Carnegie-Mellon University, Computer Science Department %P 39-73 %0 Conference Proceedings %A Doctor, D. P. %A Sudborough, H. %D 1993 %T Parallel algorithm for quadtree medial axis transform %J Proceedings Icci '93. Fifth International Conference on Computing and Information %E Abou-Rabia, O. %E Chang, C.K. %E Koczkodaj, W.W. %C Sudbury, Ont., Canada %P 266-71 %X The quadtree medial axis transform (QMAT) representation of a binary image is a very useful scheme for computer graphics and image processing applications. We present an efficient algorithm for QMAT on the shared memory EREW-PRAM model. For an image of size n*n, using n*n processors, we compute QMAT in O(log n) time. Since image sensors provide image data as a two-dimensional array, a mesh connected computer (MCC) is a popular architecture for image processing applications. Previously known parallel algorithms for QMAT require O(log/sup 2/ n) and O(log n) time on a pyramid model, and a simulation of these two algorithms takes O(n log n) time on an MCC. However, our algorithm can be executed on an MCC in O(n) time, which is optimal for that model due to the size of its diameter. %0 Report %A Dohi, Y. %A Fisher, A. %A Kung, H. T. %A Monier, L. %D 1982 %T PSC Architecture %0 Conference Proceedings %A Dohi, Y. %A Fisher, A.L. %A Kung, H.T. %A Monier, L.M. %D 1982 %T The Programmable Systolic Chip: Project Overview %J Proceedings of Workshop on Algorithmically-specialized Computer Organizations %0 Conference Proceedings %A Dohi, Y. %D 1983 %T Sorter using the PSC Linear Array %J Proceedings of 1983 International Symposium on VLSI Technology, Systems and Applications %P 255-259 %0 Journal Article %A Dohi, H. %A Ishizuka, M. %D 1993 %T Realtime synthesis of moving anthropomorphous agent's image employing small-scale parallel processors %J Journal of the Institute of Image Electronics Engineers of Japan %V 22 %N 3 %P 240-6 %K anthropomorphous agent; visual software agent; 3-D human face image; texture mapped images; transputer network; realtime synthesis; tracking; speech synthesizer GRAPHICAL USER INTERFACES; IMAGE TEXTURE; REAL-TIME SYSTEMS; STEREO IMAGE PROCESSING ; TRANSPUTERS; VISUAL PROGRAMMING %X An anthropomorphous agent which has a realistic human-like face, communication ability and intelligence is expected to play an important role toward advanced interfaces between computer and human. In the visual software agent (VSA) the user communicates with the computer through a realistic 3-D human face image which moves in realtime on a monitor. To perform realtime generation of texture mapped images a prototype of the VSA is implemented in a transputer network and executed in parallel . This paper describes realtime synthesis employing four parallel microprocessors. The VSA can turn his/her face tracking a cursor position on a window, wink his/her eyes, and talk to a user synchronized with a speech synthesizer. %0 Book %A Dongarra, J.J. %A Bunch, J.R. %A Moler, C.B. %A Stewart, G.W. %D 1979 %T LINPACK Users' Guide %I Society for Industrial and Applied Mathematics %C Philadelphia %0 Conference Proceedings %A Downton, A. C. %A Tregidgo, R. W. S. %A Cuhadar, A. %D 1994 %T Top-down structured parallelisation of embedded image and vision applications %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 5/1-6 %K processor farming; image processing ; structured top-down design; parallel embedded systems ; embedded signal processing systems; sequential software structure; generalized parallel architecture ; data parallelism; algorithmic parallelism; temporal multiplexing; input data sets COMPUTER VISION ; IMAGE PROCESSING ; PARALLEL ARCHITECTURES %X The authors propose an architecture-independent structured top-down design methodology for parallel embedded systems. This methodology proceeds from the observation that embedded signal processing systems may be characterized as consisting of series of independent processing stages. The methodology proposes mapping this sequential software structure to a generalized parallel architecture for embedded systems based upon a pipeline of stages with well-defined data communication patterns between them. Each stage of the pipeline then exploits parallelism in the most appropriate way, for example data parallelism applied at various different levels, algorithmic parallelism, or temporal multiplexing of complete input data sets. Processor farming, which is easily adapted to all of these models of parallelism, has been proposed as a general implementation method, because it allows indefinite incremental scaling of any stage and results in a single tractable analytical model. %0 Conference Proceedings %A Drucker, Steven M. %A Schršder, Peter %D 1992 %T Fast Radiosity Using a Data Parallel Architecture %J Third Eurographics Workshop on Rendering %C Barcelona, Spain %P 247-258 %0 Journal Article %A Duda, R. O. %A Hart, P. E. %D 1972 %T Use of the Hough transform to detect lines and curves in pictures %J Communications of the ACM %V 15 %N 1 %0 Book %A Duda, R. O. %A Hart, P. E. %D 1973 %T Pattern Classification and Scene Analysis %I Wiley %0 Conference Proceedings %A Duler, A. W. G. %A Storer, R. H. %A Thomson, A. R. %A Pout, M. R. %A Dagless, E. L. %D 1990 %T A Heterogeneous Vision Architecture %J Computer Vision - ECCV 90. First European Conference on Computer Vision Proceedings %C Antibes, France %P 576-8 %0 Journal Article %A Duller, A. W. G. %A Storer, R. H. %A Thomson, A. R. %A Dagless, E. L. %D 1989 %T An Associative Processor Array for Image Processing %J Image and Vision Computing %V 7 %N 2 %P 151-8 %0 Conference Proceedings %A Dykes, S. G. %A Xiaodong, Zhang %A Yan, Zhou %A Yang, Haixu %D 1994 %T Communication and computation patterns of large scale image convolutions on parallel architectures %J Proceedings Eighth International Parallel Processing Symposium %E Siegal, H.J. %I IEEE Comput. Soc. Press %C Cancun, Mexico %P 926-31 %K computation patterns; large scale image convolutions; parallel architectures ; imag segmentation; image processing operations ; convolution calculations; memory access demand; texture segmentation application; convolution; CM-5; iPSC/860; PVM distributed memory multicomputers; parallel algorithms ; execution time; large kernel convolutions; fast memory store; processor power; communication overhead DISTRIBUTED MEMORY SYSTEMS; IMAGE SEGMENTATION; IMAGE TEXTURE; PARALLEL ALGORITHMS; PARALLEL MACHINES %X Segmentation and other image processing operations rely on convolution calculations with heavy computational and memory access demands. The article presents an analysis of a texture segmentation application containing a 96*96 convolution. Sequential execution required several hours an single processor systems with over 99% of the time spent performing the large convolution. 70% to 75% of execution time is attributable to cache misses within the convolution. We implemented the same application on CM-5, iPSC/860 and PVM distributed memory multicomputers, tailoring the parallel algorithms to each machine's architecture. Parallelization significantly reduced execution time, taking 49 seconds on a 512 node CM-5 and 6.5 minutes on a 32 node iPSC/860. The results indicate for large kernel convolutions the size and bandwidth of the fast memory store is more important than processor power or communication overhead. %0 Journal Article %A Eager, D. L. %A Zahorjan, J. %A Lazowska, E. D. %D 1989 %T Speedup versus efficiency in parallel systems %J IEEE Transactions on Computers %V 38 %N 3 %P 408-23 %0 Generic %A Ebeling, C. %T The Design of Implementation of a Chess Move Generator %0 Report %A Ebeling, C. %A Frank, E.H. %D 1981 %T Saffron: A Programmable Simulator for Digital Systems %0 Report %A Ebeling, C. %D 1981 %T Generating Hierarchical Wirelists with SIL and Analyze %0 Report %A Ebeling, C. %A Frank, E.H. %D 1981 %T Primitives for Simulation %0 Report %A Ebeling, C. %A Frank, E.F. %D 1982 %T SAFFRON User's Manual %0 Conference Proceedings %A Ebeling, C. %A Zajicek, O. %D 1983 %T Validating VLSI Circuit Layout by Wirelist Comparison %J Proceedings of 1983 IEEE International Conference on Computer-Aided Design %P 172-173 %0 Thesis %A Ebeling, C. %D 1986 %T All the Right Moves: A VLSI Architecture for Chess %0 Book %A Eggleston, H.G. %D 1957 %T Problems in Enclidean Space: Application of Convexity %I Pergamon Press %C New York %0 Conference Proceedings %A El-Ghazawi, T. A. %A Flachs, G. M. %D 1991 %T Design of pipelined processors architectures for optimal implementation of difference equations %J Proceedings of the Fourth Ismm/iasted International Conference Parallel and Distributed Computing and Systems %E Ammar, R. A. %C Washington, DC %P 51-2 %K pipelined processors architectures; optimal implementation; difference equations; optimal multiprocessor realizations; maximum concurrency; real-time applications DIFFERENCE EQUATIONS; PARALLEL ARCHITECTURES; PERFORMANCE EVALUATION; PIPELINE PROCESSING %X Difference equations have a wide range of applications including signal processing, image processing , and digital control systems. The real-time nature of such applications require high-speed implementations. Therefore, optimal multiprocessor realizations of difference equations have been targeted by many research efforts. The high-performance provided by these methods was achieved by finding the optimal number of iterations that can be run in an overlapped fashion. Each iteration is, then, scheduled to run on a separate processor. A modified design scheme, which starts with exploiting the maximum concurrency within a single iteration, is presented. It is shown that this modified design strategy results in cost effective difference equations implementations with faster responses, which is essential for real-time applications. %0 Book %A Electrotechnical Laboratory %D 1983 %T SPIDER (Subroutine Package for Image Data Enhancement and Recognition) %I Joint System Development Corp. %C Tokyo, Japan %0 Conference Proceedings %A Ellsworth, David %D 1993 %T A Multicomputer Polygon Rendering Algorithm for Interactive Applications %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, CA %P 43-48 %0 Conference Proceedings %A Elmirghani, J. M. H. %D 1994 %T Optical computing techniques for parallel image processing %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 6/1-4 %K optical signal processing; optical computing; parallel image processing ; real time image processing ; image feature estimation; background noise IMAGE PROCESSING ; OPTICAL INFORMATION PROCESSING; PARALLEL PROCESSING %X Optical signal processing (OSP) offers numerous advantages in real time image processing applications. OSP inherently offers parallelism in the processing of data at speeds much higher than those achievable using electrical digital signal processing (DSP). A review of the available OSP techniques for image processing is given. Particular attention is given to image feature estimation in background noise while the necessary OSP implementations are demonstrated. %0 Journal Article %A Elphinstone, A. C. %A Heron, A. P. %A Hobson, G. S. %A Houghton, A. D. %A Powell, A. R. %A Seed, N. L. %A Tozer, R. C. %D 1988 %T The RAPAC Image Processing System %J Microcomputer Applications %V 7 %N 1 %P 17-21 %0 Journal Article %A Erenyi, I. %A Fazekas, Z. %D 1994 %T Image processing applications and their parallel aspects %J Computing & Control Engineering Journal %V 5 %N 2 %P 71-4 %K image processing applications ; parallel aspects ; VEGA project; HW/SW platforms; intelligent microscopy; industrial quality control; analysis/simulation; parallel architectures IMAGE PROCESSING ; PARALLEL ALGORITHMS; PARALLEL ARCHITECTURES; RESEARCH INITIATIVES; VIRTUAL MACHINES %X Image processing activities at KFKI Research Institute for Measurement and Computing Techniques are summarised. First, KFKI's contribution to the VEGA project is described. Then two HW/SW platforms are mentioned (together with applications in intelligent microscopy, industrial quality control). Finally, the analysis/simulation of promising parallel architectures-to achieve considerable speed-up for image processing primitives-is outlined. This inevitably involves the modification/parallelisation of algorithms to exploit parallel capabilities of the architectures. %0 Journal Article %A Erenyi, I. %A Vassanyi, I. %D 1994 %T Mapping strategies for signal and image processing algorithm parallelization %J Journal on Communications %V 45 %P 50-2 %X The paper discusses some aspects of the fine grain size formal mapping methods aided with some heuristics. The use of a 'slightly configurable' processing elements array is proposed that seems to suffice for a wide range of image processing problems and simultaneously offers a feasible VLSI realization. Further research is needed on the desirable hardware characteristics of such arrays. Also the available VLSI components' impact on the mapping process should be thoroughly investigated. %0 Conference Proceedings %A Ernoult, C. %D 1988 %T Performance of Backpropagation on a Parallel transputer-based Machine %J Neuro-Nimes '88: International Workshop on Neural Networks and their Applications %C Nimes, France %P 311-24 %0 Book Section %A Eshaghian, M. M. %A Lee, S. H. %A Shaaban, M. E. %D 1991 %T Parallel Image Computing with Optical Technology %B Parallel Architectures and Algorithms for Image Understanding %I Academic Press %P 29-58 %0 Journal Article %A Evanczuk, S. %D 1982 %T Researchers Pump Up Systolic Approach %J Electronics %V %P 46-47 %0 Conference Proceedings %A Evans, R.A. %A Wood, D. %A Wood, K. %A McCanny, J.V. %A McWhirter, J.G. %A McCabe, A.P.H. %D 1983 %T A CMOS Implementation of a Systolic Multi-Bit Convolver Chip %J VLSI '83 %E Anceau, F. and Aas, E.J. %I North-Holland %P 227-235 %0 Book Section %A Faiss, Rudolf O. %D 1985 %T Landsat-4 Thematic Mapper Data Processing with the Massively Parallel Processor %B The Massively Parallel Processor %E Potter, Jerry L. %I MIT Press %C Cambridge, MA %P 62-84 %0 Conference Proceedings %A Faugeras, O. D. %A Toscani, G. %D 1986 %T The calibration problem for stereo %J Proceedings of the IEEE International Conference on Computer Vision and Pattern Recognition %P 15-20 %0 Book %A Faugeras, O. D. %D 1993 %T Three-Dimensional Computer Vision: A Geometric Viewpoint %I MIT Press %0 Book %A Faux, I. D. %A Pratt, M. J. %D 1979 %T Computational Geometry for Design and Manufacture %I Ellis Horwood %0 Conference Proceedings %A Feda, Martin %A Purgathofer, Werner %D 1991 %T Progressive Refinement Radiosity on a Transputer Network %J Second Eurographics Workshop on Rendering %C Barcelona, Spain %0 Conference Proceedings %A Fejes, S. %A Vajda, F. %D 1994 %T Simplified Adaptive Approach to Efficient Morphological Image Analysis %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 257-261 %0 Journal Article %A Feo, J. T. %D 1988 %T An Analysis of the Computational and Parallel Complexity of the Livermore Loops %J Parallel Computing %V 7 %N 2 %P 163-186 %0 Conference Proceedings %A Fernandez, C. %A Campoy, P. %A Platero, C. %A Sebastian, J. M. %A Aracil, R. %D 1993 %T On-line surface inspection for continuous cast aluminum strip %J Computer Vision for Industry. %I SPIE %C Munich, Germany %P 24-25 %S Proceedings of the Spie The International Society for Optical Engineering %K surface inspection; continuous cast aluminum strip; visual information; expert system; surface image analysis; parallel architecture ; image processing ; lighting system; image acquisition; texture algorithms; defect detection; formal language theory AUTOMATIC OPTICAL INSPECTION; EXPERT SYSTEMS; IMAGE PROCESSING ; IMAGE TEXTURE; PARALLEL ARCHITECTURES %X A general architecture for detecting and analyzing surface defects in aluminum strip is described. Information concerning visual information from the aluminum surface, surface temperature and strip dimensions-profile thickness-is processed jointly by means of an expert system in order to determine the quality level of each aluminum coil produced; control actions over the casting process, derived from this information, are also suggested by an expert system. The paper shows work related to surface image analysis. The data volume to be processed, up to 20 Mbytes/s, has forced up the development of a high parallel architecture for high-speed image processing . An especially suitable lighting system has been developed for enhancing matricial image acquisition from metallic surfaces that includes reflect avoidance as well as uniform incident angle of light along the scanned portion of surface -about 120000 square mm-. Similarity-based algorithms as well as texture algorithms have been developed and hardware-implemented for defect detection. On-line defect classification is attempted by means of formal language theory. %0 Journal Article %A Ferreira, A. %A Ubeda, S. %D 1994 %T Ultra-fast parallel contour tracking, with applications to thinning %J Pattern Recognition %V 27 %N 7 %P 867-78 %K ultra-fast parallel contour tracking ; thinning; binary pictures; exclusive read exclusive write parallel random access machine ; EREW PRAM; work-optimal parallel thinning algorithm ; skeleton contour IMAGE PROCESSING %X This paper proposes a parallel algorithm for contour tracking of binary pictures. Given an object contour composed by O(N) pixels, our algorithm computes in constant time the next layer of the contour of that object, using the weakest parallel model, i.e. an exclusive read exclusive write (EREW) parallel random access machine (PRAM). As an application of the technique we show a work-optimal parallel thinning algorithm for binary pictures, based on Pavlidis' characterization of a skeleton (1980). Our algorithm improves on previous solutions by producing a list of coordinates corresponding to the skeleton contour in O(N) time with O(N) processors in an EREW PRAM, where N is the width of the picture. %0 Conference Proceedings %A Feynman, C. R. %A Voorhees, H. L. %A Tucker, L. W. %D 1988 %T A Massively Parallel Approach to Object Recognition %J Intelligent Robots and Computer Vision %I SPIE %C Cambridge, MA %P 324-9 %0 Report %A Fischer, M. J. %A Paterson, M. S. %D 1974 %T String Matching and Other Products %0 Journal Article %A Fisher, J.A. %D 1981 %T Trace Scheduling: A Technique for Global Microcode Compaction %J IEEE Trans. on Computers %V C-30 %N 7 %P 478-490 %0 Journal Article %A Fisher, A.L. %D 1982 %T Systolic Algorithms for Running Order Statistics in Signal and Image Processing %J Journal of Digital Systems %V VI %N 2/3 %P 251-264 %0 Conference Proceedings %A Fisher, A.L. %A Kung, H.T. %D 1982 %T Special-Purpose VLSI Architectures: General Discussions and a Case Study %J VLSI and Modern Signal Processing %I Prentice-Hall %0 Conference Proceedings %A Fisher, A.L. %A Kung, H.T. %A Monier, L.M. %A Walker, H. %A Dohi, Y. %D 1983 %T Design of the PSC: A Programmable Systolic Chip %J Proceedings of the Third Caltech Conference on Very Large Scale Integration %E Bryant, R. %I Computer Science Press, Inc. %P 287-302 %0 Journal Article %A Fisher, A.L. %A Kung, H.T. %A Monier, L.M. %A Dohi, Y. %D 1984 %T The Architecture of a Programmable Systolic Chip %J Journal of VLSI and Computer Systems %V 1 %N 2 %P 153-169 %0 Conference Proceedings %A Fisher, A.L. %A Kung, H.T. %A Sarocky, K. %D 1984 %T Experience with the CMU Programmable Systolic Chip %J Proceedings of SPIE Symposium, Vol. 495, Real-Time Signal Processing VII %0 Journal Article %A Fisher, A.L. %A Kung, H.T. %D 1985 %T Synchronizing Large VLSI Processor Arrays %J IEEE Transactions on Computers %V C-34 %N 8 %P 734-740 %0 Conference Proceedings %A Fisher, A. J. and Highnam, P. T. %D 1987 %T Computing the Hough transform on a scan-line array processor %J Computer Architecures for Pattern Analysis and Machine Intelligence %C Seattle, Washington %0 Conference Proceedings %A Fisher, A. %A Highnam, P. T. %D 1988 %T Communication and Code Optimization in SIMD Programs %J International Conference on Parallel Processing %C University Park, PA %0 Journal Article %A Fisher, A. L. and Highnam, P. T. %D 1989 %T Computing the Hough Transform on a Scan Line Array Processor %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 11 %N 3 %P 262-65 %0 Conference Proceedings %A Fisher, A. %A Highnam, P. T. %A Leon, J. %D 1990 %T Design and Performance of a SIMD Optimizing Compiler %J Third Symposium on the Frontiers of Massively Parallel Computing %0 Conference Proceedings %A Fitzpatrick, D.T. %A Foderaro, J.K. %A Katevenis, M.G.H. %A Landman, H.A. %A Patterson, D.A. %A Peek, J.B. %A Peshkess, Z. %A Sequin, C.H. %A Sherburne, R.W. %A Van Dyke, K.S. %D 1981 %T VLSI Implementations of a Reduced Instruction Set Computer %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 326-336 %0 Journal Article %A Flanders, P. M. %A Parkinson, D. %D 1987 %T Data mapping and routing for highly parallel processor arrays %J Future Computing Systems %V 2 %N 2 %P 183-224 %0 Journal Article %A Flanders, P. M. %A Hellier, R. L. %A Jenkins, H. D. %A Pavelin, C. J. %A van den Berghe, S. %D 1991 %T Efficient High-Level Programming on the AMT DAP %J Proceedings of the IEEE %V 79 %N 4 %P 524-36 %0 Journal Article %A Fleisher, H. %A Maisel, L.I. %D 1975 %T An Introduction to Array Logic %J IBM Journal of Research and Development %V %P 98-109 %0 Conference Proceedings %A Fleury, Martin %A Clark, Adrian F. %D 1994 %T Performance Prediction for Parallel Reconfigurable Low-level Image Processing %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 349-351 %0 Conference Proceedings %A Floyd, R. W. %D 1967 %T Assigning Meanings to Programs %J Proceedings of the American Mathematical Society Symposium in Applied Mathematics %P 19-31 %0 Conference Proceedings %A Floyd, R.W. %D 1972 %T Permuting Information in Idealized Two-Level Storage %J Complexity of Computer Computations %E Miller, R.E. and Thatcher, J.W. %I Plenum Press %C New York %P 105-109 %0 Journal Article %A Floyd, R. and Steinberg, L. %D 1975 %T An Adaptive Algorithm for Spatial Grey Scale %J Society for Information Display Digest %V %P 36-7 %0 Conference Proceedings %A Floyd, R.W. %A Ullman, J.D. %D 1980 %T The Compilation of Regular Expressions into Integrated Circuits %J Proceedings of 21st Annual Symposium on Foundations of Computer Science %P 260-269 %0 Book Section %A Flynn, M.J. %D 1975 %T Introduction to Computer Architecture 10 - Interpretation, Microprogramming, and the Control of a Computer %I Science Research Associates, Inc. %S Computer Science Series %0 Conference Proceedings %A Forin, A. %A Barrera, J. %A Sanzi, R. %D 1989 %T The Shared Memory Server %J Winter USENIX Conference %I Usenix %C San Diego %0 Journal Article %A Fortes, J. A. B. %A Moldovan, D. I. %D 1985 %T Parallelism Detection and Transformation Techniques Useful for VLSI Algorithms %J Journal of Parallel and Distributed Computing %V 2 %N 3 %P 277-301 %0 Generic %A Forum, High Performance Fortran %D 1993 %T High Performance Fortran language specification vertion 1.0 %8 May %0 Generic %A Foster, M.J. %T Two Pipeline Algorithms %0 Journal Article %A Foster, M.J. %A Kung, H.T. %D 1980 %T The Design of Special-Purpose VLSI Chips %J Computer Magazine %V 13 %N 1 %P 26-40 %0 Generic %A Foster, M.J. %A Kung, H.T. %D 1980 %T Toward a Theory of Systolic Algorithms for VLSI %0 Conference Proceedings %A Foster, M.J. %D 1981 %T Syntax-Directed Verification of Circuit Function %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 196-202 %0 Conference Proceedings %A Foster, M. J. %D 1983 %T A Laser-Programmable Chip for Language Recognition %J Proceedings of the IEEE Workshop on Languages for Automation %0 Journal Article %A Foster, M.J. %A Kung, H.T. %D 1983 %T Recognize Regular Languages with Programmable Building-Blocks %J Journal of Digital Systems %V 6 %N 4 %P 323-332 %0 Conference Proceedings %A Foster, I. %A Xu, Ming %A Avalani, B. %D 1994 %T A compilation system that integrates High Performance Fortran and Fortran M %J Proceedings of the Scalable High Performance Computing Conference %I IEEE Computer Society Press %C Knoxville, TN %P 293-300 %K integrated compilation system; High Performance Fortran; Fortran M; task parallelism; data parallelism; parallel programming ; multidisciplinary simulation; command and control; Fortran compilers; image processing FORTRAN; IMAGE PROCESSING ; PARALLEL LANGUAGES; PROGRAM COMPILERS %X Task parallelism and data parallelism are often seen as mutually exclusive approaches to parallel programming. Yet there are important classes of application, for example in multidisciplinary simulation and in command and control, that would benefit from an integration of the two approaches. In this paper, we describe a programming system that we are developing to explore this sort of integration. This system builds on previous work on task- parallel and data- parallel Fortran compilers to provide an environment in which the task- parallel language Fortran M can be used to coordinate data- parallel High Performance Fortran tasks. We use an image processing problem to illustrate the issues that arise when building an integrated compilation system of this sort. %0 Journal Article %A Foulser, D. E. %A Schreiber, R. %D 1987 %T The Saxpy Matrix-1: A General Purpose Systolic Computer %J Computer Magazine %V 20 %N 7 %P 37-43 %0 Journal Article %A Fountain, T. G. %A Goetcherian, V. %D 1980 %T CLIP4 parallel processing system %J IEEE Proceedings %V %P 219-24 %0 Report %A Fox, G. %A Hiranandani, S. %A Kennedy, K. %A Koelbel, C. %A Kremer, U. %A Tseng, C.-W. %A Wu, M.-Y. %D 1990 %T FORTRAN D Language Specification %I Department of Computer Science, Rice University %R TR90-141 %0 Conference Proceedings %A Franceschetti, G. %A Lanari, R. %A Manni, A. R. %A Mazzeo, A. %A Mazzocca, N. %D 1993 %T Synchronous architectures for high precision processing of SAR data: experiments and results %J International Geoscience and Remote Sensing Symposium %E Fujimura, S. %I IEEE %C Tokyo, Japan %P 1404-9 %X Considers a two-dimensional synthetic aperture radar processing approach and compares the precision processing performances on three different synchronous general purpose computers: a RISC processor, a vector processor and a SIMD architecture with thousands of elementary processors. Results of computation provide an idea of the cost/benefit performance of the three systems for SAR applications. %0 Conference Proceedings %A Frandrianto, J. %A Woo, B. Y. %D 1985 %T VLSI Floating-Point Processors %J Proceedings of 7th Symposium on Computer Arithmetic %P 93-100 %0 Conference Proceedings %A Franics, N. D. %A Nudd, G. R. %A Atherton, T. J. %A Kerbyson, D. J. %A Packwood, R. A. %A Vaudin, J. %D 1990 %T Performance Evaluation of the Hierarchical Hough Transform on an Associate M-SIMD Architecture %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 509-11 %0 Journal Article %A Frank, E.H. %A Sproull, R.F. %D 1981 %T Testing and Debugging Custom Integrated Circuits %J Computing Surveys %V 13 %N 4 %P 425-451 %0 Report %A Frank, E.H. %A Ebeling, C.E. %A Sproull, R.F. %D 1981 %T Hierarchical wirelist format %0 Report %A Frank, E. %D 1982 %T The Fast-1: A Data-Driven Multiprocessor for Logic Simulation %0 Conference Proceedings %A Frank, E.D. %A Sproull, R.F. %D 1983 %T A Self-Timed Static RAM %J Proceedings of the Third Caltech Conference on Very Large Scale Integration %E Bryant, R. %I Computer Science Press, Inc. %P 275-285 %0 Conference Proceedings %A Franklin, M.A. %A F., Wann. D. %D 1982 %T Asynchronous and Clocked Control Structures for VLSI Interconnection Networks %J Proceedings of the 9th International Symposium on Computer Architecture %P 50-59 %0 Journal Article %A Fua, P. %D 1993 %T A parallel stereo algorithm that produces dense depth maps and preserves image features %J Machine Vision and Applications %V 6 %P 35-49 %0 Journal Article %A Fuchs, H. %A Poulton, J. %D 1981 %T Pixel-Planes: A VLSI-Oriented Design for a Raster Graphics Engine %J VLSI Design %V 11 %N 3 %P 20-28 %0 Conference Proceedings %A Fujii, T. %A Sawabe, T. %A Nomura, M. %A Fujii, T. %A Ono, S. %D 1993 %T Performance required of a real-time super high definition image processing system %J Signal Processing of Hdtv, Iv. Proceedings of the International Workshop %E Dubois, E. %E Chiariglione, L. %I Elsevier %C Kawasaki, Japan %P 597-604 %X The paper details the computational power required for the real-time processing of super high definition (SHD) images. In the first step to real-time SHD image processing, the authors have developed the highly parallel DSP system called NOVI-II HiPIPE. They implemented the JPEG coding algorithm on NOVI-II HiPIPE, and evaluate the computational performance required for motion SHD image coding. The results show that a real-time codec must have an average performance of over 100 GFlops (floating point operations) to process SHD motion images. Based on their experience with NOVI-II HiPIPE, a new DSP chip set is being designed for a massively parallel image processing system. The chip set consists of three main parts. The first is a vector processor that has a peak performance of 120 MFlops, and is being redesigned to realize performance of over 300 MFlops with 0.5 mu m fabrication technology. Second is an intercommunication switch that has six 400 Mbps data links. Third, a RISC type DSP core controls other chips and internal memories. This DSP core also has a special function to deal with bit operations in the Huffman coding process. %0 Conference Proceedings %A Fujita, Y. %A Iwashita, M. %A Temma, T. %D 1988 %T A Large Scale Image Processing System TIP-4 Prototype %J IAPR Workshop on Computer Vision: Special Hardware and Industrial Applications %C Tokyo, Japan %P 365-8 %0 Book Section %A Fuller, S. H. %D 1975 %T Introduction to Computer Architecture 11 - Performance Evaluation %I Science Research Associates, Inc. %S Computer Science Series %0 Book Section %A Furnari, M. %A Massarotti, A. %A Giordano, M. %D 1992 %T Structured Parallelism and Data Access Pattern %B Parallel Computing and Transputer Applications %E Valero, M. %E Onate, E. %E Jane, M. %E Larriba, J.L. %E Suarez, B. %I IOS Press %C Barcellona, Spagna %P 955-963 %0 Conference Proceedings %A Fussel, D. %A Varman, P. %D 1982 %T Fault-Tolerant Wafer-Scale Architectures for VLSI %J Proceedings of the 9th Annual Symposium on Computer Architecture %P 190-198 %0 Conference Proceedings %A Gannon, D. %D 1980 %T A Note on Pipelining a Mesh Connected Multiprocessor for Finite Element Problems by Nested Dissection %J Proceedings of the 1980 International Conference on Parallel Processing %P 197-216 %0 Conference Proceedings %A Garda, P. %A Reichart, A. %A Rodriguez, H. %A Devos, F. %A Zavidovique, B. %D 1988 %T Yet Another Mesh Array Smart Sensor? %J 9th International Conference on Pattern Recognition %C Rome, Italy %P 863-5 %0 Book %A Garey, M. R. %A Johnson, D. S. %D 1979 %T Computers and Intractibility: A guide to the theory of NP-completeness %I W. H. Freeman %0 Journal Article %A Gargantini, I. %D 1982 %T An effective way to represent quadtrees %J Communications of the ACM %V 25 %N 12 %P 905-10 %0 Journal Article %A Garner, H.L. %D 1976 %T A Survey of Some Recent Contributions to Computer Arithmetic %J IEEE Transactions on Computers %V C-25 %P 1277-1282 %0 Journal Article %A Gehringer, E. F. %A Abullarade, J. %A Gulyn, M. H. %D 1988 %T A Survey of Commercial Parallel Processors %J Computer Architecture News %V 16 %N 4 %P 75-107 %0 Journal Article %A Gelertner, D. %D 1985 %T Generative Communication in Linda %J ACM Transations on Programming Languages and Systems %V 7 %N 1 %P 80-112 %0 Journal Article %A Geman, S. and Geman, D. %D 1984 %T Stochastic Relaxation, Gibbs Distributions, and the Bayesian Restoration of Images %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 6 %N 6 %P 721-41 %0 Conference Proceedings %A Gennart, B. A. %A Hersch, R. D. %D 1994 %T Multimedia performance behavior of the GigaView parallel image server %J Proceedings Thirteenth Ieee Symposium on Mass Storage Systems. Towards Distributed Storage and Data Management Systems. First International Symposium %I IEEE Computer Society %C Annecy, France %P 90-8 %X Multimedia interfaces increase the need for large image databases, supporting the capability of storing and fetching streams of data with strict synchronicity and isochronicity requirements. In order to fulfill these requirements, the GigaView parallel image server architecture relies on arrays of intelligent disk nodes, with each disk node being composed of one processor and one disk. This paper analyzes, through simulation, the real-time behavior of the GigaView in terms of delay and delay jitter. For a high-end GigaView architecture, consisting of 16 disks and T9000 transputers, we evaluate stream frame access times under various parameters, such as load factors, frame size, stream throughput, and synchronicity requirements. %0 Journal Article %A Gentleman, W.M. %D 1973 %T Least Squares Computations by Givens Transformations Without Square Roots %J J. Inst. Maths Applics %V 12 %P 329-336 %0 Journal Article %A Gentleman, W.M. %D 1974 %T Basic Procedures for Large, Sparse or Weighted Linear Least Squares Problems (Algorithm AS 75) %J Applied Statistics %V 23 %N 2 %P 448-454 %0 Journal Article %A Gentleman, W.M. %D 1975 %T Error Analysis of QR Decompositions by Givens Transformations %J Linear Algebra and Its Applications %V 10 %P 189-197 %0 Conference Proceedings %A Gentleman, W.M. %A Kung, H.T. %D 1981 %T Matrix Triangularization by Systolic Arrays %J Proceedings of SPIE Symposium, Vol. 298, Real-Time Signal Processing IV %P 19-26 %0 Journal Article %A Gerla, M. %A Kleinrock, L. %D 1980 %T Flow Control: A Comparative Survey %J IEEE Transactions on Communications %V COM-28 %P 553-574 %0 Conference Proceedings %A Gerogiannis, Dimitris %A Orphanoudakis, Stelios C. %D 1992 %T Efficient Use of Parallelism in Intermediate Level Vision Tasks %J International Conference on Pattern Recognition %I IEEE Computer Society Press %C The Hague, The Netherlands %P 160-164 %0 Conference Proceedings %A Gerogiannis, Dimitris %D 1992 %T Programming Intermediate Level Vision Tasks on Parallel Machines %J International Conference on Pattern Recognition %I IEEE Computer Society Press %C The Hague, The Netherlands %P 119-123 %0 Journal Article %A Gerogiannus, D. %A Orphanoudakis, S. C. %D 1993 %T Load balancing requirement in parallel implementations of image feature extraction tasks %J IEEE Transactions on Parallel and Distributed Systems %V %P 994-1013 %0 Conference Proceedings %A Ghosh, I. %A Majumdar, B. %D 1994 %T Design of an application specific VLSI chip for image rotation %J Proceedings of the Seventh International Conference on Vlsi Design %I IEEE Computer Society Press %C Calcutta, India %P 275-8 %K application specific VLSI chip; image rotation; ASIC chip; online rotation; digital image; CORDIC based scheme; pixel displacement; high throughput; parallel architectures ; pipeline architecture; real time rotation; chip area; CMOS standard cells %X Design of an ASIC chip for on-line rotation of a digital image is reported here. A CORDIC based scheme has been used to compute the displacement of a pixel. In order to achieve high throughput, the complete image frame is divided into windows and a combination of parallel and pipeline architectures has been developed to compute the rotation of individual windows and for computing the final displacement. The chip offers real time rotation of 512*512 pixel image, with a clock frequency greater than 10.6 MHz. The estimated chip area is 211*276 mils2. %0 Journal Article %A Ghosh, J. %A Das, S. K. %A John, A. %D 1994 %T Concurrent processing of linearly ordered data structures on hypercube multicomputers %J Ieee Transactions on Parallel and Distributed Systems %V 5 %N 9 %P 898-911 %X The paper presents a simple and effective method for the concurrent manipulation of linearly ordered data structures on hypercube systems. The method Is based on the existence of an augmented binomial search tree, called the pruned binomial tree, rooted at any arbitrary processor node of the hypercube such that; every edge of the tree corresponds to a direct link between a pair of hypercube nodes; and the tree spans any arbitrary sequence of n consecutive nodes containing the root, using a fanout of at most (log/sub 2/ n) and a depth of at most (log/sub 2/ n)+1. Search trees spanning nonoverlapping processor lists are formed using only local information, and can be used concurrently without contention problems. Thus, they can be used for performing operations such as broadcast and merge simultaneously on sets with nonuniform sizes. Extensions of the tree to k-ary n-cubes and faulty hypercubes are presented. Applications of this concurrent data structure to low- and intermediate-level image processing algorithms, and for dictionary operations involving multiple keys, are also outlined. %0 Conference Proceedings %A Goad, C. %D 1983 %T Special Purpose Automatic Programming for 3D Model Based Vision %J Image Understanding Workshop %I Defense Advanced Research Projects Agency %P 94-104 %0 Journal Article %A Golden, R. L., P. A. Latus %A Lowy, P. %D 1980 %T Design Automation and the Programmable Logic Array Macro %J IBM Journal of Research and Development %V 24 %N 1 %P 23-31 %0 Book %A Golub, G.H. %A Van Loan, C.F. %D 1983 %T Matrix Computations %I The Johns Jopkins University Press %C Baltimore, Maryland %0 Conference Proceedings %A Gong, WeiXin %A Bertrand, Gilles %D 1990 %T A simple parallel 3D thinning algorithm %J International Conference on Pattern Recognition %I IEEE Computer Society Press %C Atlantic City, NJ %6 3 %P 188-190 %X In this paper, we present a parallel 3D thinning algorithm, which conserves medial surfaces. A new characterization of simple points is proposed and some new topological predicates are given which are very simple to calculate. Some new geometrical predicates are also given. We prove that the thinning operation based on those new predicates does not deconnect a 3D object. The experiments show that the method gives a satisfactory result. %0 Conference Proceedings %A Goodenough, J. %A Meacham, R. J. %A Morris, J. D. %A Seed, N. L. %A Ivey, P. A. %D 1994 %T A general purpose, single chip video signal processing (VSP) architecture for image processing , coding and computer vision %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 1 %K general purpose architecture; SIMD; 2D transforms; single chip video signal processor; systolic array; general purpose chip; multiprocessing chip; image processing ; coding; computer vision ; single chip VSP; DSP architectures; array processors; functional domains; array processing core; RISC processor; intelligent memory management processor; core architecture; 2D windowed operations; 2D MAC; 80 MHz; Si COMPUTER VISION ; DIGITAL SIGNAL PROCESSING CHIPS; IMAGE CODING; IMAGE PROCESSING EQUIPMENT; PARALLEL ARCHITECTURES %X This paper describes the architecture of a novel, internally multiprocessing, single chip VSP. The limitations of extended DSP architectures and conventional array processors are discussed in the context of the functional domains for image processing , coding and computer vision . Integration of a novel array processing core together with a RISC processor and intelligent memory management processor provide flexibility. The core architecture is a new enhanced array processor whose key features are: 2 bit datapath, dual processor mesh connected array planes and combined SIMD/systolic functionality. The core is optimised for 2D windowed operations, particularly 2D MAC and transforms. The device is expected to operate at 80 MHz on low voltage silicon and deliver in excess of 3 G Op s-1 in any target application. %0 Conference Proceedings %A Goodfriend, L. %D 1993 %T Automatic processing of ultrasound images for non-destructive testing %J Computer Vision for Industry %I SPIE %C Munich, Germany %P 24-25 %S Proceedings of the Spie The International Society for Optical Engineering %K ultrasound images; non-destructive testing; CFC panels; parallel-scanning ; data acquisition; computer vision ; pattern matching ACOUSTIC IMAGING ; AEROSPACE COMPUTING; COMPUTER VISION ; IMAGE PROCESSING ; ULTRASONIC MATERIALS TESTING %X Introduces a new system for automated sentencing of CFC panels of solid or matrix (honeycomb) construction. The author begins with a brief description of a new parallel-scanning ultrasound rig which greatly reduces the time required for data acquisition. A detailed description is then given of the design and implementation of a computer vision system which processes the resulting ultrasound images. Automatic sentencing begins with a pattern matching stage where the image of the panel on test is compared with a reference model of an acceptable standard. Gross defects are then easily detected. Further operations on the test image reject false alarms and allow detection of smaller defects. The resulting defect maps (one for solid areas, one for honeycomb) are merged and a rule base is used to determine whether the positions and sizes of defects are within acceptable levels. This system has been implemented using a MicroVAX, with dedicated array-processing hardware, and also on a Unix workstation. Sentencing is completed in less than one minute. %0 Generic %A Goulding, M. (MEIKO Limited) %D 1988 %T MK027 Frame Grabber, Test and Demonstration Software %9 Programming manual %0 Generic %A Goulding, M. %D 1988 %T Mk027 frame grabber, test & documentation software %8 November %0 Conference Proceedings %A Graefe, V. %D 1990 %T The BVV-family of robot vision systems %J IEEE International Workshop on Intelligent Motion Control %C Istanbul, Turkey %P IP55-65 %0 Journal Article %A Graham, J.W. %A Kritzinger, P.S. %D 1973 %T A Survey of Sorting Activity at Canadian Computer Installations %J Canadian Data Systems %V %P 40-41 %0 Conference Proceedings %A Gray, J.H. %A Greenstreet, M.R. %D 1984 %T A VLSI FFT System Design %J Proceedings of IEEE ASSP 1984 Workshop on VLSI Signal Processing %0 Report %A Greene, J.W. %A Gamal, A.El. %D 1983 %T Configuration of VLSI Arrays in the Presence of Defects %0 Generic %A Greer, B. %D 1991 %T 2d FFT Performance Measurements on iWarp %C iWarp Forum, Hyatt Regency, Crystal City, Maryland %8 September 11, 1991 %9 Lecture %0 Conference Proceedings %A Greer, Bruce %A Webb, Jon A. %D 1992 %T Real Time Supercomputing on iWarp %J Image Processing and Interchange: Implementation and Systems %E Arps, Ronald B. %E Pratt, William K. %I SPIE %C San Jose, CA %P 12-23 %0 Journal Article %A Grimson, W. E. L. %A Lozano-Perez, T. %D 1984 %T Model-based Recognition and Localization from Sparse Range or Tactile Data %J The International Journal of Robotics Research %V 3 %N 3 %P 3-35 %0 Journal Article %A Grimson, W. Eric L. %A Lozano-Perez, Tomas %D 1987 %T Localizing Overlapping Parts by Searching the Interpretation Tree %J PAMI %V 9 %N 4 %P 469-82 %0 Conference Proceedings %A Grimson, W. E. L. %A Horn, B. K. P, Poggio, T. %A staff %D 1992 %T Progress in Image Understanding at MIT %J Image Understanding Workshop %I Defense Advanced Research Projects Agency %C San Diego, CA %P 69-82 %0 Book %A Griswold, R. E. %A Poage, J. F. %A Polansky, I. P. %D 1968 %T The SNOBOL4 Programming Language %I Prentice-Hall %C Englewood Cliffs, NJ %0 Conference Proceedings %A Gross, T. %A Kung, H.T. %A Lam, M. %A Webb, J. %D 1985 %T Warp as a Machine for Low-level Vision %J International Conference on Robotics and Automation %I IEEE %C St. Louis, MO %P 790-800 %0 Conference Proceedings %A Gross, T. %A Lam, M. %D 1986 %T Compilation for a High-performance Systolic Array %J Proceedings of the SIGPLAN 86 Symposium on Compiler Construction %P 27-38 %0 Book %A Group, ANSI X3H3.8 - Imaging Applications Programmer Interface Task %D 1990 %T Programmer's Imaging Kernel (PIK), Strawman V8 %I ANSI %0 Journal Article %A Guan, L. %D 1994 %T Image restoration by a neural network with hierarchical cluster architecture %J Journal of Electronic Imaging %V 3 %N 2 %P 154-63 %X A neural network approach for image restoration is presented. The proposed method is based on a neural network with hierarchical cluster architecture (NNHCA), one of the recently emerged neural networks with sophisticated architectures. The method is motivated by the universally accepted concept in digital image processing that natural image formation is a local process. Therefore, the inverse problem of image restoration can be expressed by a globally coordinated local parallel processing (GCLPP) model. The GCLPP model can be readily realized by NNHCA. By utilizing the symmetric positive-definite quadratic structure of the formulation, a model-based local neuron evaluation algorithm is proposed. The algorithm significantly increases the convergence speed of restoration compared with previously proposed neural computing methods. A coordination scheme is also introduced to systematically resolve conflicting boundary conditions in the problem formulation. Visual examples are given to demonstrate that the proposed method not only produces good restoration results, but also provides a genuine parallel processing structure that ensures computationally feasible space domain image restoration. %0 Journal Article %A Guccione, Steven A. %A Gonzales, Mario J. %D 1993 %T A Data-Parallel Programming Model for Reconfigurable Architectures %V %P 79-87 %0 Conference Proceedings %A Guerra, C. and Hambrusch, S. %D 1987 %T Parallel Algorithms for Line Detection on a Mesh %J Computer Architecures for Pattern Analysis and Machine Intelligence %P 99-106 %0 Conference Proceedings %A Guerra, Concettina %D 1994 %T Survey of Parallel Algorithms for Structural Pattern Matching %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 275-278 %0 Conference Proceedings %A Gugliotta, G. %A Machi, A. %D 1994 %T Preliminary benchmark of low level image processing algorithms on the ViP 1 parallel processor %J Time Varying Image Processing and Moving Object Recognition %E Cappellini %I Elsevier %C Florence, Italy %P 105-9 %K low level image processing algorithms ; ViP 1 parallel processor ; versatile image processor; machine prototype ViP 1; technical details; parallel operation ; computational elements; cluster level; crate level; machine performance evaluation model; benchmark activity DIGITAL SIGNAL PROCESSING CHIPS; IMAGE PROCESSING ; IMAGE PROCESSING EQUIPMENT; PARALLEL ARCHITECTURES; PARALLEL PROGRAMMING; PERFORMANCE EVALUATION %X The paper is a progress report on the implementation of the prototype of the parallel processor ViP (versatile image processor). The first section of the paper gives some technical details of the machine prototype ViP 1. The second one describes some techniques useful to optimize the parallel operation of the computational elements at the cluster and crate level; it also introduces a model for the evaluation of the machine performance in low-level image processing . The last section discusses some results of actual benchmark activity. %0 Conference Proceedings %A Guibas, L.J. %A Kung, H.T. %A Thompson, C.D. %D 1979 %T Direct VLSI Implementation of Combinatorial Algorithms %J Proceedings of Conference on Very Large Scale Integration: Architecture, Design, Fabrication %P 509-525 %0 Conference Proceedings %A Guibas, L.J. %A Liang, F.M. %D 1982 %T Systolic Stacks, Queues, and Counters %J Proceedings, Conference on Advanced Research in VLSI %C Cambridge, Massachusetts %P 155-164 %0 Journal Article %A Guibas, L. J. %A Stolfi, J. %D 1985 %T Primitives for the manipulation of general subdivisions and the computation of Voronoi diagrams %J ACM Transactions on Graphics %V 4 %0 Conference Proceedings %A Guichard-Jary, P. %D 1989 %T PADMAVATI Parallel Associative Development Machine as a Vehicle for Artificial Intelligence %J ESPRIT '89. Proceedings of the 6th Annual Esprit Conference %I Kluwer Academic %C Brussels, Belgium %P 490-9 %0 Conference Proceedings %A Gunzinger, A. %A Mathis, S. %A Guggenbuehl, W. %D 1990 %T The Synchronous Dataflow Machine: A Computer Architecture for Real Time Image Processing %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 436-44 %0 Conference Proceedings %A Gunzinger, A. %D 1991 %T Concept and Realization of a Heterogeneous Multiprocessor System for Real Time Image Processing %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 263-269 %0 Thesis %A Gupta, S. %D 1981 %T Architectures and Algorithms for Parallel Updates of Raster Scan Displays %0 Journal Article %A Gupta, S. %A Sproull, R.F. %A Sutherland, I.E. %D 1981 %T A VLSI Architecture for Updating Raster Scan Displays %J Computer Graphics %V 15 %N 3 %0 Journal Article %A Gupta, S. %A Sproull, R.F. %D 1981 %T Filtering Edges for Gray-Scale Displays %J Computer Graphics %V 15 %N 3 %0 Journal Article %A Gupta, A. %A Toong, H.D. %D 1983 %T An Architectural Comparison of 32-bit Microprocessors %J IEEE Micro %V 3 %N 1 %P 9-22 %0 Book Section %A Gusciora, George %A Webb, Jon A. %D 1993 %T Parallel Affine Image Warping %B Parallel Processing for Artificial Intelligence %E Kanal, L. N. %I North-Holland %0 Journal Article %A Gustafson, J. %D 1988 %T Reevaluating Amdhal's Law %J Communications of the ACM %V 31 %N 5 %P 523-533 %0 Journal Article %A Haag, N.N. %D 1992 %T Image Matching Using Corresponding Point Measurements %J Photogrammetric Engineering and Remote Sensing %V 58 %N 12 %P 1693-1697 %0 Conference Proceedings %A Hachtel, G.D. %A Newton, A.R. %A Sangiovanni-Vincentelli, A.L. %D 1980 %T Some Results in Optimal PLA Folding %J Proceedings of the 1980 IEEE International Conference on Circuits and Computers %0 Report %A Haken, D. %D 1980 %T A Geometric Design Rule Checker %0 Conference Proceedings %A Hall, J.S. %D 1981 %T A General-Purpose CAM-Based System %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 379-388 %0 Conference Proceedings %A Hall, Richard W. %D 1994 %T Connectivity Preservation Tests for Parallel Reduction-Augmentation Algorithms %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 245-250 %0 Journal Article %A Hallin, T.G. %A Flynn, M.J. %D 1972 %T Pipelining of Arithmetic Functions %J IEEE Transactions on Computers %V C-21 %P 880-886 %0 Generic %A Hamey, L. %A H. Printz, D. Reece %A Shafer, S. %D 1987 %T A Programmer's Guide to the Generalized Image Library %0 Book Section %A Hamey, L. G. C. %A Webb, J. A. %A Wu, I. C. %D 1987 %T Low-level Vision on Warp and the Apply Programming Model %B Parallel Computation and Computers for Artificial Intelligence %E Kowalik, J. %I Kluwer Academic Publishers %P 185-199 %0 Journal Article %A Hamey, L. G. C. %A Webb, J. A. %A Wu, I-C. %D 1989 %T An Architecture Independent Programming Language for Low-Level Vision %J Computer Vision, Graphics, and Image Processing %V 48 %N 2 %P 246-64 %0 Journal Article %A Hammarling, S. %D 1974 %T A Note on Modifications to The Givens Plane Rotations %J J. Inst. Maths Applics %V 13 %P 215-218 %0 Journal Article %A Hara, K. %A Ohta, J. %A Nitta, Y. %A Kyuma, K. %D 1994 %T Surface operating optoelectronic devices and applications to optical parallel processing %J Transactions of the Institute of Electronics, Information and Communication Engineers C I %V %N no %P 293-302 %X Two-dimensional (2-D) arrays of surface operating optoelectronic devices are expected to offer massively parallel information processing and communication. This paper reviews the recent evolution of 2-D array devices, with emphasis on the application to 3-D systems. From the point of view of interaction in the array, 3-D system configurations are divided into a global optical interconnection system based on independent arrays and a local optical interconnection system based on interactive arrays. The features of each system are discussed through the application to optical switching networks, direct image processing and optical neural networks. %0 Generic %A Haralick, R. M. %T Gipsy: General image processing system %I Intelligent Systems Laboratory, Department of Electrical Engineering FT-10, The University of Washington, Seattle, WA 9819 %9 Product description brochure %0 Journal Article %A Haralick, R. M. %D 1984 %T Digital Step Edges from Zero Crossings of Second Directional Derivatives %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 6 %P 58-68 %0 Conference Proceedings %A Haralick, Robert M. %A Somani, Arun K. %A Wittenbrink, Craig %A Johnson, Robert %A Cooper, Kenneth %A Shapiro, Linda G. %A Phillips, Ihsin T. %A Hwang, Jenq-Neng %A Cheung, William %A Yao, Yung Hsi %A Chen, Chung-Ho %A Yang, Larry %A Daugherty, Brian %A Lorbeski, Bob %A Loving, Kent %A Miller, Tom %A Parkins, Larye %A Soos, Steve %D 1992 %T Proteus: a reconfigurable computational network for computer vision %J International Conference on Pattern Recognition %I IEEE Computer Society Press %C The Hague, The Netherlands %P 43-57 %0 Book %A Harary, F. %D 1969 %T Graph Theory %I Addison-Wesley %C Reading, Massachusetts %0 Journal Article %A Harvey, W. %A Kalp, D. %A Tambe, M. %A McKeown, D. %A Newell, A. %D 1991 %T The effectiveness of task-level parallelism for high-level vision %J Journal of Parallel and Distributed Computing %V 13 %N 4 %P 395-411 %0 Conference Proceedings %A Hasebe, A. %A Yonemitsu, J. %A Kato, R. %A Ito, N. %A Fujita, H. %D 1988 %T Architecture of SIPS, A Real Time Image Processing System %J International Conference on Systolic Arrays %C San Diego, CA %P 621-30 %0 Conference Proceedings %A Hasegawa, Osamu %A Yokosawa, Kasuhiko %A Ishizuka, Mitsuru %D 1994 %T Real-time Parallel and Cooperative Recognition of Facial Images for an Interactive Visual Human Interface %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 384-387 %0 Thesis %A Haskin %A Lee, Roger %D 1980 %T Hardware for Searching Very Large Text Databases %0 Journal Article %A Hayes, J.P. %D 1976 %T A Graph Model for Fault-Tolerant Computing Systems %J IEEE Transactions on Computers %V C-25 %N 9 %P 875-884 %0 Conference Proceedings %A Hayes, J. P. %A Mudge, T. N. %A Stout, Q. F. %A Colley, S. %A Palmer, J. %D 1986 %T Architecture of a Hypercube Supercomputer %J Proceedings of the 1986 International Conference on Parallel Processing %P 653-660 %0 Journal Article %A Heckbert, P. %D 1982 %T Color Image Quantization for Frame Buffer Display %J Computer Graphics %V 16 %N 3 %P 297-307 %0 Conference Proceedings %A Hedlund, K.S. %A Snyder, L. %D 1984 %T Systolic Architecture: A Wafer-Scale Approach %J Proc. IEEE International Conference on Computer Design %I IEEE %P 604-610 %0 Conference Proceedings %A Heller, D.E. %A Ipsen, I.C.F. %D 1982 %T Systolic Networks for Orthogonal Equivalence Transformations and Their Applications %J Proceedings of Conference on Advanced Research in VLSI %C Cambridge, Massachusetts %P 113-122 %0 Conference Proceedings %A Heller, D.E. %D 1983 %T Decomposition of Recursive Filters for Linear Systolic Arrays %J Proceedings of SPIE Symposium, Vol. 431, Real-Time Signal Processing VI %P 55-59 %0 Conference Proceedings %A Helzle, M. %D 1993 %T New ways in image processing with parallel DSPs %J Proceedings of the Fourth International Conference on Signal Processing Applications and Technology %I DSP Associates %C Santa Clara, USA %6 2 %P 1134-43 %X Traditional image processing systems use extensive pixel-or video-buses to handle the video data between video input and the processing elements. There are no real standards for these buses and they are also limited to the special needs (data rate) of image processing . The new parallel DSP TMS320C40 from Texas Instruments with six 20 MByte/s fast communication ports makes it possible to connect a camera or other high speed data sources directly to them and distribute the data application dependent over any number of processors. Parallelization of hardware and software will be explained. %0 Conference Proceedings %A Hennessy, J. %A Jouppi, N. %A Baskett, F. %A Gill, J. %D 1981 %T MIPS: A VLSI Processor Architecture %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 337-346 %0 Journal Article %A Hennessy, J.L. %D 1984 %T VLSI Processor Architecuture %J IEEE Transactions on Computers %V C-33 %N 12 %P 1221-1246 %0 Conference Proceedings %A Herbordt, M. C. %A Weems, C. C. %A Shu, D. B. %D 1990 %T Routing on the CAAPP %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 467-71 %0 Journal Article %A Herlihy, M. %D 1990 %T Apologizing Versus Asking Permission: Optimistic Concurrency Control for Abstract Data Types %J ACM Transactions on Database Systems %V 15 %N 1 %P 96-124 %0 Journal Article %A Hestenes, M.R. %D 1958 %T Inversion of Matrices by Biorthogonalization and Related Results %J J. Soc. Indust. Appl. Math. %V 6 %P 51-90 %0 Generic %A High Performance Fortran Forum %T Welcome to the High Performance Fortran Forum %9 Available via anonymous FTP from titan.rice.edu, file public/HPFF/welcome %0 Thesis %A Highnam, P. %D 1991 %T Systems and Programming Issues in the Design and Use of a SIMD Linear Array for Image Processing %I Carnegie Mellon University %0 Book %A Hillis, W. D. %D 1985 %T The Connection Machine %I The MIT Press %0 Journal Article %A Hillis, D. %A Steele, G. L. %D 1986 %T Data Parallel Algorithms %J Communications of the ACM %V 29 %N 12 %P 1170-83 %0 Journal Article %A Hillis, W. D. %A Tucker, L. W. %D 1993 %T The CM-5 Connection Machine Scalable Supercomputer %J Communications of the ACM %V 36 %P 30-40 %0 Conference Proceedings %A Hirsch, E. %A Paillou, Ph. %A MŸller, C. %A Gengenbach, V. %D 1991 %T A Versatile Parallel Computer Architecture for Machine Vision. Application to the Comparison of Real Images and CAD-based Representations %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 251-261 %0 Journal Article %A Hirschberg, D. S. %D 1978 %T Fast Parallel Sorting Algorithms %J Communications of the ACM %V 21 %N 8 %P 657-661 %0 Journal Article %A Hoare, C. A. R. %D 1961 %T Partition (Algorithm 63) and Quicksort (Algorithm 64) %J Communications of the ACM %V 4 %N 7 %P 321 %0 Journal Article %A Hoare, C. A. R. %D 1978 %T Communicating Sequential Processes %J Communications of the ACM %V 21 %N 8 %P 666-677 %0 Conference Proceedings %A Hobbs, T. %A Boesen, B. %A Kim, I. %A Vance, C. %A Fraser, D. %D 1993 %T A Parallel Image Processing And Display System (PIPADS): hardware architecture and control software %J Proceeding of the Twenty Sixth Hawaii International Conference on System Sciences %P 106-15 %X The hardware infrastructure, display system, digital signal processor, array and host-computer control software components developed in a joint project are described. A 64-bit wide implementation of Futurebus+ provides backplane transfer rates of 500 to 700 MByte/s for data flow between array processors, memory, and display modules all being controlled from a host computer workstation. The two million pixel display module supports viewing rates exceeding 36 images per second for single or multiple image streams. Processing is guided by the operator using ball-type or glove-type interactive devices by viewing animation-rate computed images displayed on the screen. One of the hardware modules includes a thirty-two TMS320C40 processor array capable of a peak computation rate of 1.6 GFLOPS and a sustained rate of about 1 GFLOPS on the scan-line oriented algorithms for which the architecture has been optimized. %0 Book %A Hockney, R.W. %A C.R., Jesshope %D 1981 %T Parallel Computers %I Adam Hilger Ltd. %C Bristol, U.K. %0 Conference Proceedings %A Hoey, D. %A Leiserson, C.E. %D 1980 %T A Layout for the Shuffle-Exchange Network %J Proceedings of 1980 International Conference on Parallel Processing %P 329-336 %0 Journal Article %A Holder, D. %A Buxton, H. %D 1990 %T Polyhedral object recognition with sparse data-validation of interpretations %J Image and Vision Computing %V 8 %N 2 %P 124-9 %0 Journal Article %A Holloway, J %A Steele, G.L. %A Jr. %A Sussman, G.J. %A Bell, A. %D 1981 %T SCHEME-79 -- LISP on a Chip %J Computer %V 14 %N 7 %P 10-21 %0 Journal Article %A Homewood, M. %A al., et %D 1987 %T The IMS T800 Transputer %J IEEE Micro %V 7 %N 5 %P 10-26 %0 Report %A Hon, R. %D 1980 %T The Hierarchical Analysis of VLSI Designs %0 Report %A Hon, R. %A Sequin, C. %D 1980 %T A Guide to LSI Implementation %0 Conference Proceedings %A Hong, J.-W. %A Kung, H.T. %D 1981 %T I/O Complexity: The Red-Blue Pebble Game %J Proceedings of the Thirteenth Annual ACM Symposium on Theory of Computing %P 326-333 %0 Conference Proceedings %A Hong, K. S. %A Ikeuchi, K. %A Gremban, K. D. %D 1990 %T Minimum Cost Classification: A Module of a Vision Algorithm Compiler %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 65-9 %0 Journal Article %A Hopcroft, J.E. %A Paul, W. %A Valiant, L.G. %D 1977 %T On Time Versus Space %J Journal of the ACM %V 24 %P 332-337 %0 Book %A Hopcroft, John E. %A Ullman, Jeffrey D. %D 1979 %T Introduction to Automata Theory, Languages, and Computation %I Addison-Wesley Publishing Co. %0 Generic %A Hough, P. V. C. %T Methods and means to recognize complex patterns %9 U.S. Patent 3,069,654 %0 Conference Proceedings %A Hsu, F.H. %A Kung, H.T. %A Nishizawa, T. %A Sussman, A. %D 1985 %T Architecture of the Link and Interconnection Chip %J Proceedings of 1985 Chapel Hill Conference on VLSI %E Fuchs, H. %I Computer Science Press, Inc. %P 186-195 %0 Conference Proceedings %A Hsu, William M. %D 1993 %T Segmented Ray Casting for Data Parallel Volume Rendering %J 1993 Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, California %P 7-13 %0 Conference Proceedings %A Huang, T. S. %A Yang, G. J. %A Tang, G. Y. %D 1978 %T A fast two-dimensional median filtering algorithm %J International Conference on Pattern Recognition and Image Processing %P 128-30 %0 Thesis %A Huang, A. %D 1980 %T Number Theoretic Processors: A Cellular Array Architecture %0 Conference Proceedings %A Huffman, D.A. %D 1957 %T The Synthesis of Linear Sequential Coding Networks %J Information Theory %E Cherry, C. %P 77-95 %0 Edited Book %A Hulskamp, J. %A Jones, D. %D 1993 %T Transputers and Parallel Applications. TAPA-92. Proceedings of the 5th Australian Transputer and OCCAM User Group Conference %B Amsterdam, Netherlands: Ios Press %V 221 %P 4-5 %X The following topics were dealt with: transputers and parallel applications; Linda programming; parallel signal processing; image compression; parallel neural network; cellular arrays; parallel image processing; transputer-based systems; Occam; parallel programming; Helios OS; OO methods; Petri nets; and fluid dynamics applications. %0 Conference Proceedings %A Hummel, R. %A Zhang, K. %D 1987 %T Dynamic Processor Allocation for Parallel Algorithms in Image Processing %J Optical and Digital Pattern Recognition %C Los Angeles, CA %P 268-75 %0 Book %A Hwang, K. %D 1979 %T Computer Arithmetic: Principles, Architecture and Design %I John Wiley & Sons, Inc. %C New York %0 Conference Proceedings %A Hwang, J.H. %A Raghavendra, C.S. %D 1986 %T VLSI Implementation of Fault-Tolerant Systolic Arrays %J Proc. International Conference on Computer Design %I IEEE %P 110-113 %0 Generic %A IBM %D 1988 %T Parallel FORTRAN Language and Library Reference %B First edition %0 Journal Article %A Igarashi, H. %A Kawato, M. %D 1994 %T A solution for inverse problems based on a two-layer random field model-application to image restoration using edge information %J Transactions of the Institute of Electronics, Information and Communication Engineers D II %V %N 6 %P 1104-13 %X "Standard regularization theory", which was proposed to solve ill-posed inverse problems in the fields of visual information processing and computer vision, has two weak points: energy functions must be quadratic, and regularization parameters are usually determined by heuristics. A "two-layer random field model" was proposed to improve these two weaknesses that can be applied not only to inverse optics but also to wide-ranging general inverse problems in the field of engineering. The new model consists of two random fields, one of which is loosely coupled with the other by conditional probability. The new model can deal with non-quadratic energy functions and can adjust unknown regularization parameters to appropriate values in the annealing process. In this paper, the two-layer random field model was applied to image restoration using edge information. The two tasks of searching the minimal energy state and updating the unknown parameters are implemented internally as a collection of parallel processes in order to deal with a large image (128*64 pixels). A SIMD-type parallel computer (Connection Machine CM-2) is used. The presented experimental results show the effectiveness of our approach to inverse problems. %0 Journal Article %A Ikeuchi, K. %D 1987 %T Generating an Interpretation Tree from a CAD Model for 3-D Object Recognition in Bin-Picking Tasks %J International Journal of Computer Vision %V 1 %N 2 %P 145-65 %0 Conference Proceedings %A Ikeuchi, K. %A Suehiro, T. %D 1992 %T Towards an Assembly Plan from Observation %J International Conference on Robotics and Automation %P 2171-2177 %0 Journal Article %A Illiffe, J. K. %A Jodeit, J. G. %D 1962 %T A dynamic storage allocation scheme %J The Computer Journal %V 5 %P 200-9 %0 Conference Proceedings %A Inouchi, H. %A McLoughlin, N. %D 1993 %T Parallel techniques for image processing and artificial neural network simulation %J Ai and Cognitive Science '91 %E Sorensen, H. %I Springer-Verlag %C Cork, UK %P 177-89 %K image processing ; artificial neural network simulation; parallel techniques ; memory units; Von Neumann architectures; parallel systems ; AI problems; multiple processing elements; computation models; artificial intelligence; parallel programming ; neural network models IMAGE PROCESSING ; NEURAL NETS; PARALLEL ALGORITHMS; PARALLEL PROGRAMMING; VIRTUAL MACHINES %X The emergence of systems composed of multiple processing elements and memory units, and their associated models of computation promise to alleviate many of the limitations of conventional Von Neumann architectures. The implication of this to the field of artificial intelligence is twofold, parallel systems offer both a significant increase in computing power/speed available, and a more natural physical architecture for implementing parallel solutions to AI problems. We discuss general parallel programming techniques, their real applications to image processing and neural network simulation, parallel implementation of neural network models, and finally we finish with our conclusions derived from this work. %0 Conference Proceedings %A Inoue, H. and Mizoguchi, H. %D 1984 %T A Flexible Multiwindow Vision System for Robots %J Second International Symposium on Robotics Research %I MIT Press %C Kyoto, Japan %P 95-102 %0 Generic %A Intel Corporation %T iPSC %9 Intel Scientific Computers, Beaverton, OR %0 Generic %A Intel Corporation %D 1985 %T iPSC System Overview %0 Conference Proceedings %A Ionescu, D. %A Andronic, C. %A Goodenough, D. %D 1993 %T Object oriented tools for multisensor data fusion for an SIMD computer %J Igarss '93 %E Fujimura, S. %I IEEE %C Tokyo, Japan %P 1128-30 %X The interpretation of remote sensing images challenges the image processing community not only by a variety of difficulties which are to be solved during the creation of an application but also by the computational effort required to run it. The solution to overcome the latter restriction is the use of parallel computers. However, programming such machines is another challenge. The present paper aims towards the design and implementation of powerful tools allowing the user to generate a remote sensing application even on images obtained from a variety of sensors, by icon manipulation. A graph of icons is parsed and a source code free of errors is produced in Objective C for an AIS-3500 massively parallel computer. The environment was used to generate an "Automated Road Detection" system running on the above parallel computer. The system was tested on images from Ottawa area. %0 Generic %A Ipsen, I. %D 1986 %T Talk given at the ONR 1986 Workshop on Systolic Processing %0 Conference Proceedings %A Iqbal, M. A. %A Iqbal, S. %A Shaaban, M. E. %D 1994 %T Partitioning of image processing tasks on heterogeneous computer systems %J Proceedings Heterogeneous Computing Workshop %I IEEE Computer Society Press %C Cancun, Mexico %P 43-50 %K image processing task partitioning ; heterogeneous computer systems; computer vision task decomposition ; high speed links; simultaneous execution; optimal program partitioning; tree-structured program; parallel program ; pipelined program; polynomial time approximation scheme COMPUTATIONAL COMPLEXITY; COMPUTER VISION ; DISTRIBUTED ALGORITHMS; PARALLEL PROGRAMMING; PIPELINE PROCESSING; RESOURCE ALLOCATION; TREE DATA STRUCTURES %X Many computer vision tasks can be decomposed into a set of subtasks which are by their nature heterogeneous. By partitioning such tasks onto different machines that communicate via high-speed links, each level or stage of processing can be executed simultaneously on the machine to which it is best suited. A fundamental problem with heterogeneous computing, however, is the difficulty of optimally partitioning an application program across the machines. In this paper, we address the problem of partitioning a chain or a tree-structured parallel or pipelined program over a two-processor heterogeneous system and show that it is possible to approximately solve this problem. The algorithm presented in this paper is based on a fully polynomial time approximation scheme. %0 Conference Proceedings %A Isshiki, T. %A Takeuchi, Y. %A Kunieda, H. %D 1992 %T Systematic architecture design for highly parallel image processing array %J Proceedings of the 35th Midwest Symposium on Circuits and Systems %P 299-302 %X A methodology for designing the architecture of the processor array for a wide class of image processing algorithms is proposed. A concept of spatially expanding the signal flow graph (SFG) description which enables handling the problem as merely one-dimensional signal processing is used in constructing the methodology. The problem of I/O interface which is critical in real-time processing is also considered. %0 Journal Article %A Iversen, W. R. %D 1984 %T New CMOS Chip Processes Data in Parallel %J ElectronicsWeekly %V %P 17-18 %0 Conference Proceedings %A Ivey, P. A. %A Huch, M. %A Midwinter, T. %A Hurat, P. %A Glesner, M. %D 1988 %T Design of a Large SIMD Array in Wafer Scale Technology %J Wafer Scale Integration, II %I North-Holland %P 75-85 %0 Journal Article %A Izumi, M. %A Asano, T. %A Fukunaga, K. %A Murata, H. %D 1992 %T Matching of Edge-Line Images Using Relaxation %J Ieice Transactions on Information and Systems %V E75D %N 6 %P 902-908 %0 Book %A Jack, Keith %D 1993 %T Video demystified: A handbook for the digital engineer %I High Text Publications, Inc. %C Solana Beach %0 Journal Article %A Jackson, L.B. %A Kaiser, S.F. %A McDonald, H.S. %D 1968 %T An Approach to the Implementation of Digital Filters %J IEEE Trans. Audio and Electroacoust. %V AU-16 %P 413-421 %0 Conference Proceedings %A Jacobi, W. J. %A Kendall, W. B. %A Wadsworth, L. A. %D 1990 %T SCC-100 Parallel Processor for Real-Time Imaging %J Visual Communications and Image Processing '90 %I SPIE %C Lausanne, Switzerland %P 104-8 %0 Journal Article %A Jamieson, L %A Delp, E. %A Wang, C. %A Li, J. %D 1992 %T A Software Environment for Parallel Computer Vision %J Computer %V 25 %N 2 %P 73-7 %0 Conference Proceedings %A Jamieson, Leah H. %A Delp, Edward J. %A Hambrusch, Suzanne E. %A Khokhar, Ashfaq A. %A Cook, Gregory W. %A Hameed, Farooq %A Patel, Jamshed N. %A Shen, Ke %D 1994 %T Parallel Scalalble Libraries and Algorithms for Computer Vision %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 223-228 %0 Journal Article %A Jarvis, R. A. %D 1973 %T On the Identification of the Convex Hull of a Finite Set of Points in the Plane %J Information Processing Letters %V 2 %P 18-21 %0 Journal Article %A Jarvis, J. F. %A Judice, C. N. %A Ninke, W. H. %D 1976 %T A Survey of Techniques for the Display of Continuous Tone Pictures on Bilevel Displays %J Computer Graphics and Image Processing %V 5 %P 13-40 %0 Conference Proceedings %A Jarvis, J. F. %D 1976 %T Feature Recognition in Line Drawings Using Regular Expressions %J Third International Joint Conference on Pattern Recognition %0 Journal Article %A Jaszczak, R. J. %A Jianying, Li %A Huili, Wang %A Zalutsky, M. R. %A Coleman, R. E. (Dept. of Radiol., Duke Univ. Med. Center, Durham, NC, USA) %D 1994 %T Pinhole collimation for ultra-high-resolution, small-field-of-view SPECT %J Physics in Medicine and Biology %V 39 %N 3 %P 425-37 %K pinhole collimation; ultra-high-resolution small-field-of-view SPECT; small laboratory animals imaging ; triple-head SPECT system; aperture diameter; collimator housing; 3D filtered backprojection algorithm; single photon emission computerized tomography; in vitro image quality; micro-cold-rod phantom; micro-Defrise phantom; 3D maximum likelihood-expectation maximization algorithm; rats; 0.6 to 2 mm BIOLOGICAL TECHNIQUES AND INSTRUMENTS; COMPUTERISED TOMOGRAPHY; LABORATORY APPARATUS AND TECHNIQUES; RADIOISOTOPE SCANNING AND IMAGING %X The authors evaluated small-field-of-view ultra-high-resolution pinhole collimation for a rotating-camera SPECT system that could be used to image small laboratory animals. Pinhole collimation offers distinct advantages over conventional parallel -hole collimation when used to image small objects. Since geometric sensitivity increases markedly for points close to the pinhole, small-diameter and high-magnification pinhole geometries may be useful for selected imaging tasks when used with large-field-of-view scintillation cameras. The use of large magnifications can minimize the loss of system resolution caused by the intrinsic resolution of the scintillation camera. A pinhole collimator has been designed and built that can be mounted on one of the scintillation cameras of a triple-head SPECT system. 3 Pinhole inserts with approximate aperture diameters of 0.6, 1.2 and 2.0 mm have been built and can be mounted individually on the collimator housing. When a ramp filter is used with a 3D filtered backprojection (FBP) algorithm, the 3 apertures have in-plane SPECT spatial resolutions (FWHM) at 4 cm of 1.5, 1.9 and 2.8 mm, respectively. In-air point source sensitivities at 4 cm from the apertures are 0.9, 2.6 and 5.7 counts s-1 mu Ci-1 (24, 70 and 154 counts s-1 MBq-1) for the 0.6, 1.2 and 2.0 mm apertures, respectively. In vitro image quality was evaluated with a micro-cold-rod phantom and a micro-Defrise phantom using both the 3D FBP algorithm and a 3D maximum likelihood-expectation maximization algorithm. In vivo image quality was evaluated using 2 (315 and 325 g) rats. Ultra-high-resolution pinhole SPECT is an inexpensive and simple approach for imaging small animals that can be used with existing rotating-camera SPECT systems. %0 Journal Article %A Jefferson, D. %A al., et %D 1987 %T Distributed Simulation and the Time Warp Operating System %J Operating Systems Review %V 21 %N 5 %P 77-93 %0 Conference Proceedings %A Jochem, Todd M. %A Baluja, Shumeet %D 1993 %T A Massively Parallel Road Follower %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 2-12 %0 Conference Proceedings %A Jochem, Todd M. %A Baluja, Shumeet %D 1993 %T A Massively Parallel Road Follower %0 Conference Proceedings %A Johannsen, D. %D 1979 %T Bristle blocks, a silicon compiler %J Design Automation Conference Proceedings %P 310-313 %0 Conference Proceedings %A Johansson, T. %A Bengtsson, E. %D 1994 %T Parallel Algorithms on Compact Binary Objects %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 370-372 %0 Conference Proceedings %A Johl, J. %D 1994 %T MIMD computing algorithm for connected-components problem %J Parallel Computing and Transputers. Pcat %E Arnold, D. %E Christie, R. %E Day, J. %E Roe, P. %I IOS Press %C Brisbane, Qld., Australia %P 183-90 %X This paper describes a new MIMD optimization of a parallel connected-components algorithm developed for a SIMD computer by R.E. Cypher, J.L.C. Sanz, and L. Synder (1990). The problem of labeling the connected-components of a binary image, also known as the 'connected-ones problem', has many important applications, such as in medical imaging . The algorithm reported in this paper operates on an N*N array of mesh-connected independent processors, and provides approximately a 3 times speed-up in execution time, along with a reduction in communication bandwidth compared to the SIMD array. This problem is essentially broken into two parts, consisting of the component-shrinking algorithm and the label assignment algorithm. By a clever use of the MIMD processors, the component-shrinking and label assignment algorithms may be overlapped. Also, the number of labels sent to neighboring cells can be reduced by one-third or more. For large images with lots of small objects, such as blood cells, this algorithm provides considerable savings, since no labels need be sent for a major portion of the processing. A graph showing the relationship between maximum object size and processing time is included. This chart shows speedups of a factor of ten, when the largest objects are one-eighth the frame size. This MIMD algorithm for component labeling substantially improves known SIMD methods and is still simple to program. %0 Journal Article %A Johnson %A C., Stephen %D 1980 %T Language Development Tools on the Unix System %J Computer %V 13 %N 8 %P 16-21 %0 Conference Proceedings %A Johnson, S. A. %A Berggren, M. J. %A Borup, D. T. %A Wiskin, J. W. %A Eidens, R. S. %A Hong, Leng %D 1993 %T Comparison of inverse scattering and other tomographic imaging algorithms using simulated and tank data for modeling subbottom imaging systems %J Oceans '93. Engineering in Harmony with Ocean Proceedings %I IEEE %C Victoria, BC, Canada %P I458-62 %X Comparisons are given of powerful inverse scattering methods for quantitative imaging of ocean bottoms and subbottoms with less computational intensive "quick look" methods. The advantages and tradeoffs of the various methods are discussed. The relative ease and efficiency of using parallel computers on inverse scattering is demonstrated. Finally, laboratory results are shown to illustrated typical beamforming images in subbottom environments and inverse scattering with analogous microwave scanning systems. %0 Conference Proceedings %A Johnsson, L. %A Cohen, D. %D 1981 %T A Mathematical Approach to Modelling the Flow of Data and Control in Computational Networks %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 213-225 %0 Report %A Jones, A. %A Gehringer, E. F. %D 1980 %T The Cm* Multiprocessor Project: A Research Review %0 Conference Proceedings %A Jones, J. P. %D 1993 %T Real-time construction of three-dimensional occupancy maps %J Proceedings Ieee International Conference on Robotics and Automation %I IEEE Comput. Soc. Press %C Atlanta, GA %P 52-7 %K real-time construction; parallel algorithms ; 3-D occupancy maps; laser range camera; iWarp parallel computer ; raytracing; 800 ms IMAGE PROCESSING ; LASER RANGING; PARALLEL PROCESSING %X An experimental study of parallel algorithms for constructing 3-D occupancy maps is described. Data from a laser range camera are processed on an iWarp parallel computer. The resulting 3-D map is rendered using raytracing. The construction and rendering consume less than 800 ms. %0 Conference Proceedings %A Jonker, Peter P. %D 1993 %T An SIMD-MIMD architectue for image processing and ppattern recognition %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 222-230 %0 Conference Proceedings %A Jonker, Pieter P. %D 1994 %T Why Linear Arrays are Better Image Processors %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 334-338 %0 Journal Article %A Jordan, K. E. %D 1987 %T Performance comparison of large-scale scientific computers: Scalar mainframes, mainframes with integrated vector facilities, and supercomputers %J Computer %V 20 %N 3 %P 10-23 %0 Conference Proceedings %A Jouppi, N.P. %D 1983 %T TV: An nMOS Timing Analyzer %J Proceedings of the Third Caltech Conference on Very Large Scale Integration %E Bryant, R. %I Computer Science Press, Inc. %P 71-86 %0 Book %A Joy, W. N. %A Babaoglu, O. %A Fabry, R. S. %A Sklower, K. %D 1980 %T UNIX Programmer's Manual %I University of California at Berkeley %7 4th Berkeley Distribution %0 Journal Article %A Ju, D.-C.R. %A Wu, C.-L. %A Carini, P. %D 1994 %T The Classification, Fusion, and Parallelization of Array Language Primitives. %J Journal of Parallel and Distributed Computing %V 10 %N 5 %P 1113- %0 Conference Proceedings %A Judd, Dan %A Ratha, Nalini K. %A McKinley, Philip K. %A Weng, John %A Jain, Anil K. %D 1994 %T Parallel Implementation of Vision Algorithms on Workstation Clusters %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 317-321 %0 Conference Proceedings %A Juhazs, Z. %A Crookes, D. %A Morrow, P. J. %D 1992 %T Design and implementation issues of a scalable, transputer-based parallel image processing system %J 1st Austrian Hungarian Workshop on Transputer Applications. %C Sopron, Hungary %P 59-66 %X The paper describes a transputer-based parallel image processing architecture, developed at the Queen's University of Belfast to reduce processing lime. First the system architecture is explained, then various aspects of the parallel image processing (image distribution, overlapping image segment borders, communication) are discussed. Finally the structure of the layered software is described. %0 Conference Proceedings %A Kaba, James %A Peters, Joseph %D 1993 %T A Pyramid-based Approach to Interactive Terrain Visualization %J Parallel Rendering Symposium %C San Jose, CA %P 67-70 %0 Generic %A Kahaner, D. K. %D 1991 %T Electronic mail message. Report from the first NIPT workshop 1991 %9 Available via anonymous FTP from cs.arizona.edu, file japan/kahaner.reports/nipt11.91 %0 Generic %A Kahaner, D. K. %D 1991 %T Electronic mail message. First Korea-Japan Conference on Computer Vision %9 Computer file %0 Conference Proceedings %A Kamada, H. %A Naoi, S. %A Gotoh, T. %D 1990 %T A Compact Navigation System using Image Processing and Fuzzy Control %J SOUTHEASTCON '90 %C New Orleans, LA %P 337-42 %0 Report %A Kanade, T. %A Thorpe, C. %A CMU SCVision Project Staff %D 1985 %T CMU Strategic Computing Vision Project Report: 1984 to 1985 %I Carnegie-Mellon University, The Robotics Institute %R CMU-RI-TR-86-2 %0 Book Section %A Kanade, T. %A Webb, J. %D 1986 %T Vision on a Systolic Array Machine %B Evaluation of Multicomputers for Image Processing %E Uhr, L. %E K. Preston, Jr. %E Levialdi, S. %E Duff, M. J. B. %I Academic Press %C Orlando, FL %0 Report %A Kanade, T. %A Webb, J. A. %D 1987 %T End of Year Report for Parallel Vision Algorithm Design and Implementation %I Robotics Institute, Carnegie Mellon University %R CMU-RI-TR-87-15 %0 Report %A Kang, S. B. %A Ikeuchi, K. %D 1993 %T Temporal Segmentation of Tasks form Human Hand Motion %I Carnegie Mellon University %8 April %9 Technical Report %R CMU-CS-93-150 %0 Conference Proceedings %A Kang, Sing Bing %A Ikeuchi, Katsu %D 1994 %T Determination of motion breakpoints in a task sequence from human hand motion %J International Conference on Robotics and Automation %P 551-556 %0 Journal Article %A Kant, R.M. %A Kimura, T. %D 1978 %T Decentralized Parallel Algorithms for Matrix Computation %J Proceedings of the Fifth Annual Symposium of Computer Architecture %V %0 Report %A Karp, R.M. %A Rabin, M.O. %D 1981 %T Efficient Randomized Pattern-Matching Algorithms %0 Generic %A Karp, A. %D 1992 %T The Case Against FORALL %9 Distributed through the HPFF FORALL mailing list by karp@hplms2.hpl.hp.com %0 Conference Proceedings %A Kashko, A. %D 1990 %T Reconstructing Large Images on a 32*32 Processor DAP: Simulated Annealing and Graduated Non Convexity %J Parallel Computing 89 %C Leiden, Netherlands %P 217-22 %0 Journal Article %A Kautz, W.H. %A Levitt, K.N. %A Waksman, A. %D 1968 %T Cellular Interconnection Arrays %J IEEE Transactions on Computers %V C-17 %N 5 %P 443-451 %0 Conference Proceedings %A Kedem, Z.M. %A Zorat, A. %D 1981 %T Replication of Inputs May Save Computational Resources in VLSI %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 52-60 %0 Conference Proceedings %A Kelly, R. F. %D 1987 %T 3-D Scene Generation on a Shared Memory Parallel Processor %J True Three-Dimensional Imaging Techniques and Display Technologies %C Los Angeles, CA %P 163-71 %0 Journal Article %A Kermani, P. %A Kleinrock, L. %D 1979 %T Virtual Cut-Through: A New Computer Communication Switching Technique %J Computer Networks %V 3 %N 4 %P 267-286 %0 Journal Article %A Kernighan, B.W. %A Lin, S. %D 1970 %T An Effective Heuristic Procedure for Partitioning Graphs %J Bell Systems Technical Journal %V 49 %P 291-308 %0 Journal Article %A Kernighan, B. W. %A Cherry, L. L. %D 1975 %T A System for Typesetting Mathematics %J Comm. ACM %V 18 %N 3 %P 151-157 %0 Book Section %A Kernighan, B. W. %A Richie, D. M. %D 1979 %T The M4 macro processor %B Unix Programmer's Manual %I Bell Laboratories %C Murray Hill, NJ %0 Journal Article %A Keyes, R.W. %D 1975 %T Physical Limits in Digital Electronics %J Proceedings of the IEEE %V 63 %P 740-767 %0 Journal Article %A Keyes, R.W. %D 1977 %T Physical Limits in Semiconductor Electronics %J Science %V 195 %P 1230-1235 %0 Report %A Keyes, R.W. %D 1979 %T Very High Speed Large Scale Integration %0 Conference Proceedings %A Khokhar, Asfaq %A Lin, Wei-Ming %A Prasanna, Viktor K. %D 1991 %T Stereo and Image Matching on Fixed Size Mesh Arrays %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 331-341 %0 Conference Proceedings %A Khokhar, A. %A Ghafoor, A. %D 1994 %T A heterogeneous processing (HP) framework for multimedia query processing %J Proceedings Heterogeneous Computing Workshop %I IEEE Computer Society Press %C Cancun, Mexico %P 51-7 %K heterogeneous processing framework; multimedia query processing; hierarchical computational model; hierarchical data abstraction model; face recognition; scene matching; speech recognition; parallel processing ; computer vision ; image processing ; artificial intelligence; multimedia databases; speech processing; content-based retrieval techniques; image understanding algorithms; signal processing algorithms; parallel coarse-grained symbolic algorithms ; parallel fine-grained numeric algorithms ; MIMD algorithms; SIMD algorithms; hierarchical model ARTIFICIAL INTELLIGENCE; COMPUTER VISION ; DATA STRUCTURES; DISTRIBUTED DATABASES; FACE RECOGNITION; MULTIMEDIA SYSTEMS; PARALLEL ALGORITHMS; SPEECH RECOGNITION %X Defines a novel system based on a hierarchical computational and data abstraction model to handle multimedia queries involving face recognition, scene matching, and speech recognition. For this purpose, the system integrates the state-of-the-art research in diverse areas of the computational sciences, including parallel processing, computer vision and image processing , artificial intelligence, multimedia databases, and speech and signal processing. This system uses a heterogeneous processing framework consisting state-of-the-art image understanding and signal processing algorithms in addition to content-based retrieval techniques. These algorithms comprise of parallel coarse-grained (MIMD) symbolic and fine-grained (SIMD) numeric algorithms at various levels of this hierarchical model. %0 Conference Proceedings %A Khokhar, Achfaq A. %A Cook, Gregory W. %A Jamieson, Leah H. %A Delp, Edward J. %D 1994 %T Coarse-grained Algorithms and Implementations of Structural Indexing-based Object Recognition on Intel Touchstone Delta %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 279-283 %0 Journal Article %A Kirkpatrick, S. %A Gelatt, C.D.Jr. %A Vecchi, M.P. %D 1983 %T Optimization by Simulated Annealing %J Science %V 220 %N 4598 %P 671-680 %0 Conference Proceedings %A Kistler, J. %A Webb, J. A. %D 1991 %T Connected Components with Split and Merge %J International Parallel Processing Symposium %E Kumar, V. K. Prasanna %I IEEE Computer Society Press %C Anaheim, Ca %P 194-201 %0 Book %A Knuth, D. E. %D 1973 %T Fundamental Algorithms %I Addison-Wesley %C Reading, Massachusetts %V 1 %0 Book %A Knuth, D.E. %D 1973 %T Sorting and Searching %I Addison-Wesley %C Reading, Massachusetts %V 3 %0 Journal Article %A Knuth, D. E. %A Morris, J. H. %A Pratt, V.R. %D 1977 %T Fast Pattern Matching in Strings %J SIAM Journal of Computing %V 6 %N 2 %P 323-350 %0 Book %A Knuth, D.E. %D 1981 %T Seminumerical Algorithms %I Addison-Wesley %C Reading, Massachusetts %V 2 %0 Journal Article %A Knuth, D. E. %D 1987 %T Digital Halftones by Dot Diffusion %J ACM Transactions on Graphics %V 6 %N 4 %P 245-73 %0 Book %A Kogge, P. M. %D 1981 %T The Architecture of Pipelined Computers %I McGraw Hill %C New York %0 Report %A Koikkalainen, P. and Sauer, F. %D 1990 %T Architecture independent multicomputing via a self-distributing commmunications harness %I The Information Processing Laboratory, Lappeenranta University of Technology %0 Conference Proceedings %A Koller, K.W. %A Lauther, U. %D 1977 %T The Siemens-AVESTA System for Computer Aided Design of MOS Standard-Cell Circuits %J Fourteenth Design Automation Conference %0 Conference Proceedings %A Kondo, T. %A Tada, S. %A Miyahara, S. %D 1988 %T Kanji Character Recognition Unit with Hand-Scanner using SIMD Processor %J Visual Communications and Image Processing '88 %C Cambridge, MA %P 476-83 %0 Journal Article %A Konstaninides, K. %D 1994 %T The Khoros Software Development Environment for Image and Signal Processing. %J Ieee transactions on image processing %V 3 %N 4 %P 243-252 %0 Journal Article %A Konstantinides, K. %A Rasure, J. R. %D 1994 %T The Khoros software development environment for image and signal processing %J Ieee Transactions on Image Processing %V 3 %N 3 %P 243-52 %K Khoros software development environment; DSP tools; image processing ; data flow visual language systems; block diagram; integrated software development environment; information processing; visualization; digital signal processing IMAGE PROCESSING ; INTEGRATED SOFTWARE; PARALLEL LANGUAGES; PROGRAMMING ENVIRONMENTS; SIGNAL PROCESSING; SOFTWARE TOOLS; VISUAL LANGUAGES; VISUAL PROGRAMMING %X Data flow visual language systems allow users to graphically create a block diagram of their applications and interactively control input, output, and system variables. Khoros is an integrated software development environment for information processing and visualization. It is particularly attractive for image processing because of its rich collection of tools for image and digital signal processing. This paper presents a general overview of Khoros with emphasis on its image processing and DSP tools. Various examples are presented and the future direction of Khoros is discussed. %0 Conference Proceedings %A Koren, I. %D 1981 %T A Reconfigurable and Fault-Tolerant VLSI Multiprocesor Array %J The 8th Annual Symposium on Computer Architecture %P 442 %0 Journal Article %A Kosaka, A. %A Kak, A.C. %D 1992 %T Fast Vision-Guided Mobile Robot Navigation Using Model-Based Reasoning and Prediction of Uncertainties %J Cvgip - Image Understanding %V 56 %N 3 %P 271-329 %0 Journal Article %A Kosaraju, S.R. %D 1975 %T Speed of Recognition of Context-Free Languages by Array Automata %J SIAM J. on Computing %V 4 %P 331-340 %0 Conference Proceedings %A Krasawa, T. %A Obata, M. %A Konda, A. %A Shimizu, Y. %D 1993 %T Parallel image processing for defect %J Transputer/Occam Japan %P 161-9 %X An automatic inspection system for complicated structures such as textile products is developed with transputers. This system uses parallel image processing with a layered structure of transputers and is coded in OCCAM. To carry out this processing, a P-tile method, a shift watcher (SW) and a window watcher (WW) are used. The P-tile method realizes the binarization of input images. The SW and the WW are the boolean operators for noise reduction and defect identification. This system is sufficiently effective for the actual factory inspection. %0 Journal Article %A Krikelis, A. %D 1991 %T Computer Vision Applications with the Associative String Processor %J Journal of Parallel and Distributed Computing %V 13 %N 2 %P 170-84 %0 Journal Article %A Kroeger, J.H. %A Tozun, O.N. %D 1980 %T CAD Pits Semicustom Chips against Standard Slices %J Electronics %V 53 %N 15 %P 119-123 %0 Conference Proceedings %A Kshirsagar, S. P. %A Hobson, C. A. %A Hartley, D. A. %A Harvey, D. M. %D 1993 %T Image processing system architecture using parallel arrays of digital signal processors %J Proceedings of the Spie The International Society for Optical Engineering %P 14-16 %X Advantages and limitations of SIMD and MIMD architectures are briefly discussed. A parallel image processing system based on MIMD architecture has been developed using multiple digital signal processors which can communicate through an interconnection network. Texas Instruments TMS320C40 digital signal processors have a powerful floating point CPU supported by fast parallel communication ports, a DMA coprocessor and two memory interfaces. A five processor system is described. The EISA bus is used as the host interface and VISION bus is used to transfer images between the processors. The system is used for automated non-contact inspection in which electro-optic signals are processed to identify manufacturing problems. %0 Conference Proceedings %A Kshirsagar, S. P. %A Harvey, D. M. %A Hartley, D. A. %A Hobson, C. A. %D 1994 %T Design and application of parallel TMS320C40-based image processing system %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 10/1-5 %K parallel image processing system ; medical applications; noncontact inspection; Texas Instruments; TMS320C40 digital signal processor; industrial applications; high resolution images DIGITAL SIGNAL PROCESSING CHIPS; IMAGE PROCESSING EQUIPMENT; INSPECTION; PARALLEL PROCESSING %X An image processing system based upon Texas Instruments TMS320C40 digital signal processor is currently being applied to non-contact inspection of medical and industrial applications. The system is capable of manipulating high resolution images. %0 Book %A Kuck, D.J. %D 1978 %T The Structure of Computers and Computations %I John Wiley & Sons %C New York %V 1 %0 Journal Article %A Kuck, D. J. %A Davidson, E. S. %A Lawrie, D. H. %A Sameh, A. H. %D 1986 %T Parallel Supercomputing: Today and the Cedar Approach %J Science %V 231 %N 4741 %P 967-74 %0 Conference Proceedings %A Kuehn, J. T. %A Schwederski, T. %A Siegel, H. J. %D 1985 %T Design of a 1024-processor PASM system %J 1st International Conference on Supercomputing Systems %C St. Petersburgh, FL %P 603-612 %0 Conference Proceedings %A Kuhn, R. %D 1982 %T Yield Enhancement by Fault Tolerant Systolic Arrays %J Proceedings of USC Workshop on VLSI & Modern Signal Processing %P 145-152 %0 Book Section %A Kumar, V. %A Rao, V. N. %D 1990 %T Scalable Parallel Formulations of Depth-First Search %B Parallel Algorithms for Machine Intelligence and Vision %I Springer-Verlag %P 1-41 %0 Report %A Kumar, V. %A Gupta, A. %D 1992 %T Analyzing Scalability of Parallel Algorithms and Architectures %I Army High Performance Computing Research Center, University of Minnesota %R 92-020 %0 Generic %A Kung, H. T. %A Leiserson, C. E. %D 1978 %T Systolic Array Apparatuses for Matrix Computations %0 Conference Proceedings %A Kung, H.T. %D 1979 %T Let's Design Algorithms for VLSI Systems %J Proceedings of Conference on Very Large Scale Integration: Architecture, Design, Fabrication %P 65-90 %0 Conference Proceedings %A Kung, H. T. %A Leiserson, C. E. %D 1979 %T Systolic Arrays (for VLSI) %J Sparse Matrix Proceedings 1978 %E Duff, I. S. and Stewart, G. W. %P 256-282 %0 Generic %A Kung, H.T. %D 1980 %T Notes on VLSI Computation %0 Conference Proceedings %A Kung, H.T. %D 1980 %T Special-Purpose Devices for Signal and Image Processing: An Opportunity in VLSI %J Proceedings of the SPIE, Vol. 241, Real-Time Signal Processing III %P 76-84 %0 Conference Proceedings %A Kung, H.T. %D 1980 %T The Structure of Parallel Algorithms %J Advances in Computers, Volume 19 %E Yovits, M.C. %I Academic Press %C New York %P 65-112 %0 Conference Proceedings %A Kung, H.T. %D 1980 %T VLSI System and Computation %J Proceedings of International Computer Symposium 1980 %C Taipei, Taiwan %P 661-670 %0 Conference Proceedings %A Kung, H.T. %A Lehman, P.L. %D 1980 %T Systolic (VLSI) Arrays for Relational Database Operations %J Proceedings of ACM-SIGMOD 1980 International Conference on Management of Data %I ACM %P 105-116 %0 Conference Proceedings %A Kung, H.T. %D 1981 %T Use of VLSI in Algebraic Computation: Some Suggestions %J Proceedings of the 1981 ACM Symposium on Symbolic and Algebraic Computation %E Wang, P.S. %P 218-222 %0 Conference Proceedings %A Kung, S.Y. %D 1981 %T A Matrix Data Flow Language for Parallel Matrix Operations Based on Computational Wavefront Concept %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 235-244 %0 Conference Proceedings %A Kung, S.Y. %A Bhaskar Rao, D.V. %D 1981 %T Highly Parallel Architectures for Solving Linear Equations %J Proc. ICASSP '81 %C Atlanta, Ga. %P 39-42 %0 Conference Proceedings %A Kung, S.Y. %A Hu, Y.H. %D 1981 %T Fast and Parallel Algorithms for Solving Toeplitz Systems %J Proceedings of International Symposium on Mini and Microcomputers in Control and Measurement %C San Francisco, California %0 Edited Book %A Kung, H.T. %A Sproull, R.F. %A Steele, G.L., Jr. %D 1981 %T Proceedings of CMU Conference on VLSI Systems and Computations %I Computer Science Press %0 Conference Proceedings %A Kung, H. T. %A Picard, R. L. %D 1981 %T Hardware pipelines for multi-dimensional convolution and resampling %J Computer Architecture for Pattern Analysis and Image Database Management %I IEEE Computer Society %C Hot Springs, VA %P 273-278 %0 Journal Article %A Kung, H.T. %D 1982 %T Why Systolic Architectures? %J Computer Magazine %V 15 %N 1 %P 37-46 %0 Conference Proceedings %A Kung, S.Y. %A Gal-Ezer, R.J. %D 1982 %T Synchronous vs. Asynchronous Computation in VLSI Array Processors %J Proceedings of SPIE Symposium, Vol. 341, Real-Time Signal Processing V %P 53-65 %0 Conference Proceedings %A Kung, H.T. %A Song, S.W. %D 1982 %T A Systolic 2-D Convolution Chip %J Multicomputers and Image Processing: Algorithms and Programs %E Preston, K., Jr. and Uhr, L. %I Academic Press %P 373-384 %0 Conference Proceedings %A Kung, H.T. %D 1983 %T A High Performance Microprocessor Chip to Be Used in Groups of Hundreds %J Proceedings of IEEE EASCON '83 %P 251-258 %0 Conference Proceedings %A Kung, H.T. %D 1983 %T On the Implementationz|z|z|z|~ and Use of Systolic Array Processors %J Proceedings of International Conference on Computer Design: VLSI in Computers %P 370-373 %0 Journal Article %A Kung, H.T. %A Ruane, L.M. %A Yen, D.W.L. %D 1983 %T Two-Level Pipelined Systolic Array for Multidimensional Convolution %J Image and Vision Computing %V 1 %N 1 %P 30-36 %0 Conference Proceedings %A Kung, H.T. %D 1983 %T Two-Level Pipelined Systolic Arrays for Matrix Multiplication, Polynomial Evaluation and Discrete Fourier Transform %J Proceedings of the Workshop on Dynamical Behaviour of Automata: Theory and Applications %I Academic Press %0 Conference Proceedings %A Kung, H.T. %D 1983 %T VLSI, Computer Science, and Synergetic Research %J Proceedings of the ACM 11th Annual Computer Science Conference %P 17-19 %0 Journal Article %A Kung, S-Y %A Hu, Y. H. %D 1983 %T A Highly Concurrent Algorithm and Pipelined Architecture for Solving Toeplitz Systems %J IEEE Transactions on Acoustics, Speech, and Signal Processing %V ASSP-31 %N 1 %P 66-76 %0 Conference Proceedings %A Kung, H.T. %A Yu, S.Q. %D 1983 %T Integrating High-Performance Special-Purpose Devices into a System %J VLSI Architecture %E Randel, B. and Treleaven, P.C. %P 205-211 %0 Conference Proceedings %A Kung, H.T. %D 1984 %T Systolic Algorithms for the CMU Warp Processor %J Proceedings of the Seventh International Conference on Pattern Recognition %P 570-577 %0 Conference Proceedings %A Kung, H.T. %D 1984 %T Systolic Algorithms %J Large Scale Scientific Computation %E Parker, S.V. %I Academic Press %P 127-139 %0 Journal Article %A Kung, H.T. %A Lam, M. %D 1984 %T Wafer-Scale Integration and Two-Level Pipelined Implementations of Systolic Arrays %J Journal of Parallel and Distributed Computing %V 1 %N 1 %P 32-63 %0 Conference Proceedings %A Kung, H.T. %A Lin, W.T. %D 1984 %T An Algebra for Systolic Computation %J Elliptic Problem Solvers II %E Birkhoff, G. and Schoenstadt, A. %I Academic Press %P 141-160 %0 Conference Proceedings %A Kung, H.T. %A Menzilcioglu, O. %D 1984 %T Warp: A Programmable Systolic Array Processor %J Proceedings of SPIE Symposium, Vol. 495, Real-Time Signal Processing VII %P 130-136 %0 Conference Proceedings %A Kung, H.T. %A Picard, R.L. %D 1984 %T One-Dimensional Systolic Arrays for Multidimensional Convolution and Resampling %J VLSI for Pattern Recognition and Image Processing %E Fu, King-sun %I Springer-Verlag %P 9-24 %0 Journal Article %A Kung, H.T. %D 1985 %T Memory Requirements for Balanced Computer Architectures %J Journal of Complexity %V 1 %N 1 %P 147-157 %0 Book %A Kung, S.Y. %A Whitehouse, H.J. %A Kailath, T. %D 1985 %T VLSI and Modern Signal Processing %I Prentice-Hall %0 Conference Proceedings %A Kung, H.T. %A Webb, J.A. %D 1985 %T Global Operations on the CMU Warp Machine %J Proceedings of 1985 AIAA Computers in Aerospace V Conference %P 209-218 %0 Journal Article %A Kung, H. T. %A Webb, J. A. %D 1986 %T Mapping Image Processing Operations onto a Linear Systolic Machine %J Distributed Computing %V 1 %N 4 %P 246-57 %0 Generic %A Kung, H. T. %D 1986 %T Bibliography of Systolic Papers %0 Journal Article %A Kung, H. T. %D 1988 %T Deadlock Avoidance for Systolic Communication %J Journal of Complexity %V 4 %N 2 %P 87-105 %0 Conference Proceedings %A Kung, H. T. %D 1988 %T Systolic Communication %J Proceedings of the International Conference on Systolic Arrays %C San Diego, California %P 695-703 %0 Journal Article %A Kung, H. T. %D 1988 %T Computational Models for Parallel Computers %J Philosophical Transactions of the Royal Society %V A %N 326 %P 357-371 %0 Conference Proceedings %A Kung, H. T. %D 1988 %T Warp Experience: We Can Map Computations onto a Parallel Computer Efficiently %J Conference Proceedings of 1988 International Conference on Supercomputing %I ACM %C St. Malo, France %P 668-675 %0 Conference Proceedings %A Kung, H. T. %D 1989 %T Network-Based Multicomputers: Redefining High Performance Computing in the 1990s %J Proceedings of Decennial Caltech Conference on VLSI %C Pasadena, California %0 Journal Article %A Kurashige, M. %D 1993 %T Recent progress of optical neural network technologies for image processing %J Journal of the Institute of Image Electronics Engineers of Japan %V 22 %N 2 %P 137-42 %X Neurocomputers are expected to process incomplete input information. Optical electronics technology, composed mainly of optical fiber telecommunication and semiconductor laser technology has been developed since the 1980s as technology applicable to neurocomputers with new architectures such as super-parallel machines. The author describes the neurocomputer, and an optical neurodevice which has a function unique to light and is hard to realize by Si-LSI technology. %0 Journal Article %A Kyuma, K. %D 1993 %T Photoelectronic coexistent neural network %J Journal of the Institute of Electrical Engineers of Japan %V 113 %N 4 %P 279-86 %K photoelectronic coexistent neural network; highly integrated wiring; direct image processing ; optical-technology-applied neural network; optical neuro devices; variable sensitivity photodetector; memory-built-in optical neural network chips; artificial retina chips; parallel light access neuro chips ; super-large scale optical neural networks %X It takes too much time to perform simulation on a digital computer and consecutive processing of a neural network, and it becomes necessary to develop a high-speed computer for real time processing and miniaturization of the system, making the most of characteristics of space parallelism of optical technology, highly integrated wiring, direct image processing , and large memory capacity. The author describes the basic structure and principles of the neural network, basic architecture of the optical-technology-applied neural network, and optical neuro devices such as the variable sensitivity photodetector (VSPD), memory-built-in optical neural network chips, artificial retina chips, parallel light access neuro chips and super-large scale optical neural networks. %0 Journal Article %A Ladner, R.E. %A Fischer, M.J. %D 1980 %T Parallel Prefix Computation %J Journal of the ACM %V 27 %N 4 %P 831-838 %0 Conference Proceedings %A Lalwaney, P. %A Koren, I. %D 1994 %T Reconfigurable optical interconnects for computer vision applications %J Proceedings of the First International Workshop on Massively Parallel Processing Using Optical Interconnections %I Ieee Comput. Soc. Press %C Los Alamitos, Ca, Usa %P 224-36 %K reconfigurable optical interconnects; massively parallel systems ; network configurations; application-dependent; computer vision ; link speeds; link latencies; system size; message size; network topologies COMPUTER VISION ; OPTICAL INTERCONNECTIONS; PARALLEL ARCHITECTURES %X Evaluates the advantages of reconfigurable optical interconnects within massively parallel systems due to their ability to provide versatile application-dependent network configurations. Furthermore, they are being considered as alternatives to electronic interconnects within high-performance computers because of their advantages of high bandwidth, low wire density and low power requirement at high data rates. Fiber optic interconnects based on wavelength division multiplexing and free-space holographic interconnects are two classes of optical interconnects that can support network reconfiguration. Using computer vision applications, the authors compare these two classes of optical interconnects with electronic interconnects taking into account the combined effects of link speeds, link latencies, system size, message size and network topologies feasible with current implementation capabilities. %0 Conference Proceedings %A Lam, M. %A Mostow, J. %D 1983 %T A Transformational Model of VLSI Systolic Design %J Proceedings of the 6th International Symposium on Computer Hardware Description Languages and their Applications %E Uehara, T. and Barbacci, M. %P 65-77 %0 Thesis %A Lam, M. %D 1987 %T A Systolic Array Optimizing Compiler %0 Conference Proceedings %A Lam, M. %D 1988 %T Software Pipelining: An Effective Scheduling Technique for VLIW Machines %J ACM Sigplan '88 Conference on Programming Language Design and Implementation. %0 Conference Proceedings %A Lam %A Monica %D 1988 %T Compiler Optimizations for Asynchronous Systolic Array Programs %J Proc. Fifteenth Annual ACM Symposium on Principles of Programming Languages %0 Conference Proceedings %A Lamdan, Y. %A Wolfson, H. J. %D 1988 %T Geometric Hashing: A General and Efficient Model-Based Recognition Scheme %J Second International Conference on Computer Vision %C Tampa, FL %P 218-49 %0 Journal Article %A Lane, R. A. %A Thacker, N. A. %A Seed, N. L. %D 1994 %T Stretch-correlation as a real-time alternative to feature based stereo matching algorithms %J Image and Vision Computing %V 12 %N 4 %P 203-12 %K feature based stereo matching algorithms; robust stereo vision algorithm; industrial applications; visual appearance; illumination sources; correlation-based approaches; Stretch-Correlation; warped image blocks; front-o-parallel constraint FEATURE EXTRACTION; REAL-TIME SYSTEMS; STEREO IMAGE PROCESSING %X We have analysed the requirements for a robust stereo vision algorithm for use in typical industrial applications. For such applications the views obtained in the two cameras have large differences in visual appearance due to the orientation difference between the two cameras and the close proximity of illumination sources. We have concluded that for this category of problem, feature-based methods should be more robust than conventional, area-based approaches, and this conclusion appears to be borne out in the published literature. However, correlation-based approaches are more suited to efficient implementation on available hardware. The technique which we have developed, called Stretch-Correlation, is based on the cross-correlation of warped image blocks which have been preprocessed to maximize the useful information content. Our new method models the severe warping effects encountered in difficult stereo problems and effectively relaxes the front-o- parallel constraint which is normally imposed in area-based disparity calculation. This algorithm imposes effectively most of the local constraints present in feature-based algorithms, and can be efficiently implemented on available hardware. %0 Conference Proceedings %A Lanser, S. %A Eckstein, W. %D 1992 %T A modification of Deriche's approach to edge detection %J 11th IAPR International Conference on Pattern Recognition. Conference C: Image, Speech, and Signal Analysis %I IEEE Computer Society Press %C The Hague, Netherlands %P 633-7 %K Canny filter. Edge detection. FIR-filter. IIR-filters. Deriche-filter. Shen-filter %X Canny (1983) presented criteria for measuring the quality of edge detectors and derived an optimal FIR-filter for step edges by optimizing them. Four years later Deriche proposed an approach to edge detection based on Canny's design utilizing IIR-filters which can be implemented very efficiently and recursively. Using the Deriche-filter leads to a distortion of the amplitudes of the edges depending on their direction. In this paper, it is shown that these distortions are systematic errors which can be eliminated by a simple modificaiton of the edge deteciton procedure. Becuase of its obvious 'kinship' to the Derice-filter the Shen-filter has been included in the investigations. %0 Conference Proceedings %A Laplante, P. A. (Fairleigh Dickinson Univ., Madison, NJ, USA) %D 1992 %T A real-time image processing language? %J Real Time Computing. Proceedings of the Nato Advanced Study Institute %E Halang, W.A. %E Stoyenko, A.D. %C Sint Maarten, Dutch Antilles %P 701 %K real-time image processing language ; multimedia systems; virtual reality; simulation; remote command and control; standard language; execution time optimization; concurrent processing; synchronization; timing constraints; response times; compile time; efficient image description; image storage; image manipulation; digital electronic architectures; sequential architectures; parallel architectures ; bulk optical architectures; object-oriented paradigms; built-in exception handling; storage optimization IMAGE PROCESSING ; PROGRAMMING LANGUAGES; REAL-TIME SYSTEMS %X Summary form only given, as follows. Real-time image processing is widely used in multimedia systems, virtual reality and simulation, and remote command and control. Unfortunately, there is no standard language to support image processing in a real-time framework. Moreover, it is unwise to assume that other real-time programming languages can support the specialized needs of image processing . A real-time image processing language must provide those constructs needed for real-time as well as those for image processing . These include: methods for enunciation of concurrent processing, synchronization, and timing constraints, while in some way guaranteeing response times at compile time; a framework for efficient image description, storage and manipulation; and support for various digital electronic, sequential and parallel architectures and possibly bulk optical architectures. Other desirable features include: support for object-oriented paradigms; built-in exception handling; and storage and execution time optimization strategies. At this juncture, there is apparently no language with these features. It is therefore imperative that more research be focused on the development of said language. %0 Conference Proceedings %A Laprie, J.C. %D 1985 %T Dependable Computing and Fault Tolerance: Concepts and Terminology %J 15th International Symposium on Fault-Tolerant Computing Systems %I IEEE %0 Book %A Lasser, C. %D 1986 %T The Complete *Lisp Manual %I Thinking Machines Corporation %0 Conference Proceedings %A Lavin, M. %A Flickner, M. %D 1989 %T An Object-Oriented Language for Image and Vision Execution (OLIVE) %J Workshop on Tools for Artificial Intelligence: Architectures, Languages, and Algorithms %C Fairfax, VA %P 598-607 %0 Conference Proceedings %A Lazarus, R. B. %A Meyer, F. M. %D 1993 %T Realization of a dynamically reconfigurable preprocessor %J Proceedings of the Ieee National Aerospace and Electronics Conference. NAECON 1993 %I IEEE %C Dayton, OH %6 2 %P 74-80 %K dynamically reconfigurable preprocessor; field programmable gate arrays; FPGA; high-speed algorithm-specific processing architectures; avionic signal processing; low-cost; flexible alternative; radar; communication processing; image enhancement; configurable logic devices; processing architectures; low-level algorithmic functions; subroutines; software algorithm; parallel architecture ; pipelined architecture AEROSPACE COMPUTING; DIGITAL SIGNAL PROCESSING CHIPS; IMAGE PROCESSING EQUIPMENT; LOGIC ARRAYS; LOGIC DESIGN; PARALLEL ARCHITECTURES; PIPELINE PROCESSING; RECONFIGURABLE ARCHITECTURES; SIGNAL PROCESSING EQUIPMENT %X Our research demonstrates the feasibility of employing field programmable gate arrays (FPGAs) to realize high-speed algorithm-specific processing architectures for avionic signal processing applications. Architectures composed of FPGAs provide a low-cost and flexible alternative to custom hard-wired preprocessors and a lower-cost, physically smaller alternative to massively parallel processors (both SIMD and MIMD machines). Algorithm segments which require processing hundreds of millions of operations per second have been mapped into a single FPGA device. This technology may ultimately fill a range of processing requirements in the areas of radar and communication processing as well as image enhancement applications. The application of configurable logic devices allows realization of processing architectures to efficiently compute low-level algorithmic functions, or segments. Reconfiguration of FPGAs to implement several algorithm segments is analogous to selecting subroutines to form a software algorithm suite in a conventional processor, since it can be accomplished without hardware modification. %0 Conference Proceedings %A Le Moigne, J. %D 1994 %T Parallel registration of multi-sensor remotely sensed %J Wavelet Applications. Proceedings of the Spie. The International Society for Optical Engineering %C Orlando, FL %P 5-8 %K multi-sensor remotely sensed imagery; wavelet coefficients; parallel registration ; image registration; remote sensing systems; coarse-resolution viewing satellite sensors; input image; reference image; ground control points; deformation model; decomposition; reconstruction; SIMD massively parallel computer ; MasPar MP-1 DATA ANALYSIS; IMAGE PROCESSING ; PARALLEL PROCESSING; RADIOMETRY; REMOTE SENSING; SENSOR FUSION; WAVELET TRANSFORMS %X Due to the increasing amount and diversity of remotely sensed data, image registration is becoming one of the most important issues in remote sensing. The most common approach to image registration is to choose, in both input image and reference image, some well defined ground control points (GCP's), and then to compute the parameters of a deformation model. The main difficulty lies in the choice of the GCP's. In our work, a parallel implementation of decomposition and reconstruction by wavelet transforms has been developed on a single instruction multiple data (SIMD) massively parallel computer, the MasPar MP-1. Utilizing this framework, we show how maxima of wavelet coefficents, which can be used for finding ground control points of similar resolution remotely sensed data (1993), can also form the basis of the registration of very different resolution data, such as data from the NOAA advanced very high resolution radiometer (AVHRR) and from the Landsat/thematic mapper (TM). %0 Conference Proceedings %A Lea, R. M. %D 1990 %T ASP Modules: Building Blocks for Application-Specific Massively Parallel Processors %J International Conference on Application Specific Array Processors %C Princeton, N. J. %P 493-504 %0 Journal Article %A Lea, R. M. and Jalowiecki, I. P. %D 1991 %T Associative Massively Parallel Computers %J IEEE Proceedings %V 79 %N 4 %P 469-79 %0 Conference Proceedings %A LeClerc, Y. %D 1989 %T Image and Boundary Semnetation via Minimal-Length Encoding on the Connection Machine %J Image Understanding Workshop %I Defense Advanced Research Projects Agency %C Palo Alto, CA %P 1056-65 %0 Conference Proceedings %A Lee, S.-Y. %A Aggarwal, J. K. %D 1987 %T Image Processing on Multiprocessor Systems %J International Conference on Systems, Man, and Cybernetics %C Alexandria, VA %P 20-3 %0 Journal Article %A Lee, S.-Y. %A Aggarwal, J. K. %D 1987 %T Parallel 2-D Convolution on a Mesh Connected Array Processor %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 9 %N 4 %P 590-594 %X Hamiltonian paths for moviing intermediate results in convolution. %0 Conference Proceedings %A Lefer, Wilfrid %D 1993 %T An Efficient Parallel Ray Tracing Scheme for Distributed Memory Parallel Computers %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, California %P 77-80 %0 Conference Proceedings %A Lehman, P.L. %D 1981 %T A Systolic (VLSI) Array for Processing Simple Relational Queries %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 285-295 %0 Conference Proceedings %A Leighton, F.T. %A Miller, G.L. %D 1981 %T Optimal Layouts for Small Shuffle-Exchange Graphs %J VLSI 81 %I Academic Press %P 289-299 %0 Conference Proceedings %A Leighton, F.T. %A Leiserson, C.E. %D 1982 %T Wafer-Scale Integration of Systolic Arrays %J Proceedings of 23rd Annual Symposium on Foundations of Computer Science %P 279-311 %0 Conference Proceedings %A Leiserson, C.E. %D 1979 %T Systolic Priority Queues %J Proceedings of Conference on Very Large Scale Integration: Architecture, Design, Fabrication %P 199-214 %0 Conference Proceedings %A Leiserson, C.E. %D 1980 %T Area-Efficient Graph Layouts (for VLSI) %J Proceedings of 21st Annual Symp. on Foundations of Computer Science %P 270-281 %0 Thesis %A Leiserson, C.E. %D 1981 %T Area-Efficient VLSI Computation %0 Conference Proceedings %A Leiserson, C.E. %A Pinter, R.Y. %D 1981 %T Optimal Placement for River Routing %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 126-142 %0 Journal Article %A Leiserson, C.E. %A Saxe, J.B. %D 1983 %T Optimizing Synchronous Systems %J Journal of VLSI and Computer Systems %V 1 %N 1 %P 41-68 %0 Journal Article %A Leiserson, C. E. %D 1985 %T Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing %J IEEE Transactions on Computers %V 34 %N 10 %P 892-901 %0 Conference Proceedings %A Lengauer, T. %A Mehlhorn, K. %D 1981 %T On the Complexity of VLSI-Computations %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 89-99 %0 Conference Proceedings %A Leung, K. %A Chu, A. %A Wong, C. %A Chu, E. %A Jin, M. %D 1993 %T The Magellan UNIX-based SAR processor %J Igarss '93 %E Fujimura, S. %I IEEE %C Tokyo, Japan %P 1121-4 %X Through three cycles of radar data collection at Venus that ended in September 1992, the Magellan mission has collected radar image data covering over 99% of the Venusian planet surface. The data reduction process of deriving image data from radar signal data has been performed primarily on the Primary SAR Processor (PSP) at the Magellan Radar Data Processing Facility (MRDPF). The MRDPF is currently scheduled for de-commissioning in September 1993 after completing its third year of SAR data processing operations. The Magellan UNIX-based SAR Processor (USP) was developed with the objective of preserving Magellan data processing capability. The USP development was a clear departure from utilizing custom-built hardware for SAR processor implementation. It followed the current trend in SAR processor development in utilizing commercial concurrent processing technology and parallel computing machinery. The USP development is presented with discussions focused on algorithm enhancements made possible by the removal of hardware constraints and pertinent implementation considerations that affected throughput and image quality. %0 Journal Article %A Levialdi, S. %D 1972 %T On Shrinking Binary Pictures %J Communications of the ACM %V 15 %N 1 %P 7-10 %0 Journal Article %A Levitt, K.N. %A Kautz, W.H. %D 1972 %T Cellular Arrays for the Solution of Graph Problems %J Communications of the ACM %V 15 %N 9 %P 789-801 %0 Conference Proceedings %A Lewicki, G. %A Cohen, D. %A Losleben, P. %A Trotter, D. %D 1984 %T MOSIS: Present and Future %J Proceedings of Conference on Advanced Research in VLSI %E Penfield, P. Jr. %I Artech House, Inc. %C Dedham, Massachusetts %P 124-128 %0 Conference Proceedings %A Lewicki, S. %A Meemong, Lee %A Chodas, P. %A DeJong, E. %D 1993 %T Stereo processing of Magellan SAR imagery performed on a transputer architecture %J Igarss '93 %E Fujimura, S. %I IEEE %C Tokyo, Japan %P 1786-8 %X The stereo processing of Magellan SAR imagery into digital elevation maps is presented. The algorithms used and their implementation on a parallel transputer architecture is explained. Results are given along with the effects of using mosaicked imagery and of errors in the spacecraft ephemeris. Ways of improving the knowledge of the spacecraft ephemeris are described. %0 Edited Book %A Li, H. %A Stout, Q.F. %D 1991 %T Reconfigurable Massively Parallel Computers %I Prentice-Hall %C Englewood Cliffs, NJ %0 Conference Proceedings %A Li, Z. N. %A Zhang, D. %D 1993 %T Real-time line-based motion stereo %J Proceedings Ieee International Conference on Robotics and Automation %I IEEE Computer Society Press %C Atlanta, GA %P 367-72 %K parallel hierarchical pyramidal algorithm ; line-based motion stereo; hybrid pyramid machine; real-time computer vision ; line merging; matching; 3-D Hough space; depth maps; linear features COMPUTER VISION ; PARALLEL ALGORITHMS; PARALLEL MACHINES; STEREO IMAGE PROCESSING %X A hybrid pyramid machine has been built for real-time computer vision applications. An algorithm for line-based motion stereo is presented. Input data is obtained from a single camera and a moving belt. A parallel and hierarchical (pyramidal) algorithm for line merging and matching is described. It is shown that the problem of matching lines among the multiple motion stereo images can be effectively carried out in a 3-D Hough space. Preliminary experimental results from the hybrid pyramid are presented. The system is capable of producing depth maps along the linear features in less than a second. %0 Generic %A Ligetts, D. %A McCluskey, G. %A McKeeman, W. M. %D 1982 %T Parallel LR Parsing %9 Technical Report TR-82-03, Wang Institute of Graduate Studies School of Information Technology, July, 1982 %0 Journal Article %A Ligon, W. B. %A Ramachandran, U. %D 1994 %T Evaluating multigauge architectures for computer vision %J Journal of parallel and distributed computing %V 21 %N 3 %P 323- %0 Conference Proceedings %A Lim, H.S. %A Binford, T.O. %D 1984 %T Survey of Array Processors %J Proceedings: ARPA Image Understanding Workshop %I Defense Information Agency %C New Orleans %P 334-343 %0 Report %A Lim, W. %A Agrawal, A. %A Nekludova, L. %D 1986 %T A Fast Parallel Algorithm for Labeling Connected Components in Image Arrays %I Thinking Machines Corporation %R 15 %0 Book Section %A Lim, W. %A Agrawal, A. %A Nekludova, L. %D 1989 %T A Fast Parallel Algorithm for Labeling Connected Components %B Parallel Processing for Computer Vision and Display %I Addison-Wesley %P 169-179 %0 Conference Proceedings %A Lin, Cho-Chin %A Prasanna, Viktor K. %A Khokhar, Ashfaq %D 1993 %T Scalable Parallel Extraction of Linear Features on MP-2 %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 352-361 %0 Generic %A Lindberg, Donald %D 1994 %T High Performance Computing and Communications Program %B AIPR Special Session: Image Information Processing on High Performance Computers %C Cosmos Club, Washington, D. C. %8 14 October %9 Invited lecture %0 Journal Article %A Linnik, U.V %D 1944 %T On the Least Prime in an Arithmetic Progression. I. The Basic Theorem %J Rec. Math. %V 15 %P 139-178 %0 Journal Article %A Lipton, R.J. %A Eisenstat, S.C. %A DeMillo, R.A. %D 1976 %T Space and Time Hierarchies for Classes of Control Structures and Data Structures %J Journal of the ACM %V 23 %N 4 %P 720-732 %0 Journal Article %A Liren, Liu %A Xuejun, Zhang %A Zhang, Zibei %D 1994 %T Gray-tone image processing by threshold superposition in an optical cellular-logic binary-image processor %J Applied Optics %V 33 %N 20 %P 4383-91 %X A parallel architecture for gray-tone image processing is proposed that utilizes the concept of threshold sum-superposition into a cellular two-layer logic binary-image processor. Various processing functions constituted by gray-tone dilation, erosion, fuzzy-logic operations, and arithmetic operations are obtained. The optoelectronic implementation is illustrated. %0 Conference Proceedings %A Little, J. J. %A Glelloch, G. %A Cass, T. %D 1987 %T Parallel Algorithms for Computer Vision on the Connection Machine %J In Image Understanding Workshop %I Defense Advanced Research Projects Agency %P 628-38 %0 Conference Proceedings %A Little, J. J. %A Blelloch, G. %A Cass, T. %D 1987 %T How To Program the Connection Machine for Computer Vision %J Computer Architecures for Pattern Analysis and Machine Intelligence %C Seattle, Washington %0 Conference Proceedings %A Little, J. %A Bulthoff, H. %A Poggio, T. %D 1987 %T Parallel optical flow computation %J Image Understanding Workshop %I Defense Advanced Research Projects Agency %C Los Angeles, CA %P 915-20 %0 Journal Article %A Little, J. J. %A Blelloch, G. E. %A Cass, T. A. %D 1989 %T Algorithmic Techniques for Computer Vision on a Fine-Grained Parallel Machine %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 11 %N 3 %P 244-57 %0 Conference Proceedings %A Little, James J. %A Barman, Rod %A Kingdon, Stewart %A Lu, Jiping %D 1991 %T Computational Architectures for Responsive Vision: the Vision Engine %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 233-240 %0 Conference Proceedings %A Little, James J. %A Kam, Johnny %D 1993 %T A Smart Buffer for Tracking Using Motion Data %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 257-266 %0 Conference Proceedings %A Little, James J. %D 1994 %T Vision Servers and Their Clients %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 295-299 %0 Conference Proceedings %A Liu, K.Y. %D 1981 %T Architecture for VLSI Design of Reed-Solomon Encoders %J Proceedings of Second Caltech Conference on Very Large Scale Integration %P 539-553 %0 Conference Proceedings %A Liu, M. J. %A Hasson, R. %A Ioannides, A. A. %D 1993 %T A transputer-based system for magnetic field tomography %J Transputer Applications and Systems '93. Proceedings of the %E Grebe, R. %E Hektor, J. %E Hilton, S.C. %E Jane, M.R. %E Welch, P.H. %I IOS Press %C Aachen, Germany %P 1290-7 %K transputer-based system; magnetic field tomography; brain activity; magnetoencephalographic signals; 3D estimates; processing requirements; parallel implementation ; T800 transputers; patient data analysis %X Magnetic field tomography (MFT) provides a view of brain activity derived from magnetoencephalographic (MEG) signals. The derivation of three-dimensional estimates, millisecond by millisecond, imposes huge processing requirements, which have been satisfied by a parallel implementation of the method on a network of 30 T800 transputers. This system has been fully tested and has been extensively used to analyse MEG data from both normal subjects and patients. %0 Journal Article %A Lopresti, D. P. %D 1987 %T P-NAC: A Systolic Array for Comparing Nucleic Acid Sequences %J Computer Magazine %V 20 %N 7 %P 98-99 %0 Journal Article %A Lourens, T. %A Petkov, N. %A Kruizinga, P. (Dept. of Math., Rijksuniv. Groningen, Netherlands) %D 1994 %T Large scale natural vision simulations %J Future Generation Computer Systems %V 10 %P 2-3 %X A computationally intensive approach to pattern recognition in images is developed and applied to face recognition. Similarly to previous work, we compute functional inner products of a two-dimensional input signal (image) with a set of two-dimensional Gabor functions which fit the receptive fields of simple cells in the primary visual cortex of mammals. The proposed model includes nonlinearities, such as thresholding, orientation competition and lateral inhibition. The output of the model is a set of cortical images each of which contains only edge lines of a particular orientation in a particular light-to-dark transition direction. In this way the information of the original image is split into different channels. The cortical images are used to compute a lower-dimension space representation for object recognition. The method was implemented on the Connection Machine CM-5 and achieved a recognition rate of 97% when applied to a large database of face images. %0 Journal Article %A Loveman, D. B. %D 1993 %T High Performance Fortran %J IEEE Parallel and Distributed Technology: Systems and Applications %V 1 %N 1 %P 25-42 %0 Thesis %A Lowerre, B. %D 1976 %T The Harpy Speech Recognition System %0 Conference Proceedings %A Luk, W.K. %D 1981 %T A Regular Layout for Parallel Multiplier of 0(log^2 n) Time %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 317-326 %0 Conference Proceedings %A Luk, Schimmel and %D 1986 %T A new systolic array for the singular value decomposition %J Fourth MIT Conference on Advanced Research in VLSI %0 Conference Proceedings %A Luk, W. %A Wu, T. %A Page, I. %D 1994 %T Hardware-software codesign of multidimensional programs %J Proceedings Ieee Workshop on FPGAs for Custom Computing Machines %E Buell, D.A. %E Pocek, K.L. %I IEEE Computer Society %C Napa Valley, CA %P 82-90 %X Presents a method for parametrised partitioning of multidimensional programs for acceleration using a hardware coprocessor. The method involves a divide-and-conquer structure, with the "divide" and "merge" phases carried out by a general-purpose processor, while the "conquer" phase is handled by application-specific hardware. The partitioning strategy has been captured in a simple functional language, and we have automated the production of partitioned programs in this language. Our approach has been tested on an FPGA-based system using a number of computer vision algorithms, including the Canny edge detector, and the performance is compared against executing the programs on the PC host. %0 Journal Article %A Lukacs, J. %A Vajda, F. %D 1994 %T Research Institute for Measurement and Computing Techniques-a Hungarian institute in a changing environment %J Computing & Control Engineering Journal %V 5 %N 2 %P 57-60 %K Research Institute for Measurement and Computing Techniques; Hungarian institute; changing environment; applied research and development; information technology; laboratory automation; industrial automation; parallel processing ; image processing ; protocol engineering; simulation COMPUTERISED CONTROL; DP INDUSTRY; IMAGE PROCESSING ; PARALLEL PROCESSING; RESEARCH INITIATIVES; SIMULATION %X The Research Institute for Measurement and Computing Techniques of the Hungarian Academy of Sciences was founded in it present form in 1992 for basic and applied research and development in the field of information technology. Its activities involve laboratory automation, industrial automation, parallel processing, image processing , protocol engineering and simulation. The Institute has a long history, starting as a nuclear electronics group in the 1950s, growing into a large establishment in the 1970s and finally changing to its present status as a genuine research institute. %0 Journal Article %A Lumia, R. %A Shapiro, L %A Zuniga, O. %D 1983 %T A New Connected Components Algorithm for Virtual Memory Computers %J Computer Vision, Graphics, and Image Processing %V 22 %P 287-300 %0 Conference Proceedings %A Lundstrom, S. F. and Barnes, G. H. %D 1980 %T A Controllable MIMD Architecture %J International Conference on Parallel Processing %C St. Charles, Illinois %P 19-27 %0 Journal Article %A Lyon, R.F. %D 1976 %T Two's Complement Pipeline Multipliers %J IEEE Transactions on Communications %V COM-24 %N 4 %P 418-425 %0 Generic %A Lyon, Richard F. %D 1980 %T Signal Processing with VLSI %0 Conference Proceedings %A Lyon, R. F. %D 1981 %T A Bit-Serial VLSI Architectural Methodology for Signal Processing %J First International Conference on Very Large Scale Integration %P 131-140 %0 Conference Proceedings %A Lyon, R.F. %D 1981 %T The Optical Mouse, and an Architectural Methodology for Smart Digital Sensors %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 1-19 %0 Conference Proceedings %A Ma, Kwan-Liu %A Painter, James S. %A Hansen, Chales D. %A Krogh, Michael F. %D 1993 %T A Data Distributed, Parallel Algorithm for Ray-Traced Volume Rendering %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, CA %P 15-22 %0 Book %A MacWilliams, F.J. %A Sloane, N.J.A. %D 1977 %T The Theory of Error-Correcting Codes %I North-Holland %C Amsterdam, Holland %0 Conference Proceedings %A Maeder, A. J. %A Bell, D. M. %D 1994 %T Parallel region-based progressive image compression %J Parallel Computing and Transputers. Pcat %E Arnold, D. %E Christie, R. %E Day, J. %E Roe, P. %I IOS Press %C Brisbane, Qld., Australia %P 110-15 %X A method for progressive compression of digital images based on modelling regional structure of the scene is described. The computational cost is high because several passes through the image data along different paths are required. The method requires several different stages of computation involving different groupings of data to be performed. This paper discusses appropriate approaches for parallelising the method, with particular relevance to coarse grain systems. %0 Generic %A Mago, G.A. %T A Network of Microprocessors to Execute Reduction Languages %0 Conference Proceedings %A Malachi, Y. %A Owicki, S.S. %D 1981 %T Temporal Specifications of Self-Timed Systems %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 203-212 %0 Journal Article %A Manning, F.B. %D 1977 %T An Approach to Highly Integrated, Computer-Maintained Cellular Arrays %J IEEE Transactions on Computers %V C-26 %N 6 %P 536-552 %0 Book Section %A Manning, L. J. %A Dew, P. M. %A Wang, H. %D 1988 %T Design and Analysis of Image Processing Algorithms for Programmable VLSI Array Processors %B Parallel Architectures and Computer Vision %E Page, I. %I Oxford University Press %P 217-42 %0 Journal Article %A Mansfield, P. %A Pykett, I.L. %D 1978 %T Biological and Medical Imaging by NMR %J Journal of Magnetic Resonance %V 29 %P 355-373 %0 Journal Article %A Maragos, Petros %D 1989 %T Pattern Spectrum and Multiscale Shape Representations %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 11 %N 7 %P 701-716 %0 Journal Article %A Maresca, M. %A Li, H. %D 1989 %T Connection Autonomy in SIMD Computers: A VLSI Implementation %J Journal of Parallel and Distributed Computing %V 7 %N 2 %P 302-20 %0 Journal Article %A Maresca, M. %A Li, H. %A Sheng, M. M. C. %D 1989 %T Parallel Computer Vision on Polymorphic Torus Architecture %J Machine Vision Applications %V 2 %N 4 %P 215-30 %0 Conference Proceedings %A Maresca, M. %D 1990 %T Packet Switching Algorithm for SIMD Computers and its Application to Parallel Computer Vision %J High-Speed Inspection Architectures, Barcoding and Character Recognition %I SPIE %P 206-14 %0 Book %A Marr, D. %D 1972 %T Vision: A Computational Investigation into the Human Processing and Representation of Information %I W. H. Freeman and Co. %C San Francisco %0 Book %A Marr, D. %D 1982 %T Vision %I W. H. Freeman and Company %0 Journal Article %A Marsh, B. %A Brown, C. %A LeBlanc, T. %A Scott, M. %A Becker, T. %A Quiroz, C. %A Das, P. %A Karlsson, J. %D 1992 %T The Rochester Checkers Player %J Computer %V 25 %N 2 %P 12-9 %0 Journal Article %A Marshall, M. %D 1980 %T VLSI Pushes Super-CAD Techniques %J Electronics %V 53 %N 17 %P 73-80 %0 Journal Article %A Martino, R. L. %A Johnson, C. A. %A Suh, E. B. %A Trus, B. L. %A Yap, T. K. %D 1994 %T Parallel computing in biomedical research %J Science %V 265 %N 5174 %P 902-8 %X Scalable parallel computer architectures provide the computational performance needed for advanced biomedical computing problems. The National Institutes of Health have developed a number of parallel algorithms and techniques useful in determining biological structure and function. These applications include processing electron micrographs to determine the three-dimensional structure of viruses, calculating the solvent-accessible surface area of proteins to help predict the three-dimensional conformation of these molecules from their primary structures, and searching for homologous DNA or amino acid sequences in large biological databases. Timing results demonstrate substantial performance improvements with parallel implementations compared with conventional sequential systems. %0 Conference Proceedings %A Masuzawa, T. %A Nakauchi, S. %A Wada, K. %A Hagihara, K. %A Tokura, N. %D 1983 %T Systolic Algorithm Description Language SADL and Support System for Systolic Algorithm Design %J Proceedings of 1983 International Symposium on VLSI Technology, Systems and Applications %0 Journal Article %A Matick, R. E. %D 1984 %T Architecture Implementation in the Design of Microprocessors %J IBM Systems Journal %V 23 %N 3 %P 264-280 %0 Journal Article %A Matsuda, K. %A Kawai, O. %D 1993 %T LSIs for image and video signal processing %J Journal of the Institute of Television Engineers of Japan %V 47 %N 11 %P 1483-7 %K image processing ; multimedia systems; 3D graphics; DSP chips; spatial filter; video signal processing; video image coding; decoding; LSI; RISC chips DIGITAL SIGNAL PROCESSING CHIPS; IMAGE CODING; IMAGE PROCESSING EQUIPMENT; LARGE SCALE INTEGRATION; VIDEO SIGNALS %X Among all the media such as text, voice and images, images have the strongest impact on people, but it is the most difficult to process because of its enormous amount of information. Accordingly, video image coding (compression) and decoding is indispensable technology for the construction of multimedia systems. Computer graphics is also attracting great interest for multimedia applications. The author describes recent development trends in image coding/decoding LSI, image processing LSI, and LSI for 3-dimensional graphics, referring particularly to image coding/decoding LSI for the MPEG and JPEG, image processing LSI such as a spatial filter, and a 3-D graphics accelerator which has many RISC chips and DSPs in parallel . %0 Conference Proceedings %A Matsuyama, T. %A Asada, N. %A Aoyama, M. %D 1993 %T Parallel Image Analysis on Recursive Torus Architecture %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 202-214 %0 Journal Article %A Matthaei, D. %A Frahm, J. %A Hasse, A. %A Hanicke, W. %D 1985 %T Regional Physiological Functions Depicted by Sequences of Rapid Magnetic Resonance Images %J The Lancet %V 2 %P 893 %0 Conference Proceedings %A Matthies, L. H. %A Thorpe, C. E. %D 1984 %T Experience with visual robot navigation %J IEEE OCEANS'84 Conference %I IEEE %P 594-7 %0 Conference Proceedings %A Matthies, L H. %A Shafer, S. A. %D 1986 %T Error modelling in stereo navigation %J Fall Joint Computer Conference %I ACM/IEEE %P 114-23 %0 Journal Article %A Matthies, Larry %D 1992 %T Stereo vision for planetary rovers: Stochasting modeling to near real-time implementation %J International Journal of Computer Vision %V 8 %N 1 %P 71-91 %0 Generic %A May, D. %A Shepherd, R. %D 1986 %T Communicating Process Computers %0 Journal Article %A McApline, G. %A McLain, W. J. %A Feldkamp, G. B. %D 1982 %T Controller smooths data flow through multiprocessor systems %J Electronic Design %V %P 45-9 %0 Conference Proceedings %A McCanny, J.V. %A Wood, K.W. %A McWhirter, J.G. %A Oliver, C.J. %D 1983 %T The Relationship between Word and Bit Level Systolic Arrays as Applied to Matrix x Matrix Multiplication %J Proceedings of SPIE Symposium, Vol. 431, Real-Time Signal Processing VI %P 114-120 %0 Journal Article %A McCanny, J. V %A McWhirter, J. G. %D 1987 %T Some Systolic Array Development in the United Kingdom %J Computer Magazine %V 20 %N 7 %P 51-63 %0 Book %A McEliece, R.J. %D 1977 %T The Theory of Information and Coding %I Addison-Wesley %C Reading, Massachusetts %V 3 %0 Conference Proceedings %A McLeod, A. %D 1993 %T Automated video surveillance-teaching an old dog new tricks %J Computer Vision for Industry %I SPIE %C Munich, Germany %P 24-25 %S Proceedings of the Spie The International Society for Optical Engineering %K automated video surveillance; technology; automated surveillance system; PC-based hybrid systems; parallel processing ; neural networks ACCESS CONTROL; COMPUTER VISION %X Digital-based automated video surveillance systems for indoor use have been around since the late 1970's. In the early 1980's they were applied to monitoring of outdoor scenes and consequently gained a poor reputation with regard to performance and reliability. In particular, the high levels of false alarms made the systems almost unusable. Problems of camera shake, perspective, changing environmental conditions and cluttered scenes with many moving objects all presented major headaches for the suppliers of these systems. These problems have been solved as the technology has matured. The automated video surveillance market is booming with new players, new systems, new hardware and software, and an extended range of applications. The paper reviews available technology, and describes the features required for a good automated surveillance system. Both hardware and software are discussed. An overview of typical applications is also given. A shift towards PC-based hybrid systems, use of parallel processing, neural networks, and exploitation of modern telecomms are introduced, highlighting the evolution modern video surveillance systems. %0 Report %A McMahon, F. H. %D 1986 %T The Livermore Fortran Kernels: A Computer Test of the Numerical Performance Range %0 Conference Proceedings %A McWhirter, J.G. %D 1983 %T Recursive Least-Squares Minimization Using a Systolic Array %J Proceedings of SPIE Symposium, Vol. 431, Real-Time Signal Processing VI %P 105-112 %0 Journal Article %A Mead, C.A. %A Pashley, R.D. %A Britton, L D. %A Daimon, Y.T. %A Sando, S.F. %D 1976 %T 128-Bit Multicomparator %J IEEE Journal of Solid-State Circuits %V SC-11 %N 5 %P 692-695 %0 Conference Proceedings %A Mead, C.A. %D 1979 %T VLSI and Technological Innovation %J Proceedings of Conference on Very Large Scale Integration: Architecture, Design, Fabrication %E Seitz, C.L. %P 15-28 %0 Journal Article %A Mead, C.A. %A Rem, M. %D 1979 %T Cost and Performance of VLSI Computing Structures %J IEEE Journal of Solid State Circuits %V SC-14 %N 2 %P 455-462 %0 Book %A Mead, C.A. %A Conway, L.A. %D 1980 %T Introduction to VLSI Systems %I Addison-Wesley %C Reading, Massachusetts %0 Conference Proceedings %A Mehenni, B. %A Wahab, M. A. %D 1993 %T APRIS: Automatic Pattern Recognition and Inspection System %J CompEuro Proceedings. Computers in Design, Manufacturing, and Production %E Croisier, A. %E Israel, M. %E Chavand, F. %I IEEE Computer Society Press %C Pris-Evry, France %P 23-8 %K high density FPGA; APRIS; Automatic Pattern Recognition and Inspection System; 2D patterns; printing industries; n-tuple method; pixel-by-pixel comparison method; massively parallel hardware implementation ; application specific integrated circuits; ASICs; field programmable gate arrays; automated assembly lines APPLICATION SPECIFIC INTEGRATED CIRCUITS; ASSEMBLING; AUTOMATIC OPTICAL INSPECTION; IMAGE PROCESSING EQUIPMENT; IMAGE RECOGNITION; LOGIC ARRAYS; PARALLEL PROCESSING; PRINTING INDUSTRY; PRODUCTION ENGINEERING COMPUTING %X A fast visual automatic pattern recognition and inspection system is described. The major aim of the system is the recognition and inspection of 2D patterns and images in the printing industries. The strategy behind the system uses a hybrid structure combining the conventional n-tuple method and the pixel-by-pixel comparison method. Both of these methods lend themselves to a massively parallel hardware implementation using application specific integrated circuits (ASICs). High-density field programmable gate arrays (FPGAs) were chosen for the implementation of the system, providing the high speeds required by the automatic recognition and inspection of modern automated assembly lines. %0 Conference Proceedings %A Memin, E. %A Heitz, F. %A Charot, F. %D 1994 %T Efficient parallel multigrid relaxation algorithms for Markov random field-based low-level vision applications %J Proceedings IEEE Computer Society Conference on Computer Vision and Pattern Recognition %I IEEE Computer Society Press %C Seattle, WA %P 644-8 %X We present a new algorithmic framework which enables making a full use of the large potential of data parallelism available on 2D processor arrays for the implementation of nonlinear multigrid relaxation methods. This framework leads to fast convergence towards quasi-optimal solutions. It is demonstrated on two different low-level vision applications. %0 Thesis %A Menzilcioglu, O. %D 1988 %T Using Powerful Processors in a Configurable Systolic Array Architecture %I Carnegie Mellon University %8 October %0 Generic %A Metropolis %A al., et %D 1953 %B J.Chem.Phys. %V 21 %P 1087 %J J.Chem.Phys. %0 Conference Proceedings %A Mettala, E. G. %D 1992 %T The OSD Tactical Unmanned Ground Vehicle Program %J Image Understanding Workshop %I Defense Advanced Research Projects Agency %C San Diego, CA %P 159-71 %0 Conference Proceedings %A MŽrigot, Alain %A Dulac, Didier %A Mohammadi, Siamak %D 1994 %T A New Scheme for Massively Parallel Image Analysis %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 352-356 %0 Conference Proceedings %A Miller, R. %A Stout, Q. F. %D 1987 %T Mesh Computer Algorithms for Line Segments and Simple Polygons %J International Conference on Parallel Processing %C University Park, PA %P 282-5 %0 Conference Proceedings %A Miller, R. %A Stout, Q. F. %D 1988 %T Convexity Algorithms for Parallel Machines %J CVPR '88: The Computer Society Conference on Computer Vision and Pattern Recognition %I IEEE Computer Society %C Ann Arbor, MI %P 918-24 %0 Conference Proceedings %A Miller, R. %A Stout, Q. F. %D 1988 %T Simulating Essential Pyramids %J CVPR '88: The Computer Society Conference on Computer Vision and Pattern Recognition %I IEEE Computer Society %C Ann Arbor, MI %P 912-7 %0 Conference Proceedings %A Miller, R. %A Prasanna-Kumar, V. K. %A Reisis, D. I. %A Stout, Q.F. %D 1988 %T Image Computations on Reconfigurable VLSI Arrays %J CVPR '88: The Computer Society Conference on Computer Vision and Pattern Recognition %I IEEE Computer Society %C Ann Arbor, MI %P 925-30 %0 Book Section %A Miller, R. %A Kumar, V. K. P. %A Reisis, D. I. %A Stout, Q. F. %D 1991 %T Efficient Parallel Algorithms for Intermdiate-Level Vision Analysis on the Recopnfigurable Mesh %B Parallel Architectures and Algorithms for Image Understanding %I Academic Press %P 185-207 %0 Journal Article %A Ming, Z. %A Ming, Y. %A Dong, Yao Qin %D 1994 %T Parallel algorithm for edge tracing by use of GAPP %J Acta Electronica Sinica %V 22 %N 4 %P 98-101 %X Based on the result of former processing steps, edge tracing is classified as a sequential operation. In this paper, a new parallel algorithm, called all direction tracing, is proposed. In this way, the sequential bottleneck appears in the previous process may be overcome. This algorithm can be realized on the GAPP systolic array processors. %0 Journal Article %A Misra, M. %A Nichols, T. %D 1994 %T Computation of 2-D wavelet transforms on the Connection Machine-2 %J Ifip Transactions A %V 44 %P 3-12 %X An important step in image processing tasks involves the identification of certain desired attributes in an image. Traditionally, this is done by transforming the image into a domain where the desired attributes or features are easily identifiable. The authors discuss the parallel implementation of one such image transform, the 2-D Gabor based Wavelet Transform. Individual components of this transform are sensitive to particular ranges of frequencies and the orientation of features in an image. The transform is formed by computing convolutions of the image with a family of wavelets. Each member of the wavelet family is a 2-D Gabor Function. The authors describe how this 2-D Wavelet Transform can be computed efficiently on a fine-grained, Single Instruction, Multiple Data Stream (SIMD) computer, the Connection Machine (CM-2). The transform of a 128*128 pixel image using 40 wavelets (sensitive to different frequency levels and orientations of features) takes 2.43 seconds on the CM-2 as compared to 240 seconds on a Sun 4/200 and 55 seconds on a SPARCsystem 10. The gains achieved by these speed-ups are even more dramatic when hundreds of images have to be transformed (as in the Face Recognition problem). %0 Conference Proceedings %A Mitkas, P. A. %A Beyette, F. R., Jr. %A Feld, S. A. %A Irakliotis, L. J. %A Wilmsen, C. W. %D 1994 %T Optoelectronic parallel processing with straight-pass optical interconnections and smart pixel arrays %J Proceedings of the First International Workshop on Massively Parallel Processing Using Optical Interconnections %I Ieee Comput. Soc. Press %C Los Alamitos, Ca, Usa %P 170-81 %K optoelectronic parallel processing ; straight-pass optical interconnections; smart pixel arrays; parallel computer architectures ; 2D processing element arrays; lenslet array; numerical computations; data comparison; sorting; associative processing; database operations; relational database environment; image processing operations ; vertical-cavity surface emitting lasers; emitters; heterostructure phototransistors; detectors IMAGE PROCESSING ; INTEGRATED OPTOELECTRONICS; OPTICAL INFORMATION PROCESSING; OPTICAL INTERCONNECTIONS; PARALLEL ARCHITECTURES; RELATIONAL DATABASES; SORTING %X Several fine and medium grain parallel computer architectures comprise multiple stages of 2D processing element arrays. The parallel massive interconnections between two such stages can be implemented in optics. Straight-pass interconnections, as one possible interconnection scheme, can be easily realized with a lens or a lenslet array and their simplicity and regularity permits easy scale-up. We have identified four application classes with operations that can be performed in parallel by straight pass interconnections between smart pixel arrays. These classes include numerical computations such as data comparison and sorting, associative processing, database operations in a relational database environment, and image processing operations. We propose several implementations which use vertical-cavity surface emitting lasers as emitters and heterostructure phototransistors as detectors. %0 Conference Proceedings %A Modayur, Bharath R. %A Shapiro, Linda G. %D 1994 %T Fast Parallel Object Recognition %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 284-289 %0 Journal Article %A Moldovan, D. I. %D 1982 %T On the Analysis and Synthesis of VLSI Algorithms %J IEEE Transactions on Computers %V C-31 %N 11 %P 1121-1126 %0 Journal Article %A Moldovan, D .I. %A Fortes, J. A. B. %D 1986 %T Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays %J IEEE Transactions on Computers %V C-35 %N 1 %P 1-12 %0 Journal Article %A Montret, L. %A Ekerol, H. %A Hodgson, D. C. %D 1994 %T Object tracking at field rate using the Hough transform %J Mechatronics %V 4 %N 3 %P 331-7 %K object tracking; field rate; Hough transform; packaging machinery; wrapped confectionery; motion control system; optical tracking system; CCD camera; motion tracking; open loop orientation control; 60 Hz CCD IMAGE SENSORS; COMPUTER VISION ; FOOD PROCESSING INDUSTRY; HOUGH TRANSFORMS; PACKAGING; POSITION CONTROL; TRANSPUTERS %X One of the novel elements in a new form of packaging machinery under development is the ability to control the motion of wrapped confectionery products, e.g. chocolate bars, on a flat horizontal surface by the means of air jets. The motion control system needs an instantaneous knowledge of the position and orientation of the bar which has been achieved by means of an optical tracking system based on a CCD camera. Because of its power and modularity, the transputer has been chosen as the computing control element within the system. The task of extracting position and orientation data can be achieved with many algorithms. The authors have chosen to evaluate the Hough transform for this task because of its immunity to noise and its potential for expression in parallel form on an array of transputers. Position and orientation sampling at field rate (60 Hz) has been achieved and some preliminary results of motion tracking and open loop orientation control are shown. %0 Book %A Monzingo, R.A. %A Miller, T.W. %D 1980 %T Introduction to Adaptive Arrays %I John Wiley & Sons, Inc. %C New York %0 Conference Proceedings %A Moore, G.E. %D 1979 %T Are we really ready for VLSI? %J Proceedings of Conference on Very Large Scale Integration: Architecture, Design, Fabrication %E Seitz, C.L. %P 3-14 %0 Conference Proceedings %A Moore, W.R. %D 1986 %T Review of Fault-Tolerant Techniques for the Enhancement of Integrated Circuit Yield %J Special Issue on Fault Tolerance in VLSI %I IEEE %0 Conference Proceedings %A Moore, W. %A Cook, M. %A Anderson, L. %D 1994 %T Control applications of parallel processing in the food industry %J Parallel Computing and Transputers. Pcat %E Arnold, D. %E Christie, R. %E Day, J. %E Roe, P. %I IOS Press %C Brisbane, Qld., Australia %P 292, 294-300 %X This paper addresses the application of a multiprocessor system to the manipulation of food in a continuous processing environment. The use of imaging on a transputer system is described in the orientation of the product (fish pieces) on a processing line. A prototype food processing system is being constructed that will allow full automation of fish processing line at the Edgell-Birdseye plant at Bathurst and this will include this imaging system if satisfactory performance is demonstrated. The paper discusses the use of a neural net approach to control product alignment on a production line. %0 Report %A Moravec, H. %D 1980 %T Obstacle Avoidance and Navigation in the Real World by a Seeing Robot Rover %I Carnegie-Mellon University Robotics Institute %R CMU-RI-TR-3 %0 Book Section %A Morrow, P. J. %A Perrott, R. H. %D 1988 %T The Design and Implementation of Low-Level Image Processing Algorithms on a Transputer Network %B Parallel Architectures and Computer Vision %E Page, I. %I Oxford Science %P 243-59 %0 Conference Proceedings %A Morrow, P. J. %A Crookes, D. %D 1993 %T A portable abstract machine model for image processing : an implementation technique for software tools %J Proceedings. Euromicro Workshop on Parallel and Distributed Processing %I Ieee Comput. Soc. Press %C Gran Canaria, Spain %P 466-73 %K portable abstract machine model; low-level image processing ; portable implementation technique; software tools; software development; parallel image processing ; high-level programming language; workbench environment %X This paper discusses the design of an abstract machine model for low-level image processing . Two software development tools for parallel image processing , namely a high-level programming language and a workbench environment, are described briefly. We then present the abstract machine model as a portable implementation technique for the language and environment. %0 Journal Article %A Mukherjee, J. %A Das, P.P. %A Chatterji, B.N. %D 1992 %T Segmentation of Range Images %J Pattern Recognition %V 25 %N 10 %P 1141-1156 %0 Report %A Mukhopadhyay, A. %A Ichikawa, T. %D 1972 %T An n-Step Parallel Sorting Machine %0 Journal Article %A Mukhopadhyay, A. %D 1979 %T Hardware Algorithms for Nonnumeric Computation %J IEEE Transactions on Computers %V C-28 %N 6 %P 384-394 %0 Conference Proceedings %A Murakami, K. %A Mori, S. %A Fukuda, A. %A Sueyoshi, T. %A Tomita, S. %D 1989 %T The Kyushu University Reconfigurable Parallel Processor-Design Philosophy and Architecture %J Information Processing 89. Proceedings of the IFIP 11th World Computer Congress %C San Francisco, CA %P 995-1000 %0 Conference Proceedings %A Mzaik, T. %A Jagadeesh, J. %D 1993 %T Simulation of pyramid architecture on the connection machine and implementation of algorithms %J National Aerospace and Electronics Conference. NAECON 1993 %I IEEE %C Dayton, OH %P 838-44 %K pyramid architecture; connection machine; parallel architectures ; image processing ; computer vision ; SIMD; multiresolution algorithm; top-down/bottom up algorithms; pyramid simulation environment; mapping; pyramid algorithms; Gaussian pyramid; Laplacian pyramid; subband pyramid; pyramid search; segmentation COMPUTER VISION ; IMAGE SEGMENTATION; NEURAL NETS; PARALLEL ALGORITHMS; PARALLEL ARCHITECTURES; PROGRAMMING ENVIRONMENTS; VIRTUAL MACHINES %X Many parallel architectures have been proposed to meet the high computational requirement of image processing and computer vision . SIMD pyramid architectures have been proposed to efficiently implement several classes of vision tasks such as multiresolution and top-down/bottom up algorithms. In this paper, a pyramid simulation environment implemented on the Connection Machine (CM) is presented. Discussion of the mapping scheme and the basic features of the simulator along with implementation of several pyramid algorithms using the simulator is presented. %0 Conference Proceedings %A Mzaik, T. %A Chandra, S. %A Panda, D. K. %A Jagadeesh, J. M. %D 1993 %T Analysis of routing in pyramid architectures %J Proceedings of the IEEE 1993 National Aerospace and Electronics Conference. NAECON 1993 %I IEEE %C Dayton, OH %P 831-7 %K pyramid architectures; massively parallel systems ; image processing applications ; mesh connected nodes; node-to-node routing; routing algorithms; neighbor-tree algorithm; neighbor-descedent-tree algorithm; maximum message latency; average message latency; flow control; packet switching; circuit switching; wormhole routing; discrete event simulation library; communication patterns; simulation DISCRETE EVENT SIMULATION; IMAGE PROCESSING ; MESSAGE PASSING; NETWORK ROUTING; PACKET SWITCHING; PARALLEL ARCHITECTURES; PERFORMANCE EVALUATION %X Pyramid machines are massively parallel systems motivated by image processing applications. The architecture consists of several layers of mesh connected nodes of decreasing dimensions. In this paper, we investigate general node-to-node routing in pyramids. We propose two routing algorithms neighbor-tree (NT) and neighbor-descedent-tree (NDT). For each routing algorithm, we find the average and maximum message latency for each of the three flow control schemes: packet switching, circuit switching, and wormhole routing. The performance of the proposed algorithms is evaluated using a discrete event simulation library (SMPL) and is compared with pyramid mesh and tree routing. %0 Conference Proceedings %A Nakahira, H. %A Sakiyama, S. %A Maruyama, M. %A Hasegawa, K. %A Kouda, T. %A Maruno, S. %A Shimeki, Y. %A Satonaka, T. %A Nagano, Y. %D 1993 %T A digital neuroprocessor using quantizer neurons %J Symposium on VLSI Circuits. Digest of Technical Papers %C Kyoto, Japan %P 35-6 %X We discuss a digital neuroprocessor using quantizer neurons designed for character or image recognition and learning. The number of synapses in a neural network is a very important factor for the accurate recognition of images. A neural network with a large amount of synapses can achieve high recognition accuracy, however, it makes the processing speed lower because of the large number of network calculations. To realize both a large amount of synapses and high speed processing, a neuroprocessor has been fabricated with the Multi-Functional Layered Network (MFLN) model. The neuroprocessor contains 27,000 gates on a chip fabricated by using 1.2 mu m double metal CMOS, sea of gates technology. Chip size is 10.99 mm x 10.93 mm. The neuroprocessor operates with a clock cycle time of 25 nsec. It simulates the MFLN model with 4,736 neurons and two million synaptic weights in 2.8 msec when the width of the combination function is three. Therefore, the performance is 0.76 GCPS (Giga Connections Per Second). It achieves 20.5 GCPS, when the width of the combination function is one. It can execute Hebbian learning with 20.0 MCUPS (Mega Connections Updated Per Second). %0 Conference Proceedings %A Nakiyame, T. %A Kusano, T. %A Matsumoto, K. %A Hurokawa, H. %A Toshiaki, H. %A Ueno, H. %A Temma, T. %D 1984 %T A VLSI Image Pipeline Processor %J International Solid-State Circuits Conference %I IEEE %P 208-9, 339 %0 Conference Proceedings %A Narayan, S.S. %A Nash, J.G. %A Nudd, G.R. %D 1983 %T VLSI Processor Array for Adaptive Radar Applications %J Proceedings of SPIE Symposium, Vol. 431, Real-Time Signal Processing VI %P 127-135 %0 Journal Article %A Narayanan, P. J. %A Chen, L. T. %A Davis, L. S. %D 1992 %T Effective Use of SIMD Parallelism in Low- and Intermediate-Level Vision %J Computer %V 25 %N 2 %P 68-73 %0 Journal Article %A Narayanan, P.J. %A Davis, L.S. %D 1992 %T Replicated Data Algorithms in Image Processing %J Cvgip - Image Understanding %V 56 %N 3 %P 351-365 %0 Conference Proceedings %A Nash, J.G. %A Hansen, S. %A Nudd, G.R. %D 1981 %T VLSI Processor Arrays for Matrix Manipulation %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 367-378 %0 Conference Proceedings %A Nash, J. G. %A Petrozolin, C. %D 1985 %T VLSI Implementation of a Linear Systolic Array %J Proc. ICASSP '85 %C Tampa, Florida. %P 1392-1395 %0 Conference Proceedings %A Nash, J.G. %D 1986 %T Review of Arithmetic Algorithms and Circuits for High Speed Digital Signal Processing %J Proceedings of SPIE's O-E/LASE '86 Optoelectronics and Laser Applications in Science and Engineering %0 Journal Article %A Nash, J. G. %A Przytula, K. W. %A Hansen, S. %D 1987 %T The Systolic/Cellular System for Signal Processing %J Computer Magazine %V 20 %N 7 %P 96-97 %0 Book %A National Physical Laboratory, England %D 1961 %T Modern Computing Methods %I Her Majesty's Stationery Office %C London %0 Generic %A NCUBE Corporation %T NCUBE/10, an overview %I NCUBE, Beaverton, OR. %9 Product brochure %0 Conference Proceedings %A Neumann, Ulrich %D 1993 %T Parallel Volume-Rendering Algorithm Performance on Mesh-Connected Multicomputers %J Parallel Rendering Symposium %C San Jose, CA %P 97-104 %0 Conference Proceedings %A Nevatia, R. %A Price, K. %A Medioni, G. %D 1992 %T USC Image Understanding Research: 1990-1991 %J Image Understanding Workshop %I Defense Advanced Research Projects Agency %C San Diego, CA %P 3-25 %0 Conference Proceedings %A Nevatia, R. %D 1994 %T Heterogeneous computing for vision %J Proceedings Heterogeneous Computing Workshop %I IEEE Computer Society Press %C Cancun, Mexico %P 37-42 %K heterogeneous computing; computer vision tasks ; processing levels; photointerpretation; special purpose parallel computers ; commercially available parallel computers COMPUTER VISION ; PARALLEL PROCESSING; SPECIAL PURPOSE COMPUTERS %X Identifies the computational requirements of tasks in vision. Vision tasks usually require three levels of processing-low, intermediate and high-each having distinctly different characteristics thus pointing to the need for heterogeneous computing. An example from the domain of photo-interpretation is used to illustrate some of the specifics of the processing levels. Finally, we discuss the pros and cons of using special-purpose and commercially available parallel computers for vision tasks. %0 Conference Proceedings %A Nevatia, Ramkant %A Reinhart, C. C. %D 1994 %T Parallel Processing for Spatial Grouping and Matching %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 290-294 %0 Book %A Newman, W.M. %A Sproull, R.F. %D 1979 %T Principles of Interactive Computer Graphics %I McGraw-Hill %C New York %0 Conference Proceedings %A Nishitani, T. %A Kawakami, Y. %A Maruta, R. %A Sawai, A. %D 1980 %T LSI Signal Processing Development for Communications Equipment %J Proceedings of ICASSP 80 %P 386-389 %0 Edited Book %A Noguchi, S. %A Yamomoto, M. %D 1993 %T Transputer/Occam Japan 5. Proceedings of the 5th Transputer/Occam International Conference %B Amsterdam, Netherlands: Ios Press %X The following topics were dealt with: parallel control systems; parallel image processing; parallel algorithms; parallel frameworks; and networking. %0 Journal Article %A Nomura, J. %A Nishiyama, T. %A Nakajima, R. %D 1994 %T A telepresence robot for surveillance use and development of its autonomous movement %J Displays %V 15 %N 1 %P 7-15 %K telepresence robot; surveillance; autonomous movement; fire-detection; pinpoint data collection; hazardous remote environment; operator-machine interface; mobile security robot; fuzzy control; autonomous obstacle avoidance; stereoscopic camera; parallel processing COMPUTER VISION ; FIRES; FUZZY CONTROL; MAN-MACHINE SYSTEMS; MOBILE ROBOTS; PARALLEL PROCESSING; SAFETY SYSTEMS; SECURITY; TELECONTROL %X A mobile telepresence robot is currently being developed for use in surveillance and fire-detection applications. The system permits precision observation and pinpoint data collection without subjecting the user to a possibly hazardous remote environment. Since control of such a robot is a complicated task, a telepresence operator-machine interface is designed to allow users to feel the robot as an extension of themselves. In this paper, an overview of the current system is shown, where the manual control system by the user using the joystick is explained. The control system, however, forces the user to control the robot all the time. In order to decrease the workload of the user, an autonomous movement of the robot based on fuzzy control is integrated with the current system. %0 Conference Proceedings %A Nouri, T. %A Pflug, L. %D 1993 %T Real time 3D scanner, investigations and results %J Display Systems %I SPIE %C Munich, Germany %P 4-10 %S Proceedings of the SPIE - The International Society for Optical Engineering %K touch loss techniques; parallel interference optical fringes ; 3D reconstruction; real time 3D scanner; 3D surface data; computer-visualization; 3D data extraction; cosmetic surgery; CAD; animation; research; parallel interference fringes ; visible laser COMPUTER VISION ; DATA VISUALISATION; IMAGE RECONSTRUCTION; IMAGE SCANNERS %X This article presents a concept of reconstruction of three-dimensional (3D) objects using non-invasive and touch loss techniques. The principle of this method is to display parallel interference optical fringes on an object and then to record the object under two angles of view. According to an appropriated treatment one reconstructs the 3D object even when the object has no symmetrical plan. The 3D surface data is available immediately in digital form for computer-visualization and for analysis software tools. The optical set-up for recording the 3D object, the 3D data extraction and treatment as well as the reconstruction of the 3D object are reported and commented on. This application is dedicated for reconstructive/cosmetic surgery, CAD, animation and research purposes. %0 Conference Proceedings %A Noyce, R.N. %D 1979 %T Hardware Prospects and Limitations %J The Computer Age: A Twenty-Year View %E Dertouzos, M.L. and Moses, J. %I IEEE %P 321-337 %0 Conference Proceedings %A Nudd, G. R. %A Atherton, T. J. %A Francis, N. D. %A Howarth, R. M. %A Kerbyson, D. J. %A Packwood, R. A. %A Vaudin, G. J. %D 1990 %T A Hierarchical Multiple-SIMD Architecture for Image Analysis %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 642-7 %0 Journal Article %A Nurre, J. H. %A Hall, E. L. %D 1991 %T Positioning Quadric Surfaces in an Active Stereo Imaging System %J Ieee transactions on pattern analysis and machine intelligence %V 13 %N 5 %P 491- %0 Journal Article %A Nurre, Joseph H. %A Hall, Ernest L. %D 1992 %T Encoded Grid Generation from a Computer Solid Model %J Computer Vision Graphics and Image Processing. Image understanding %V 56 %N 2 %P 131- %0 Generic %A Nuttall, T. C. %D 1957 %T Apparatus for Counting Objects %I U.S. %N 2803406 %8 August 20, 1957 %0 Conference Proceedings %A O'Hallaron, D. R. %D 1991 %T The ASSIGN Parallel Program Generator %J 6th Distributed Memory Computing Conference %C Portland, OR %0 Report %A O'Hallaron, D %D 1991 %T Introduction to Assign %I Carnegie Mellon University, School of Computer Science %0 Conference Proceedings %A Obrebska, M. %D 1981 %T Comparative Survey of Different Design Methodologies for Control Parts of Microprocessors %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 347-356 %0 Generic %A Oflazer, K. %T A Reconfigurable VLSI Architecture for a Database Processor %0 Report %A Oflazer, K. %D 1982 %T Design and Implementation of a Single-chip Median Filter %0 Journal Article %A Ofman, Y. %D 1962 %T On the Algorithmic Complexity of Discrete Functions %J Dokl. Akad. Nauk SSSR %V 145 %P 48-51 %0 Conference Proceedings %A Ohhashi, M. %A Schneider, R.E. %D 1985 %T High-speed Computation of Unary Functions %J Proc. 7th Symposium on Computer Arithmetic %P 82-85 %0 Journal Article %A Okada, Y. %A Sakai, T. %D 1993 %T Locally parallel image-processing in large-scale systolic array processor %J Transactions of the Institute of Electrical Engineers of Japan, Part C %V 113 %N 11 %P 933-8 %K large-scale systolic array processor; locally parallel image-processing ; VLSI technology; transformation characteristics; pre-processing; geometric arithmetic parallel processor chips ; GAPP; LSAPS DIGITAL SIGNAL PROCESSING CHIPS; IMAGE PROCESSING ; SYSTOLIC ARRAYS; VLSI %X In recent years there have been remarkable developments in VLSI technology. A proposal has made for the realization of VLSI algorithm performance in image processing fields. The systolic array is an example for VLSI architecture. A systolic array has a control system of parallel processing abilities. Pre-processing and transformation characteristics are very useful for industrial applications. In this paper we present a discussion on the method of realization of parallel image processing using a systolic array processor GAPP (geometric arithmetic parallel processor chips and LSAPS (large scale systolic array processor system). We discuss in detail the pre-processing and transformation characteristics of images, in which high speed processing capability is essential to deal with large volume data. %0 Conference Proceedings %A Okutomi, M. %A Kanade, T. %D 1991 %T A Multiple Baseline Stereo %J IEEE Computer Society Conference on Computer Vision and Pattern Recognition %I IEEE Computer Society %C Lahaina, Maui, Hawaii %P 63-69 %0 Journal Article %A Okutomi, M. %A Kanade, T. %D 1993 %T A Multiple-Baseline Stereo %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 15 %N 4 %P 353-63 %0 Journal Article %A Okutomi, M. %A Kanade, T. %D 1993 %T A Multiple-Baseline Stereo %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 15 %N 4 %P 353-63 %0 Report %A Olson, T. J. %D 1985 %T An Image Processing Package for the BBN Butterfly Parallel Processor %I University of Rochester, Department of Computer Science %R 9 %0 Conference Proceedings %A Orrey, D. %A Harbridge, J. %A Ivey, P. %A Midwinter, T. %A Huch, M. %A Saucier, G. %A Glesner, M %D 1988 %T The Design of a Large SIMD Array in Wafer Scale Technology %J Eighth International Custom Microelectronics Conference %C London, UK %P 11/1-6 %0 Conference Proceedings %A Ososanya, E. T. %A Jung, Chi Chen %A Reyes, Poo %D 1994 %T Performance evaluation of parallel fast Walsh transform algorithms on a shared-memory multiprocessor computer %J Proceedings of the 26th Southeastern Symposium on System Theory %I IEEE Computer Society Press %C Athens, OH %P 562-6 %K performance evaluation; parallel fast Walsh transform algorithms ; shared-memory multiprocessor computer; digital signal processing; high definition television; HDTV; X-ray image processing ; ultrasonic image processing ; heart; medicine; target tracking; object identification; military application; computer applications; Alliant FX/2800 Supercomputer; computational time; Alliant architecture; parallel computation %X The Walsh transforms have been used in various digital signal processing applications, such as high definition television (HDTV), processing ultrasonic or X-ray images of the heart in medicine, target tracking and object identification in military applications, and many more image processing applications. As the area of computer applications has broadened, the quantity of data to be transformed has greatly increased. One way of achieving fast transform is to parallelize the transform algorithms used in these applications. The author present the parallelization of three fast Walsh transform algorithms on the Alliant FX/2800 Supercomputer. They examine different parallelization techniques to optimize the computational time, and show how the Alliant architecture may be efficiently used for parallel computation. %0 Journal Article %A Ottmann, T.A. %A Rosenberg, A.L. %A Stockmeyer, L.J. %D 1982 %T A Dictionary Machine (for VLSI) %J IEEE Transactions on Computers %V C-31 %N 9 %P 892-897 %0 Journal Article %A Ousterhout, J. %D 1981 %T Caesar: An Interactive Editor for VLSI Circuits %J VLSI Design %V %N Fourth Quarter %P 34-38 %0 Conference Proceedings %A Ousterhout, J. K. %D 1983 %T Crystal: A Timing Analyzer for nMOS VLSI Circuits %J Proceedings of the Third Caltech Conference on Very Large Scale Integration %E Bryant, R. %I Computer Science Press, Inc. %P 57-70 %0 Journal Article %A Pagano, F. %A Parodi, G. %A Zunino, R. %D 1993 %T Parallel Implementation of Associative Memories for Image Classification. %J Parallel Computing %V 19 %N 6 %P 667-684 %X Associative techniques are useful in computer vision because they are notably able to robustify a recognition system. The noise-like coding model of associative memory has been already applied successfully to image-classification. This paper describes the implementation of the associative system on transputer-based architectures. After explaining the model's basic formalism, the paper marks out the key-generation mechanism, the data-mapping strategy, and the hierarchical processor organization. The basic result of this research is a general methodology for efficient HW configuration of real-time assocaitve visual systems. The system's efficiency can be predicted by theoretical derivations, in which both the FFt-computation speed and the data-transmission speed play a crucial role. Experimental results including different HW configuration and different image-sizes always confirmed theoretical expectations. %0 Book Section %A Page, I. %D 1988 %T The Disputer: A Dual Paradigm Parallel Processor for Graphics and Vision %B Parallel Architectures and Computer Vision %E Page, I. %I Oxford Science %P 201-16 %0 Journal Article %A Pan, He-Ping %D 1994 %T Two-level global optimization for image segmentation %J Isprs Journal of Photogrammetry and Remote Sensing %V 49 %N 2 %P 21-32 %X Domain-independent image segmentation is considered as the global optimization problem of seeking the simplest descriptions of a given input image in terms of coherent closed regions. The approach consists of two levels of processing: pixel-level and region-level, both based on the Minimum-Description-Length principle. Pixel-level processing leads to forming the atomic regions that are then labelled. In region-level processing neighbouring regions are merged into larger regions using an explicit attributed graph evolution mechanism. Both level processings are stopped automatically without using any heuristic control parameters. Experiments are carried out with a number of images of different scene types. Parallel implementation of region-level processing is the most difficult problem to be solved for the operational application of this approach. %0 Generic %A ParaSoft Corporation %T Programming Parallel Computers Using the EXPRESS System %9 Product description literature %0 Journal Article %A Parker, A.C. %A Wallace, J.J. %D 1981 %T An I/O Hardware Descriptive Language %J IEEE Transactions on Computers %V C-30 %N 6 %P 423 - 438 %0 Conference Proceedings %A Parkinson, D. %A Hunt, D. J. and MacQueen, K. S. %D 1988 %T The AMT DAP 500 %J Thirty-third IEEE Computer Society International Conference - Compcon Spring 88 %I IEEE Computer Society %C San Francisco, CA %P 196-9 %0 Book %A Parkinson, D. and Litt, J. %D 1990 %T Massively Parallel Computing with the DAP %I MIT Press %0 Book Section %A Parkinson, D. %D 1991 %T Experiments in Component Labelling in a Parallel Computer %B Parallel Architectures and Algorithms for Image Understanding %E Page, I. %I Academic Press %P 209-25 %0 Conference Proceedings %A Parulekar, Rahul %A Davis, Larry %A Chellappa, Rama %A Saltz, Joel %A Sussman, Alan %A Townshend, John %D 1994 %T High Performance Computing for Land Cover Dynamics %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 234-238 %0 Conference Proceedings %A Patel, Jamshed N. %A Jamieson, Leah H. %D 1993 %T Evaluating Scalability of the 2-D FFT on Parallel Computers %J Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society Press %C New Orleans, LA %P 109-115 %0 Conference Proceedings %A Paterson, M.S. %A Ruzzo, W.L. %A L., Snyder. %D 1981 %T Bounds on Minimax Edge Length for Complete Binary Trees %J Proceedings of the Thirteenth Annual ACM Symposium on Theory of Computing %P 293-299 %0 Journal Article %A Patterson, D.A. %D 1985 %T Reduced Instruction Set Computers %J Communications of the ACM %V 28 %N 1 %P 8-21 %0 Book %A Paul, R. %D 1981 %T Robot Manipulators: Mathematics, Programming, and Control %I The MIT Press %C Cambridge, Massachusetts %0 Journal Article %A Paul, R.P. %A Shimano, B. %A Mayer, G. %D 1981 %T Kinematic Control Equations for Simple Manipulators %J IEEE Transactions on Systems, Men and Cybernetics %V SMC-11 %P 449-455 %0 Journal Article %A Pease, M.C. %D 1968 %T An Adaptation of the Fast Fourier Transform for Parallel Processing %J Journal of the ACM %V 15 %P 252-264 %0 Journal Article %A Peleg, S. %A Rosenfeld, A. %D 1978 %T Determining Compatibility Coefficients for Curve Enhancement Relaxation Processes %J IEEE Transactions on systems, Man, and Cybernetics %V SMC-8 %N 7 %P 548:556 %0 Conference Proceedings %A Pervin, Edward %A Webb, Jon A. %D 1983 %T Quaternions for Computer Vision and Robotics %J Computer Vision and Pattern Recognition %I IEEE Computer Society %C Washington, D. C. %P 382-383 %0 Conference Proceedings %A Pervin, Edward %A Webb, Jon A. %D 1984 %T The Shape of Subjective Contours %J National Conference on Artificial Intelligence %C Austin, TX %P 340-343 %0 Book %A Peterson, W.W. %A Weldon, E.J. %A Jr. %D 1972 %T Error-Correcting Codes %I MIT Press %C Cambridge, Massachusetts %0 Conference Proceedings %A Peterson, J.G. %D 1981 %T Keys to Successful VLSI System Design %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 21-28 %0 Conference Proceedings %A Peterson, J. %A Chow, E. %A Madan, H. %D 1988 %T A High-Speed Message-Driven Communication Architecture %J Conference Proceedings of 1988 International Conference on Supercomputing %I ACM %C St. Malo, France %P 355-366 %0 Conference Proceedings %A Pfister, G. F. %A Norton, V.A. %D 1985 %T Hot Spot Contention and Combining in Multistage Interconnection Networks %J Proceedings of 1985 International Conference on Parallel Processing %P 790-795 %0 Conference Proceedings %A Pietikanen, M. %A Seppaenen, T. %A Alapuranen, P. %D 1990 %T A Hybrid Computer Architecture for Machine Vision %J 10th International Conference on Pattern Recognition %P 426-31 %0 Conference Proceedings %A Pinter, R.Y. %D 1981 %T Optimal Routing in Rectilinear Channels %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 160-177 %0 Conference Proceedings %A Pippenger, N. %D 1980 %T Pebbling %J Proceedings of the Fifth IBM Symposium on Mathematical Foundations of Computer Science %0 Edited Book %A Pitas, I. %D 1993 %T Parallel Processing Algorithms for Digital Image Processing %I Wiley %C New York %0 Conference Proceedings %A Podroobny, O. V. %D 1993 %T Fault-tolerant array processor for parallel image processing %J Proceedings of the Spie The International Society for Optical Engineering %P 5-6 %X The processor described has a regular array of simple programmable elements and distributed hardware subsystem for self-testing, self-diagnostics and self-reconfiguration. Each element has an operational unit (1-bit ALU), input and output commutators and control unit. Either of 2 spare can replace any elements in a cluster of 4 main ones at fault. This report covers the overall structure of the VLSI, self-testing and self-reconfiguration subsystem design and working. %0 Journal Article %A Poggio, T. %A Gamble, E. B. %A Little, J. J. %D 1988 %T Parallel Integration of Vision Modules %J Science %V 242 %N 4877 %P 436-40 %0 Conference Proceedings %A Pomerleau, D. A. %A Gusciora, G. L. %A Touretzky, D. S. %A Kung, H. T. %D 1988 %T Neural Network Simulation at Warp Speed: How We Got 17 Million Connections Per Second %J Proceedings of 1988 IEEE International Conference on Neural Networks %P 143-150 %0 Book Section %A Pomerleau, D. A. %D 1989 %T ALVINN: An Autonomous Land Vehicle In a Neural Network %B Advances in Neural Information Processing Systems %E Touretzky, D. E. %I Kaufmann %0 Book Section %A Pomerleau, D. A. %D 1990 %T Neural network based autonomous navigation %B Vision and Navigation: The CMU Navlab %E Thorpe, C. E. %I Kluwer Academic Publishers %0 Conference Proceedings %A Pomerleau, D. A. %D 1991 %T Neural Network-Based Vision Processing for Autonomous Robot Guidance %J Applications of Neural Networks II %C Orlando, FL %P 121-8 %0 Journal Article %A Pomerleau, Dean A. %D 1991 %T Efficient Training of Artificial Neural Networks for Autonomous Navigation %J Neural Computation %V 3 %N 1 %P 88-97 %0 Book %A Pomerleau, Dean %D 1993 %T Neural network perception for mobile robot guidance %I Kluwer Academic Publishing %0 Journal Article %A Potier, D. %A Angeniol, B. %D 1989 %T Neural Net Activities at Thomson-CSF %J Bulletin de Liaison de la Recherche en Informatique et en Automatique %V %N 124 %P 9-10 %0 Edited Book %A Potter, Jerry L. %D 1985 %T The Massively Parallel Processor %I MIT Press %C Cambridge, MA %P 304 %0 Book %A Pountain, D. %A May, D. %D 1987 %T A Tutorial Introduction to occam Programming %I BSP Professional Books %0 Conference Proceedings %A Powell, N.R. %D 1981 %T Functional Parallelism in VLSI Systems and Computations %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 41-49 %0 Report %A Pozo, R. %A MacDonald, A. E. %D 1989 %T Performance Characteristics of Scientific Computation on the Connection Machine %I University of Colorado at Boulder, Department of Computer Science %R CU-CS-440-89 %0 Report %A Pozo, R. and MacDonald, A. E. %D 1989 %T Performance Characteristics of Scientific Computation on the Connection Machine %R CU-CS-440-89 %0 Conference Proceedings %A Prasanna, Viktor K. %A Wang, Cho-Li %A Khokar, Ashfaq A. %D 1993 %T Low Level Vision Processing on Connection Machine CM-5 %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 117-126 %0 Conference Proceedings %A Prasanna, V. K. %A Wang, Cho-Li %D 1994 %T Scalable data parallel object recognition using geometric hashing on CM-5 %J Proceedings of the Scalable High Performance Computing Conference %I IEEE Computer Society Press %C Knoxville, TN %P 817-24 %K Connection Machine CM-5; scalable data-parallel algorithms ; object recognition; geometric hashing; abstract computer model; load balancing technique; processor-time optimal algorithms; model probe; processor nodes; feature points; voting; hash bin length; scene points; model database; machine size COMPUTATIONAL COMPLEXITY; COMPUTATIONAL GEOMETRY; COMPUTER VISION ; FEATURE EXTRACTION; FILE ORGANISATION; IMAGE RECOGNITION; PARALLEL ALGORITHMS; PARALLEL MACHINES; RESOURCE ALLOCATION %X Presents scalable parallel algorithms for object recognition using geometric hashing. We define an abstract model of the CM-5 computer. We develop a load balancing technique that results in scalable processor-time optimal algorithms for performing a probe on the CM-5 model. Given a model of a CM-5 with P processor nodes and a set S of feature points in a scene, a probe of the recognition phase can be performed in O( mod V(S) mod )/P) time, where V(S) is the set of votes cast by feature points in S. This algorithm is scalable in the range 1