|
Papers by Year (Most Recent on the top)
2008 |
(under review) Distributed Localization of Modular Robot Ensembles | bib | |
Stanislav Funiak, Padmanabhan Pillai, Michael P. Ashley-Rollman, Jason D. Campbell, and Seth Copen Goldstein.
International Journal of Robotics Research,
2008.
|
| @article{funiak-ijrr08,
author = {Funiak, Stanislav and Pillai, Padmanabhan and
Ashley-Rollman, Michael P. and Campbell, Jason D. and Goldstein,
Seth Copen},
title = {Distributed Localization of Modular Robot Ensembles},
journal = {International Journal of Robotics Research},
year = {2008}
}
|
|
Heterogeneous Latch-Based Asynchronous Pipelines | pdf bib abstract | |
Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein.
Asynchronous Circuits and Systems, International Symposium on,
pages 83–92, 2008.
|
| hide Abstract | We present a technique to automatically synthesize heterogeneous asynchronous pipelines by combining two different latching styles: normally open D-latches for high performance and self-resetting D-latches for low power. Theformer is fast but results in high power consumption due to data glitches that leak through the latch when it is open. The latter is normally closed and is opened just before data stabilizes. Thus, it is more power-efficient but slower than normally open D-latches. We propose a module selection optimization that assigns each pipeline stage to one of these two latching styles. This is performed by an automated algorithm that uses two types of heuristics: (1) it uses the Global Critical Path (GCP), to assign D-latches to stages that are sequentially critical, and (2) it estimates potential datapath glitching to make SR-latch assignment decisions. The algorithm has quadratic-time complexity and experiments that apply the algorithm on several media processing kernels indicate that, on average, the heterogeneous pipelining algorithm achieves higher performance and is more energy efficient than either the homogeneous D-latch or SR-latch pipeline styles. |
| | @inproceedings{venkataramani-async08,
author = {Venkataramani, Girish and Chelcea, Tiberiu and Goldstein,
Seth Copen},
title = {Heterogeneous Latch-Based Asynchronous Pipelines},
journal = {Asynchronous Circuits and Systems, International
Symposium on},
year = {2008},
issn = {1522-8681},
pages = {83--92},
keywords = {Asychronous Circuits},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2008.21},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
abstract = {We present a technique to automatically synthesize
heterogeneous asynchronous pipelines by combining two different
latching styles: normally open D-latches for high performance and
self-resetting D-latches for low power. Theformer is fast but
results in high power consumption due to data glitches that leak
through the latch when it is open. The latter is normally closed
and is opened just before data stabilizes. Thus, it is more
power-efficient but slower than normally open D-latches. We
propose a module selection optimization that assigns each
pipeline stage to one of these two latching styles. This is
performed by an automated algorithm that uses two types of
heuristics: (1) it uses the Global Critical Path (GCP), to assign
D-latches to stages that are sequentially critical, and (2) it
estimates potential datapath glitching to make SR-latch
assignment decisions. The algorithm has quadratic-time complexity
and experiments that apply the algorithm on several media
processing kernels indicate that, on average, the heterogeneous
pipelining algorithm achieves higher performance and is more
energy efficient than either the homogeneous D-latch or SR-latch
pipeline styles.},
url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-async08.pdf}
}
|
|
Near-Optimal Instruction Selection on DAGs | pdf bib abstract | |
David Ryan Koes and Seth Copen Goldstein.
In Proceedings of the International Symposium on Code Generation and Optimization (CGO'08),
2008.
|
| hide Abstract | Instruction selection is a key component of code generation. High
quality instruction selection is of particular importance in the embedded space where complex instruction sets are common and code size is a prime concern. Although instruction selection on tree expressions is a well understood and easily solved problem, instruction selection on directed acyclic graphs is NP-complete. In this paper we present NOLTIS, a near-optimal, linear time instruction selection algorithm for DAG expressions. NOLTIS is easy to implement, fast, and effective with a demonstrated average code size improvement of 5.1% compared to the traditional tree decomposition
and tiling approach. |
| | @inproceedings{koes-cgo08,
author = {Koes, David Ryan and Goldstein, Seth Copen},
title = {Near-Optimal Instruction Selection on {DAG}s},
booktitle = {Proceedings of the International Symposium on Code
Generation and Optimization {(CGO'08)}},
year = {2008},
keywords = {Compilers:Instruction Selection},
abstract = {Instruction selection is a key component of code
generation. High quality instruction selection is of particular
importance in the embedded space where complex instruction sets
are common and code size is a prime concern. Although instruction
selection on tree expressions is a well understood and easily
solved problem, instruction selection on directed acyclic graphs
is NP-complete. In this paper we present NOLTIS, a near-optimal,
linear time instruction selection algorithm for DAG expressions.
NOLTIS is easy to implement, fast, and effective with a
demonstrated average code size improvement of 5.1\% compared to
the traditional tree decomposition and tiling approach.},
publisher = {IEEE Computer Society},
url = {http://www.cs.cmu.edu/~seth/papers/koes-cgo08.pdf},
address = {Washington, DC, USA}
}
|
|
Programming Modular Robots with Locally Distributed Predicates | pdf bib abstract | |
Michael De Rosa, Seth Copen Goldstein, Peter Lee, Jason D. Campbell, and Padmanabhan Pillai.
In Proceedings of the IEEE International Conference on Robotics and Automation ICRA '08,
2008.
|
| hide Abstract | We present a high-level language for programming modular robotic systems, based on locally distributed predicates (LDP), which are distributed conditions that hold for a connected subensemble of the robotic system. An LDP program is a collection of LDPs with associated actions which are triggered on any subensemble that matches the predicate. The result is a reactive programming language which efficiently and concisely supports ensemble-level programming. We demonstrate the utility of LDP by implementing three common, but diverse, modular robotic tasks. |
| | @inproceedings{derosa-icra08,
author = {De~Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
and Campbell, Jason D. and Pillai, Padmanabhan},
booktitle = {Proceedings of the IEEE International Conference on
Robotics and Automation {ICRA '08}},
keywords = {Claytronics, Modular Robotics, Programming, LDP},
title = {Programming Modular Robots with Locally Distributed
Predicates},
year = {2008},
abstract = {We present a high-level language for programming modular
robotic systems, based on locally distributed predicates (LDP),
which are distributed conditions that hold for a connected
subensemble of the robotic system. An LDP program is a collection
of LDPs with associated actions which are triggered on any
subensemble that matches the predicate. The result is a reactive
programming language which efficiently and concisely supports
ensemble-level programming. We demonstrate the utility of LDP by
implementing three common, but diverse, modular robotic tasks.},
url = {http://www.cs.cmu.edu/~claytronics/papers/derosa-icra08.pdf}
}
|
|
Slack Analysis in the System Design Loop | bib talk | |
Girish Venkataramani and Seth Copen Goldstein.
In IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS),
pages 231–236, October, 2008.
|
| @inproceedings{venkataramani-codes08,
author = {Venkataramani, Girish and Goldstein, Seth Copen},
booktitle = {IEEE/ACM/IFIP International Conference on
Hardware/Software Codesign and System Synthesis {(CODES-ISSS)}},
year = {2008},
address = {Atlanta, GE},
month = {October},
keywords = {Asychronous Circuits, CAD, Global Critical Path},
title = {Slack Analysis in the System Design Loop},
pages = {231--236}
}
|
|
Generalizing Metamodules to Simplify Planning in Modular
Robotic Systems | pdf bib abstract | |
Daniel Dewey, Siddhartha S. Srinivasa, Michael P. Ashley-Rollman, Michael De Rosa, Padmanabhan Pillai, Todd C. Mowry, Jason D. Campbell, and Seth Copen Goldstein.
In Proceedings of IEEE/RSJ 2008 International Conference on Intelligent Robots and Systems IROS '08,
September, 2008.
|
| hide Abstract | In this paper we develop a theory of metamodules
and an associated distributed asynchronous planner which generalizes previous work on metamodules for lattice-based modular robotic systems. All extant modular robotic systems have some form of non-holonomic motion constraints. This has prompted many researchers to look to metamodules, i.e., groups of modules that act as a unit, as a way to reduce motion constraints and the complexity of planning. However, previous metamodule designs have been specific to a particular modular robot. By analyzing the constraints found in modular robotic systems we develop a holonomic metamodule which has two important properties: (1) it can be used as the basic unit of an
efficient planner and (2) it can be instantiated by a wide variety
of different underlying modular robots, e.g., modular robot arms, expanding cubes, hex-packed spheres, etc. Using a series of transformations we show that our practical metamodule system has a provably complete planner. Finally, our approach allows the task of shape transformation to be separated into a planning task and a resource allocation task. We implement our planner for two different metamodule systems and show that the time to completion scales linearly with the diameter of the ensemble. |
| | @inproceedings{dewey-iros08,
author = {Dewey, Daniel and Srinivasa, Siddhartha S. and
Ashley-Rollman, Michael P. and De~Rosa, Michael and Pillai,
Padmanabhan and Mowry, Todd C. and Campbell, Jason D. and
Goldstein, Seth Copen},
title = {Generalizing Metamodules to Simplify Planning in Modular
Robotic Systems},
booktitle = {Proceedings of IEEE/RSJ 2008 International Conference
on Intelligent Robots and Systems {IROS '08}},
year = {2008},
address = {Nice, France},
month = {September},
abstract = {In this paper we develop a theory of metamodules and an
associated distributed asynchronous planner which generalizes
previous work on metamodules for lattice-based modular robotic
systems. All extant modular robotic systems have some form of
non-holonomic motion constraints. This has prompted many
researchers to look to metamodules, i.e., groups of modules that
act as a unit, as a way to reduce motion constraints and the
complexity of planning. However, previous metamodule designs have
been specific to a particular modular robot. By analyzing the
constraints found in modular robotic systems we develop a
holonomic metamodule which has two important properties: (1) it
can be used as the basic unit of an efficient planner and (2) it
can be instantiated by a wide variety of different underlying
modular robots, e.g., modular robot arms, expanding cubes,
hex-packed spheres, etc. Using a series of transformations we
show that our practical metamodule system has a provably complete
planner. Finally, our approach allows the task of shape
transformation to be separated into a planning task and a
resource allocation task. We implement our planner for two
different metamodule systems and show that the time to completion
scales linearly with the diameter of the ensemble.},
url = {http://www.cs.cmu.edu/~claytronics/papers/dewey-iros08.pdf},
keywords = {Meld, Planning, Multi-Robot Formations, Controlling
Ensembles, Robotics}
}
|
|
Distributed Localization of Modular Robot Ensembles | pdf bib abstract | |
Stanislav Funiak, Padmanabhan Pillai, Michael P. Ashley-Rollman, Jason D. Campbell, and Seth Copen Goldstein.
In Proceedings of Robotics: Science and Systems,
June, 2008.
|
| | | |
|
Distributed Watchpoints: Debugging Large Modular Robotic Systems | pdf bib abstract | |
Michael De Rosa, Seth Copen Goldstein, Peter Lee, Jason D. Campbell, and Padmanabhan Pillai.
International Journal of Robotics Research,
27(3),March, 2008.
Also appeared as Distributed Watchpoints: Debugging Large Multi-Robot Systems, (icra07).
|
| hide Abstract | Distributed systems frequently exhibit properties of interest which span multiple entities. These properties cannot easily be detected from any single entity, but can be readily be detected by combining the knowledge of multiple entities. Testing for distributed properties is especially important in debugging or verifying software for modular robots. We have developed a technique we call distributed watchpoint triggers which can efficiently recognize distributed conditions. Our watchpoint description language can handle a variety of temporal, spatial, and logical properties spanning multiple robots. This paper presents the specification language, describes the distributed online mechanism for detecting distributed conditions in a running system, and evaluates the performance of our implementation. |
| | @article{mderosa-ijrr-2008,
author = {De~Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
and Campbell, Jason D. and Pillai, Padmanabhan},
journal = {International Journal of Robotics Research},
keywords = {Debugging, Distributed Systems},
month = {March},
url = {http://www.cs.cmu.edu/~claytronics/papers/mderosa-ijrr-2008.pdf},
number = {3},
title = {Distributed Watchpoints: Debugging Large Modular Robotic
Systems},
abstract = {Distributed systems frequently exhibit properties of
interest which span multiple entities. These properties cannot
easily be detected from any single entity, but can be readily be
detected by combining the knowledge of multiple entities. Testing
for distributed properties is especially important in debugging
or verifying software for modular robots. We have developed a
technique we call distributed watchpoint triggers which can
efficiently recognize distributed conditions. Our watchpoint
description language can handle a variety of temporal, spatial,
and logical properties spanning multiple robots. This paper
presents the specification language, describes the distributed
online mechanism for detecting distributed conditions in a
running system, and evaluates the performance of our
implementation.},
volume = {27},
also = {Distributed Watchpoints: Debugging Large Multi-Robot
Systems, (icra07)},
year = {2008}
}
|
2007 |
Operation Chaining Asynchronous Pipelined Circuits | pdf bib abstract | |
Girish Venkataramani and Seth Copen Goldstein.
In ICCAD,
November, 2007.
|
| hide Abstract | We define operation chaining (op-chaining) as an optimization problem to determine the optimal pipeline depth for balancing performance against energy demands in pipelined asynchronous designs. Since there are no clock period requirements, asynchronous pipeline stages can have non-uniform latencies. We exploit this fact to coalesce several stages together thereby saving power and area due to the elimination of control-path resources from the pipeline. The trade-off is potentially reduced pipeline parallelism.
In this paper, we formally define this optimization as a graph covering problem, which finds sub-graphs that will be synthesized as an opchained pipeline stage. We then define the solution space for provably correct solutions and present an algorithm to efficiently search this space. The search technique partitions the graph based on post-dominator relationships to find sub-graphs that are potential op-chain candidates. We use knowledge of the Global Critical Path (GCP) [13] to evaluate the performance impact of accepting a candidate sub-graph and formulate a heuristic cost function to model this trade-off. The algorithm has a quadratic-time complexity in the size of the dataflow graph. We have implemented this algorithm within an automated asynchronous synthesis toolchain [12]. Experimental evidence from applying the algorithm on several media processing kernels reveals that the average energy-delay and energy-delay-area products improve by about 1.4x and 1.8x respectively, with a maximum improvement of 5x and 18x. |
| | @inproceedings{venkataramani-iccad07,
author = {Venkataramani, Girish and Goldstein, Seth Copen},
title = {Operation Chaining Asynchronous Pipelined Circuits},
booktitle = {ICCAD},
abstract = {We define operation chaining (op-chaining) as an
optimization problem to determine the optimal pipeline depth for
balancing performance against energy demands in pipelined
asynchronous designs. Since there are no clock period
requirements, asynchronous pipeline stages can have non-uniform
latencies. We exploit this fact to coalesce several stages
together thereby saving power and area due to the elimination of
control-path resources from the pipeline. The trade-off is
potentially reduced pipeline parallelism. In this paper, we
formally define this optimization as a graph covering problem,
which finds sub-graphs that will be synthesized as an opchained
pipeline stage. We then define the solution space for provably
correct solutions and present an algorithm to efficiently search
this space. The search technique partitions the graph based on
post-dominator relationships to find sub-graphs that are
potential op-chain candidates. We use knowledge of the Global
Critical Path (GCP) [13] to evaluate the performance impact of
accepting a candidate sub-graph and formulate a heuristic cost
function to model this trade-off. The algorithm has a
quadratic-time complexity in the size of the dataflow graph. We
have implemented this algorithm within an automated asynchronous
synthesis toolchain [12]. Experimental evidence from applying the
algorithm on several media processing kernels reveals that the
average energy-delay and energy-delay-area products improve by
about 1.4x and 1.8x respectively, with a maximum improvement of
5x and 18x.},
month = {November},
year = {2007},
url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iccad07.pdf},
keywords = {Asychronous Circuits, CAD, Global Critical Path}
}
|
|
A Modular Robotic System Using Magnetic Force Effectors | pdf bib abstract | |
Brian Kirby, Burak Aksak, Seth Copen Goldstein, James F. Hoburg, Todd C. Mowry, and Padmanabhan Pillai.
In Proceedings of the IEEE International Conference on Intelligent Robots and Systems (IROS '07),
October, 2007.
|
| hide Abstract | One of the primary impediments to building ensembles
with many modular robots is the complexity and number of mechanical mechanisms used to construct the individual modules. As part of the Claytronics project—which aims to build very large ensembles of modular robots—we investigate how to simplify each module by eliminating moving parts and reducing the number of mechanical mechanisms on each robot by using force-at-a-distance actuators. Additionally, we are also investigating the feasibility of using these unary actuators to improve docking performance, implement intermodule adhesion, power transfer, communication, and sensing. |
| | @inproceedings{bkirby-iros07,
author = {Kirby, Brian and Aksak, Burak and Goldstein, Seth Copen
and Hoburg, James F. and Mowry, Todd C. and Pillai, Padmanabhan},
title = {A Modular Robotic System Using Magnetic Force Effectors},
booktitle = {Proceedings of the IEEE International Conference on
Intelligent Robots and Systems ({IROS '07})},
year = {2007},
month = {October},
abstract = {One of the primary impediments to building ensembles
with many modular robots is the complexity and number of
mechanical mechanisms used to construct the individual modules.
As part of the Claytronics project---which aims to build very
large ensembles of modular robots---we investigate how to
simplify each module by eliminating moving parts and reducing the
number of mechanical mechanisms on each robot by using
force-at-a-distance actuators. Additionally, we are also
investigating the feasibility of using these unary actuators to
improve docking performance, implement intermodule adhesion,
power transfer, communication, and sensing.},
keywords = {Claytronics, Actuation, Adhesion},
url = {http://www.cs.cmu.edu/~claytronics/papers/bkirby-iros07.pdf}
}
|
|
A Scalable Distributed Algorithm for Shape Transformation in Multi-Robot Systems | pdf bib abstract | |
Ramprasad Ravichandran, Geoffrey Gordon, and Seth Copen Goldstein.
In Proceedings of the IEEE International Conference on Intelligent Robots and Systems IROS '07,
October, 2007.
|
| hide Abstract | Distributed reconfiguration is an important problem in multi-robot systems such as mobile sensor nets and metamorphic robot systems. In this work, we present a scalable distributed reconfiguration algorithm, Hierarchical Median Decomposition, to achieve arbitrary target configurations. Our algorithm is built on top of a novel distributed median consensus estimator. The algorithms presented are fully distributed and do not require global communication. We show results from simulations in an open source multi-robot simulator. |
| | @inproceedings{ravichandran-iros07,
author = {Ravichandran, Ramprasad and Gordon, Geoffrey and
Goldstein, Seth Copen},
title = {A Scalable Distributed Algorithm for Shape Transformation
in Multi-Robot Systems},
booktitle = {Proceedings of the IEEE International Conference on
Intelligent Robots and Systems {IROS '07}},
year = {2007},
month = {October},
keywords = {Claytronics, Multi-Robot Formations},
abstract = {Distributed reconfiguration is an important problem in
multi-robot systems such as mobile sensor nets and metamorphic
robot systems. In this work, we present a scalable distributed
reconfiguration algorithm, Hierarchical Median Decomposition, to
achieve arbitrary target configurations. Our algorithm is built
on top of a novel distributed median consensus estimator. The
algorithms presented are fully distributed and do not require
global communication. We show results from simulations in an open
source multi-robot simulator.},
url = {http://www.cs.cmu.edu/~claytronics/papers/ravichandran-iros07.pdf}
}
|
|
Declarative Programming for Modular Robots | pdf bib abstract | |
Michael P. Ashley-Rollman, Michael De Rosa, Siddhartha S. Srinivasa, Padmanabhan Pillai, Seth Copen Goldstein, and Jason D. Campbell.
In Workshop on Self-Reconfigurable Robots/Systems and Applications at IROS '07,
October, 2007.
|
| hide Abstract | Because of the timing, complexity, and asynchronicity challenges common in modular robot software we have recently begun to explore new programming models for modular robot ensembles. In this paper we apply two of those models to a metamodule-based shape planning algorithm and comment on the differences between the two approaches. Our results suggest that declarative programming can provide several advantages over more traditional imperative approaches, and that the differences between declarative programming styles can themselves contribute leverage to different parts of the problem domain. |
| | @inproceedings{ashley-rollman-derosa-iros07wksp,
author = {Ashley-Rollman, Michael P. and De~Rosa, Michael and
Srinivasa, Siddhartha S. and Pillai, Padmanabhan and Goldstein,
Seth Copen and Campbell, Jason D.},
title = {Declarative Programming for Modular Robots},
booktitle = {Workshop on Self-Reconfigurable Robots/Systems and
Applications at {IROS '07}},
year = {2007},
month = {October},
keywords = {Claytronics, Programming Models, Planning, LDP, Meld},
abstract = {Because of the timing, complexity, and asynchronicity
challenges common in modular robot software we have recently
begun to explore new programming models for modular robot
ensembles. In this paper we apply two of those models to a
metamodule-based shape planning algorithm and comment on the
differences between the two approaches. Our results suggest that
declarative programming can provide several advantages over more
traditional imperative approaches, and that the differences
between declarative programming styles can themselves contribute
leverage to different parts of the problem domain.},
url = {http://www.cs.cmu.edu/~claytronics/papers/ashley-rollman-derosa-iros07wksp.pdf}
}
|
|
Electrostatic Latching for Inter-module Adhesion, Power
Transfer, and Communication in Modular Robots | pdf bib abstract | |
Mustafa Emre Karagozler, Jason D. Campbell, Gary K. Fedder, Seth Copen Goldstein, Michael Philetus Weller, and Byung W. Yoon.
In Proceedings of the IEEE International Conference on
Intelligent Robots and Systems (IROS '07),
October, 2007.
|
| hide Abstract | A simple and robust inter-module latch is possibly the
most important component of a modular robotic system. This paper describes a latch based on capacitive coupling which not only provides significant adhesion forces, but can also be used for inter-module power transmission and communication. The key insight that enables electrostatic adhesion to be effective at the macroscale is to combine flexible electrodes with a geometery that uses shear forces to provide adhesion. To measure the effectiveness of our latch we incorporated it into a 28cm x 28cm x 28cm modular robot. The result is a latch which requires almost zero static power and yet can hold over 0.6N/cm^2 of latch area. |
| | @inproceedings{karagozler-iros07,
author = {Karagozler, Mustafa Emre and Campbell, Jason D. and
Fedder, Gary K. and Goldstein, Seth Copen and Weller, Michael
Philetus and Yoon, Byung W.},
title = {Electrostatic Latching for Inter-module Adhesion, Power
Transfer, and Communication in Modular Robots},
booktitle = {Proceedings of the IEEE International Conference on
Intelligent Robots and Systems ({IROS '07})},
year = {2007},
month = {October},
abstract = {A simple and robust inter-module latch is possibly the
most important component of a modular robotic system. This paper
describes a latch based on capacitive coupling which not only
provides significant adhesion forces, but can also be used for
inter-module power transmission and communication. The key
insight that enables electrostatic adhesion to be effective at
the macroscale is to combine flexible electrodes with a geometery
that uses shear forces to provide adhesion. To measure the
effectiveness of our latch we incorporated it into a 28cm x 28cm
x 28cm modular robot. The result is a latch which requires almost
zero static power and yet can hold over 0.6N/cm^2 of latch
area.},
keywords = {Actuation, Adhesion, Claytronics},
url = {http://www.cs.cmu.edu/~claytronics/papers/karagozler-iros07.pdf}
}
|
|
Internal Localization of Modular Robot Ensembles | pdf bib abstract | |
Stanislav Funiak, Padmanabhan Pillai, Jason D. Campbell, and Seth Copen Goldstein.
In Workshop on Self-Reconfiguring Modular Robotics at the IEEE International Conference on Intelligent Robots and Systems (IROS) '07,
October, 2007.
|
| hide Abstract | The determination of the relative position and pose of every robot in a modular robotic ensemble is a necessary preliminary step for most modular robotic tasks. Localization is particularly important when the modules make local noisy observations and are not significantly constrained by inter-robot latches. In this paper, we propose a robust hierarchical approach to the internal localization problem that uses normalized cut to identify subproblems with small localization error.
A key component of our solution is a simple method to reduce the cost of normalized cut computations. The result is a robust algorithm that scales to large, non-homogeneous ensembles. We evaluate our algorithm in simulation on ensembles of up to 10,000 modules, demonstrating substantial improvements over prior work. |
| | @inproceedings{funiak-iros07,
author = {Funiak, Stanislav and Pillai, Padmanabhan and Campbell,
Jason D. and Goldstein, Seth Copen},
title = {Internal Localization of Modular Robot Ensembles},
booktitle = {Workshop on Self-Reconfiguring Modular Robotics at the
IEEE International Conference on Intelligent Robots and Systems
(IROS) '07},
year = {2007},
month = {October},
abstract = {The determination of the relative position and pose of
every robot in a modular robotic ensemble is a necessary
preliminary step for most modular robotic tasks. Localization is
particularly important when the modules make local noisy
observations and are not significantly constrained by inter-robot
latches. In this paper, we propose a robust hierarchical approach
to the {\em internal localization} problem that uses normalized
cut to identify subproblems with small localization error. A key
component of our solution is a simple method to reduce the cost
of normalized cut computations. The result is a robust algorithm
that scales to large, non-homogeneous ensembles. We evaluate our
algorithm in simulation on ensembles of up to 10,000 modules,
demonstrating substantial improvements over prior work.},
keywords = {Claytronics, Probabilistic Inference, Sensing,
Localization, Distributed Algorithms},
url = {http://www.cs.cmu.edu/~claytronics/papers/funiak-iros07.pdf}
}
|
|
Meld: A Declarative Approach to Programming Ensembles | pdf bib abstract | |
Michael P. Ashley-Rollman, Seth Copen Goldstein, Peter Lee, Todd C. Mowry, and Padmanabhan Pillai.
In Proceedings of the IEEE International Conference on Intelligent Robots and Systems (IROS '07),
October, 2007.
|
| hide Abstract | This paper presents Meld, a programming language for modular robots, i.e., for independently executing robots where inter-robot communication is limited to immediate neighbors. Meld is a declarative language, based on P2, a logic-programming language originally designed for programming overlay networks. By using logic programming, the code for an ensemble of robots can be written from a global perspective, as opposed to a large collection of independent robot views.
This greatly simplifies the thought process needed for programming large ensembles. Initial experience shows that this also leads to a considerable reduction in code size and complexity. An initial implementation of Meld has been completed and has been used to demonstrate its effectiveness in the Claytronics simulator. Early results indicate that Meld programs are considerably more concise (more than 20x shorter) than programs written in C++, while running nearly as efficiently. |
| | @inproceedings{ashley-rollman-iros07,
author = {Ashley-Rollman, Michael P. and Goldstein, Seth Copen and
Lee, Peter and Mowry, Todd C. and Pillai, Padmanabhan},
title = {Meld: A Declarative Approach to Programming Ensembles},
booktitle = {Proceedings of the IEEE International Conference on
Intelligent Robots and Systems ({IROS '07})},
year = {2007},
month = {October},
keywords = {Claytronics, Programming Languages, Meld},
abstract = {This paper presents Meld, a programming language for
modular robots, i.e., for independently executing robots where
inter-robot communication is limited to immediate neighbors. Meld
is a declarative language, based on P2, a logic-programming
language originally designed for programming overlay networks. By
using logic programming, the code for an ensemble of robots can
be written from a global perspective, as opposed to a large
collection of independent robot views. This greatly simplifies
the thought process needed for programming large ensembles.
Initial experience shows that this also leads to a considerable
reduction in code size and complexity. An initial implementation
of Meld has been completed and has been used to demonstrate its
effectiveness in the Claytronics simulator. Early results
indicate that Meld programs are considerably more concise (more
than 20x shorter) than programs written in C++, while running
nearly as efficiently.},
url = {http://www.cs.cmu.edu/~claytronics/papers/ashley-rollman-iros07.pdf}
}
|
|
Movement Primitives for an Orthogonal Prismatic Closed-Lattice-Constrained Self-Reconfiguring Module | pdf bib abstract | |
Michael Philetus Weller, Mustafa Emre Karagozler, Brian Kirby, Jason D. Campbell, and Seth Copen Goldstein.
In Workshop on Self-Reconfiguring Modular Robotics at the IEEE International Conference on Intelligent Robots and Systems (IROS) '07,
October, 2007.
|
| hide Abstract | We describe a new set of prismatic movement primitives for cubic modular robots. Our approach appears more practical than previous metamodule-based approaches.
We also describe recent hardware developments in our cubic robot modules that have sufficient stiffness and actuator strength so that when they work together they can realize, in earth’s gravity, all of the motion primitives we describe here. |
| | @inproceedings{weller-iros07,
author = {Weller, Michael Philetus and Karagozler, Mustafa Emre and
Kirby, Brian and Campbell, Jason D. and Goldstein, Seth Copen},
title = {Movement Primitives for an Orthogonal Prismatic
Closed-Lattice-Constrained Self-Reconfiguring Module},
booktitle = {Workshop on Self-Reconfiguring Modular Robotics at the
IEEE International Conference on Intelligent Robots and Systems
(IROS) '07},
year = {2007},
month = {October},
keywords = {Claytronics, Adhesion, Robotics, Planning},
abstract = {We describe a new set of prismatic movement primitives
for cubic modular robots. Our approach appears more practical
than previous metamodule-based approaches. We also describe
recent hardware developments in our cubic robot modules that have
sufficient stiffness and actuator strength so that when they work
together they can realize, in earth's gravity, all of the motion
primitives we describe here.},
url = {http://www.cs.cmu.edu/~claytronics/papers/weller-iros07.pdf}
}
|
|
Global Critical Path: A Tool for System-Level Timing Analysis | pdf bib abstract | |
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, and Seth Copen Goldstein.
In Proceedings of the 44th ACM/IEEE Design Automation Conference,
pages 783–786, June, 2007.
|
| hide Abstract | An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is defined at the RTL level, as the longest path in the combinational logic between clocked reisters. In this paper, we present a system-level timing analysis technique to define the concept of a Global Critical Path (GCP), for predicting system-level performance. We show how the GCP can be used as a theoretical and practical tool for understanding, summarizing and optimizing the behavior of highly concurrent self-timed circuits. We formally define the GCP and show how it can be constructed using a discrete event model and hardware profiling techniques. The GCP provides valuable insight into the control-path behavior of circuits and in finding system-level bottlenecks. We have incorporated the GCP construction and analysis framework into a high-level synthesis and simulation toolchain, thus enabling complete automation in modeling, analysis and optimization. |
| | @inproceedings{dac07-gcp,
author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
Tiberiu and Goldstein, Seth Copen},
title = {Global Critical Path: A Tool for System-Level Timing
Analysis},
booktitle = {Proceedings of the 44th ACM/IEEE Design Automation
Conference},
year = {2007},
month = {June},
address = {San Diego, CA},
pages = {783--786},
abstract = {An effective method for focusing optimization effort on
the most important parts of a design is to examine those elements
on the critical path. Traditionally, the critical path is defined
at the RTL level, as the longest path in the combinational logic
between clocked reisters. In this paper, we present a
system-level timing analysis technique to define the concept of a
Global Critical Path (GCP), for predicting system-level
performance. We show how the GCP can be used as a theoretical and
practical tool for understanding, summarizing and optimizing the
behavior of highly concurrent self-timed circuits. We formally
define the GCP and show how it can be constructed using a
discrete event model and hardware profiling techniques. The GCP
provides valuable insight into the control-path behavior of
circuits and in finding system-level bottlenecks. We have
incorporated the GCP construction and analysis framework into a
high-level synthesis and simulation toolchain, thus enabling
complete automation in modeling, analysis and optimization.},
url = {http://www.cs.cmu.edu/~seth/papers/dac07-gcp.pdf},
keywords = {Asychronous Circuits, CAD, Global Critical Path, System
modeling, Hardware profiling}
}
|
|
Self-Resetting Latches for Asynchronous Micro-Pipelines | pdf bib abstract | |
Tiberiu Chelcea, Girish Venkataramani, and Seth Copen Goldstein.
In Proceedings of the 44th ACM/IEEE Design Automation Conference,
pages 986–989, June, 2007.
|
| hide Abstract | Asynchronous circuits are increasingly attractive as low power or high-performance replacements to synchronous designs. A key part of these circuits are asynchronous micropipelines; unfortunatelly, the existing micropipeline styles either improve performance or decrease power consumption, but not both. Very often, the pipeline register plays a crucial role in these cost metrics. In this paper we introduce a new register design, called self-resetting latches, for asynchronous micropipelines which bridges the gap between fast, but power hungry, latch-based designs and slow, but low power, flip-flop designs. The energy-delay metric for large asynchronous systems implemented with self-resetting latches is, on average, 41% better than latch-based designs and 15% better than flip-flop designs. |
| | @inproceedings{dac07-sr,
author = {Chelcea, Tiberiu and Venkataramani, Girish and Goldstein,
Seth Copen},
title = {Self-Resetting Latches for Asynchronous Micro-Pipelines},
booktitle = {Proceedings of the 44th ACM/IEEE Design Automation
Conference},
year = {2007},
month = {June},
address = {San Diego, CA},
pages = {986--989},
keywords = {Asychronous Circuits},
abstract = {Asynchronous circuits are increasingly attractive as low
power or high-performance replacements to synchronous designs. A
key part of these circuits are asynchronous micropipelines;
unfortunatelly, the existing micropipeline styles either improve
performance or decrease power consumption, but not both. Very
often, the pipeline register plays a crucial role in these cost
metrics. In this paper we introduce a new register design, called
self-resetting latches, for asynchronous micropipelines which
bridges the gap between fast, but power hungry, latch-based
designs and slow, but low power, flip-flop designs. The
energy-delay metric for large asynchronous systems implemented
with self-resetting latches is, on average, 41\% better than
latch-based designs and 15\% better than flip-flop designs.},
url = {http://www.cs.cmu.edu/~seth/papers/dac07-sr.pdf}
}
|
|
Distributed Watchpoints: Debugging Large Multi-Robot Systems | pdf bib abstract | |
Michael De Rosa, Seth Copen Goldstein, Peter Lee, Jason D. Campbell, Padmanabhan Pillai, and Todd C. Mowry.
In Proceedings of the IEEE International Conference on Robotics and Automation ICRA '07,
April, 2007.
|
| hide Abstract | Tightly-coupled multi-agent systems such as modular robots frequently exhibit properties of interest that span multiple modules. These properties cannot easily be detected from any single module, though they might readily be detected by combining the knowledge of multiple modules. Testing for distributed conditions is especially important in debugging or verifying the correctness of software for modular robots. We have developed a technique we call distributed watchpoint triggers which can efficiently recognize such distributed conditions. Our watchpoint description language can handle a variety of temporal, spatial, and logical properties spanning multiple robots. This paper presents that language, describes our fully-distributed, online mechanism for detecting distributed conditions in a running system, and evaluates the performance of our implementation. We found that the performance of the system is highly dependent on the program being debugged, scales linearly with ensemble size, and is small enough to make the system practical in all but the worst case scenarios. |
| | @inproceedings{derosa-icra07,
abstract = {Tightly-coupled multi-agent systems such as modular
robots frequently exhibit properties of interest that span
multiple modules. These properties cannot easily be detected from
any single module, though they might readily be detected by
combining the knowledge of multiple modules. Testing for
distributed conditions is especially important in debugging or
verifying the correctness of software for modular robots. We have
developed a technique we call distributed watchpoint triggers
which can efficiently recognize such distributed conditions. Our
watchpoint description language can handle a variety of temporal,
spatial, and logical properties spanning multiple robots. This
paper presents that language, describes our fully-distributed,
online mechanism for detecting distributed conditions in a
running system, and evaluates the performance of our
implementation. We found that the performance of the system is
highly dependent on the program being debugged, scales linearly
with ensemble size, and is small enough to make the system
practical in all but the worst case scenarios.},
author = {De~Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
and Campbell, Jason D. and Pillai, Padmanabhan and Mowry, Todd
C.},
booktitle = {Proceedings of the IEEE International Conference on
Robotics and Automation {ICRA '07}},
title = {Distributed Watchpoints: Debugging Large Multi-Robot
Systems},
year = {2007},
month = {April},
keywords = {Debugging, Distributed Algorithms},
url = {http://www.cs.cmu.edu/~claytronics/papers/derosa-icra07.pdf}
}
|
|
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis | pdf bib abstract | |
Tiberiu Chelcea, Girish Venkataramani, and Seth Copen Goldstein.
In Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems,
pages 117–128, March, 2007.
|
| hide Abstract | Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous toolflows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal algorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding better average-case latencies than their synchronous counterparts. |
| | @inproceedings{chelcea-async07,
author = {Chelcea, Tiberiu and Venkataramani, Girish and Goldstein,
Seth Copen},
title = {Area Optimizations for Dual-Rail Circuits Using
Relative-Timing Analysis},
booktitle = {Proceedings of the 13th IEEE International Symposium on
Asynchronous Circuits and Systems},
year = {2007},
address = {Berkeley, CA},
month = {March},
pages = {117--128},
abstract = {Future deep sub-micron technologies will be
characterized by large parametric variations, which could make
asynchronous design an attractive solution for use on large
scale. However, the investment in asynchronous CAD tools does not
approach that in synchronous ones. Even when asynchronous tools
leverage existing synchronous toolflows, they introduce large
area and speed overheads. This paper proposes several heuristic
and optimal algorithms, based on timing interval analysis, for
improving existing asynchronous CAD solutions by optimizing area.
The optimized circuits are 2.4 times smaller for an optimal
algorithm and 1.8 times smaller for a heuristic one than the
existing solutions. The optimized circuits are also shown to be
resilient to large parametric variations, yielding better
average-case latencies than their synchronous counterparts.},
url = {http://www.cs.cmu.edu/~seth/papers/chelcea-async07.pdf},
keywords = {Asychronous Circuits, CAD}
}
|
2006 |
A Better Global Progressive Allocator | pdf bib abstract | |
David Ryan Koes and Seth Copen Goldstein.
In LCTES 06 Student Poster Session,
2006.
|
| hide Abstract | We present an improvement to the simultaneous heuristic allocator component of the global progressive register allocator described in our previous work \cite{koes-pldi2006}. Our improved allocator decomposes the control flow graph into linear traces which are allocated in the same manner as a single basic block. We investigate two methods for handling the control flow within the traces both of which produce better quality allocations than the simultaneous heuristic allocator. |
| | @inproceedings{koes-lctes06,
author = {Koes, David Ryan and Goldstein, Seth Copen},
title = {A Better Global Progressive Allocator},
publisher = {Academia Press},
url = {http://www.cs.cmu.edu/~seth/papers/koes-lctes06.pdf},
booktitle = {LCTES 06 Student Poster Session},
year = {2006},
abstract = {We present an improvement to the simultaneous heuristic
allocator component of the global progressive register allocator
described in our previous work \cite{koes-pldi2006}. Our improved
allocator decomposes the control flow graph into linear traces
which are allocated in the same manner as a single basic block.
We investigate two methods for handling the control flow within
the traces both of which produce better quality allocations than
the simultaneous heuristic allocator.},
keywords = {Compilers:Register Allocation}
}
|
|
A global progressive register allocator | pdf bib abstract | |
David Ryan Koes and Seth Copen Goldstein.
In Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation (PLDI'06),
pages 204–215, 2006.
|
| hide Abstract | This paper describes a global progressive register allocator, a register allocator that uses an expressive model of the register allocation problem to quickly find a good allocation and then progressively find better allocations until a provably optimal solution is found or a preset time limit is reached. The key contributions of this paper are an expressive model of global register allocation based on multi-commodity network flows that explicitly represents spill code optimization, register preferences, copy insertion, and constant rematerialization; two fast, but effective, heuristic allocators based on this model; and a more elaborate progressive allocator that uses Lagrangian relaxation to compute the optimality of its allocations. Our progressive allocator demonstrates code size improvements as large as 16.75% compared to a traditional graph allocator. On average, we observe an initial improvement of 3.47%, which increases progressively to 6.84% as more time is permitted for compilation. |
| | @inproceedings{koes-pldi2006,
author = {Koes, David Ryan and Goldstein, Seth Copen},
title = {A global progressive register allocator},
booktitle = {Proceedings of the 2006 ACM SIGPLAN conference on
Programming language design and implementation (PLDI'06)},
year = {2006},
isbn = {1-59593-320-4},
pages = {204--215},
doi = {http://doi.acm.org/10.1145/1133981.1134006},
publisher = {ACM Press},
address = {New York, NY},
abstract = {This paper describes a {\em global progressive register
allocator}, a register allocator that uses an expressive model of
the register allocation problem to quickly find a good allocation
and then progressively find better allocations until a provably
optimal solution is found or a preset time limit is reached. The
key contributions of this paper are an expressive model of global
register allocation based on multi-commodity network flows that
explicitly represents spill code optimization, register
preferences, copy insertion, and constant rematerialization; two
fast, but effective, heuristic allocators based on this model;
and a more elaborate progressive allocator that uses Lagrangian
relaxation to compute the optimality of its allocations. Our
progressive allocator demonstrates code size improvements as
large as 16.75\% compared to a traditional graph allocator. On
average, we observe an initial improvement of 3.47\%, which
increases progressively to 6.84\% as more time is permitted for
compilation.},
keywords = {Compilers:Register Allocation},
url = {http://www.cs.cmu.edu/~seth/papers/koes-pldi2006.pdf}
}
|
|
Hardware Compilation of Application-Specific Memory Access Interconnect | pdf bib abstract | |
Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, and Seth Copen Goldstein.
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems,
25(5):756–771,2006.
|
| hide Abstract | A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integrated circuit systems is the presence of memory accesses to a shared-memory subsystem. The latency to access memory is often not statically predictable, which creates problems for scheduling operations dependent on memory reads. More fundamental is that dependences between accesses may not be statically provable (e.g., if the specification language permits pointers), which introduces memory-consistency problems. Addressing these issues with static scheduling results in overly conservative circuits, and thus, most state-of-the-art HLS tools limit memory systems to those that have predictable latencies and limit programmers to specifications that forbid arbitrary memory-reference patterns. A new HLS framework for the synthesis and optimization of memory accesses (SOMA) is presented. SOMA enables specifications to include arbitrary memory references (e.g., pointers) and allows the memory system to incorporate features that might cause the latency of a memory access to vary dynamically. This results in raising the level of abstraction in the input specification, enabling faster design times. SOMA synthesizes a memory access network (MAN) architecture that facilitates dynamic scheduling and ordering of memory accesses. The paper describes a basic MAN construction technique that illustrates how dynamic ordering helps in efficiently maintaining memory consistency and how dynamic scheduling helps alleviate the variable-latency problem. Then, it is shown how static analysis of the access patterns can be used to optimize the MAN. One optimization changes the MAN interconnect topology to increase concurrence. A second optimization reduces the synchronization overhead necessary to maintain memory consistency. Postlayout experiments demonstrate that SOMA’s application-specific MAN construction significantly improves power and performance for a range of benchmarks. |
| | @article{venkataramani-tcad06,
title = {Hardware Compilation of Application-Specific Memory Access
Interconnect},
author = {Venkataramani, Girish and Bjerregaard, Tobias and Chelcea,
Tiberiu and Goldstein, Seth Copen},
journal = {IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems},
year = {2006},
volume = {25},
number = {5},
pages = {756--771},
issn = {0278-0070},
abstract = {{A major obstacle to successful high-level synthesis
(HLS) of large-scale application-specified integrated circuit
systems is the presence of memory accesses to a shared-memory
subsystem. The latency to access memory is often not statically
predictable, which creates problems for scheduling operations
dependent on memory reads. More fundamental is that dependences
between accesses may not be statically provable (e.g., if the
specification language permits pointers), which introduces
memory-consistency problems. Addressing these issues with static
scheduling results in overly conservative circuits, and thus,
most state-of-the-art HLS tools limit memory systems to those
that have predictable latencies and limit programmers to
specifications that forbid arbitrary memory-reference patterns. A
new HLS framework for the synthesis and optimization of memory
accesses (SOMA) is presented. SOMA enables specifications to
include arbitrary memory references (e.g., pointers) and allows
the memory system to incorporate features that might cause the
latency of a memory access to vary dynamically. This results in
raising the level of abstraction in the input specification,
enabling faster design times. SOMA synthesizes a memory access
network (MAN) architecture that facilitates dynamic scheduling
and ordering of memory accesses. The paper describes a basic MAN
construction technique that illustrates how dynamic ordering
helps in efficiently maintaining memory consistency and how
dynamic scheduling helps alleviate the variable-latency problem.
Then, it is shown how static analysis of the access patterns can
be used to optimize the MAN. One optimization changes the MAN
interconnect topology to increase concurrence. A second
optimization reduces the synchronization overhead necessary to
maintain memory consistency. Postlayout experiments demonstrate
that SOMA's application-specific MAN construction significantly
improves power and performance for a range of benchmarks.}},
keywords = {Asychronous Circuits, Spatial
Computing,Phoenix,Network-on-a-chip},
url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-tcad06.pdf}
}
|
|
Leveraging Protocol Knowledge in Slack Matching | pdf bib abstract | |
Girish Venkataramani and Seth Copen Goldstein.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
November, 2006.
|
| hide Abstract | Stalls, due to mis-matches in communication rates, are a major performance obstacle in pipelined circuits. If the rate of data production is faster than the rate of consumption, the resulting design performs slower than when the communication rate is matched. This can be remedied by inserting pipeline buffers (to temporarily hold data), allowing the producer to proceed if the consumer is not ready to accept data. The problem of deciding which channels need these buffers (and how many) for an arbitrary communication profile is called the slack matching problem; the optimal solution to this problem has been shown to be NP-complete. In this paper, we present a heuristic that uses knowledge of the communication protocol to explicitly model these bottlenecks, and an iterative algorithm to progressively remove these bottlenecks by inserting buffers. We apply this algorithm to asynchronous circuits, and show that it naturally handles large designs with arbitrarily cyclic and acyclic topologies, which exhibit various types of control choice. The heuristic is efficient, achieving linear time complexity in practice, and produces solutions that (a) achieve up to 60% performance speedup on large media processing kernels, and (b) can either be verified to be optimal, or the approximation margin can be bounded. |
| | @inproceedings{venkataramani-iccad06,
title = {Leveraging Protocol Knowledge in Slack Matching},
author = {Venkataramani, Girish and Goldstein, Seth Copen},
booktitle = {IEEE/ACM International Conference on Computer-Aided
Design (ICCAD)},
year = {2006},
address = {San Jose, CA},
month = {November},
abstract = {{Stalls, due to mis-matches in communication rates, are
a major performance obstacle in pipelined circuits. If the rate
of data production is faster than the rate of consumption, the
resulting design performs slower than when the communication rate
is matched. This can be remedied by inserting pipeline buffers
(to temporarily hold data), allowing the producer to proceed if
the consumer is not ready to accept data. The problem of deciding
which channels need these buffers (and how many) for an arbitrary
communication profile is called the slack matching problem; the
optimal solution to this problem has been shown to be
NP-complete. \par In this paper, we present a heuristic that uses
knowledge of the communication protocol to explicitly model these
bottlenecks, and an iterative algorithm to progressively remove
these bottlenecks by inserting buffers. We apply this algorithm
to asynchronous circuits, and show that it naturally handles
large designs with arbitrarily cyclic and acyclic topologies,
which exhibit various types of control choice. The heuristic is
efficient, achieving linear time complexity in practice, and
produces solutions that (a) achieve up to 60\% performance
speedup on large media processing kernels, and (b) can either be
verified to be optimal, or the approximation margin can be
bounded. }},
keywords = {Asychronous Circuits, Spatial Computing, CAD, Global
Critical Path},
url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iccad06.pdf}
}
|
|
Brain in a Bottle | pdf bib | |
Seth Copen Goldstein.
In Wild and Crazy Ideas Session of ASPLOS,
October, 2006.
|
| @inproceedings{goldstein-waci06,
author = {Goldstein, Seth Copen},
title = {Brain in a Bottle},
booktitle = {Wild and Crazy Ideas Session of ASPLOS},
year = {2006},
month = {October},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-waci06.pdf},
keywords = {Brain, Parallel Computing, Self-Assembly}
}
|
|
Hierarchical Motion Planning for Self-reconfigurable Modular Robots | pdf bib | |
Preethi Srinivas Bhat, James Kuffner, Seth Copen Goldstein, and Siddhartha Srinivasa.
In 2006 IEEE/RSJ International Confernce on Intelligent Robots and Systems (IROS),
October, 2006.
|
| @inproceedings{bhat06,
author = {Bhat, Preethi Srinivas and Kuffner, James and Goldstein,
Seth Copen and Srinivasa, Siddhartha},
title = {Hierarchical Motion Planning for Self-reconfigurable
Modular Robots},
booktitle = {2006 IEEE/RSJ International Confernce on Intelligent
Robots and Systems (IROS)},
year = {2006},
month = {October},
keywords = {Claytronics, Planning, Modular Robotics},
url = {http://www.cs.cmu.edu/~seth/papers/bhat06.pdf}
}
|
|
Tartan: Evaluating Spatial Computation for Whole Program Execution | pdf bib abstract | |
Mahim Mishra, Timothy J Callahan, Tiberiu Chelcea, Girish Venkataramani, Mihai Budiu, and Seth Copen Goldstein.
In 12th ACM International Conference on Architecture Support for Programming Languages and Operating Systems (ASPLOS),
pages 163–174, October, 2006.
|
| hide Abstract | Spatial Computing (SC) has been shown to be an energy-efficient model for implementing program kernels. In this paper we explore the feasibility of using SC for more than small kernels. To this end, we evaluate the performance and energy efficiency of entire applications on Tartan, a general-purpose architecture which integrates a reconfigurable fabric (RF) with a superscalar core. Our compiler automatically partitions and compiles an application into an instruction stream for the core and a configuration for the RF. We use a detailed simulator to capture both timing and energy numbers for all parts of the system. Our results indicate that a hierarchical RF architecture, designed around a scalable interconnect, is instrumental in harnessing the benefits of spatial computation. The interconnect uses static configuration and routing at the lower levels and a packet-switched, dynamically-routed network at the top level. Tartan is most energy-efficient when almost all of the application is mapped to the RF, indicating the need for the RF to support most general-purpose programming constructs. Our initial investigation reveals that such a system can provide, on average, an order of magnitude improvement in energy-delay compared to an aggressive superscalar core on single-threaded workloads. |
| | @inproceedings{mahim-asplos06,
title = {Tartan: Evaluating Spatial Computation for Whole Program
Execution},
author = {Mishra, Mahim and Callahan, Timothy J and Chelcea, Tiberiu
and Venkataramani, Girish and Budiu, Mihai and Goldstein, Seth
Copen},
booktitle = {12th ACM International Conference on Architecture
Support for Programming Languages and Operating Systems
(ASPLOS)},
year = {2006},
pages = {163--174},
address = {San Jose, CA},
month = {October},
abstract = {Spatial Computing (SC) has been shown to be an
energy-efficient model for implementing program kernels. In this
paper we explore the feasibility of using SC for more than small
kernels. To this end, we evaluate the performance and energy
efficiency of entire applications on Tartan, a general-purpose
architecture which integrates a reconfigurable fabric (RF) with a
superscalar core. Our compiler automatically partitions and
compiles an application into an instruction stream for the core
and a configuration for the RF. We use a detailed simulator to
capture both timing and energy numbers for all parts of the
system. \par Our results indicate that a hierarchical RF
architecture, designed around a scalable interconnect, is
instrumental in harnessing the benefits of spatial computation.
The interconnect uses static configuration and routing at the
lower levels and a packet-switched, dynamically-routed network at
the top level. Tartan is most energy-efficient when almost all of
the application is mapped to the RF, indicating the need for the
RF to support most general-purpose programming constructs. Our
initial investigation reveals that such a system can provide, on
average, an order of magnitude improvement in energy-delay
compared to an aggressive superscalar core on single-threaded
workloads.},
keywords = {Asychronous Circuits, Spatial Computing, Reconfigurable
Computing,Phoenix, Tartan},
url = {http://www.cs.cmu.edu/~seth/papers/mahim-asplos06.pdf}
}
|
|
Distributed Watchpoints: Debugging Very Large Ensembles of Robots | pdf bib abstract talk | |
Michael De Rosa, Seth Copen Goldstein, Peter Lee, Jason D. Campbell, and Padmanabhan Pillai.
In Robotics: Science and Systems Workshop on Self-Reconfigurable Modular Robots,
August, 2006.
|
| | | |
|
Modeling the Global Critical Path in Concurrent Systems | pdf bib abstract | |
Girish Venkataramani, Tiberiu Chelcea, Mihai Budiu, and Seth Copen Goldstein.
Carnegie Mellon University Technical Report No. CMU-CS-06-144,
August, 2006.
|
| hide Abstract | We show how the global critical path can be used as a practical tool for understanding, optimizing and summarizing the behavior of highly concurrent self-timed circuits. Traditionally, critical path analysis has been applied to DAGs, and thus was constrained to combinatorial sub-circuits. We formally define the global critical path (GCP) and show how it can be constructed using only local information that is automatically derived directly from the circuit. We introduce a form of Production Rules, which can accurately determine the GCP for a given input vector, even for modules which exhibit choice and early termination. The GCP provides valuable insight into the control behavior of the application, which help in formulating new optimizations and re-formulating existing ones to use the GCP knowledge. We have constructed a fully automated framework for GCP detection and analysis, and have incorporated this framework into a high-level synthesis tool-chain. We demonstrate the effectiveness of the GCP framework by re-formulating two traditional CAD optimizations to use the GCP, yielding efficient algorithms which improve circuit power (by up to 9%) and performance (by up to 60%) in our experiments. |
| | @techreport{venkataramani-tr06,
author = {Venkataramani, Girish and Chelcea, Tiberiu and Budiu,
Mihai and Goldstein, Seth Copen},
title = {Modeling the Global Critical Path in Concurrent Systems},
institution = {Carnegie Mellon University},
year = {2006},
number = {CMU-CS-06-144},
month = {August},
abstract = {We show how the global critical path can be used as a
practical tool for understanding, optimizing and summarizing the
behavior of highly concurrent self-timed circuits. Traditionally,
critical path analysis has been applied to DAGs, and thus was
constrained to combinatorial sub-circuits. We formally define the
global critical path (GCP) and show how it can be constructed
using only local information that is automatically derived
directly from the circuit. We introduce a form of Production
Rules, which can accurately determine the GCP for a given input
vector, even for modules which exhibit choice and early
termination. \par The GCP provides valuable insight into the
control behavior of the application, which help in formulating
new optimizations and re-formulating existing ones to use the GCP
knowledge. We have constructed a fully automated framework for
GCP detection and analysis, and have incorporated this framework
into a high-level synthesis tool-chain. We demonstrate the
effectiveness of the GCP framework by re-formulating two
traditional CAD optimizations to use the GCP, yielding efficient
algorithms which improve circuit power (by up to 9\%) and
performance (by up to 60\%) in our experiments.},
keywords = {Asychronous Circuits, Spatial Computing,CAD, Global
Critical Path},
url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-tr06.pdf}
}
|
|
Scalable Shape Sculpting via Hole Motion: Motion Planning in Lattice-Constrained Module Robots | pdf bib abstract | |
Michael De Rosa, Seth Copen Goldstein, Peter Lee, Jason D. Campbell, and Padmanabhan Pillai.
In Proceedings of the 2006 IEEE International Conference on Robotics and Automation (ICRA '06),
May, 2006.
|
| hide Abstract | We describe a novel shape formation algorithm for ensembles of 2-dimensional lattice-arrayed modular robots, based on the manipulation of regularly shaped voids within the lattice (“holes”). The algorithm is massively parallel and fully distributed. Constructing a goal shape requires time propor- tional only to the complexity of the desired target geometry. Construction of the shape by the modules requires no global communication nor broadcast floods after distribution of the target shape. Results in simulation show 97.3% shape compliance in ensembles of approximately 60,000 modules, and we believe that the algorithm will generalize to 3D and scale to handle millions of modules. |
| | @inproceedings{derosa-icra06,
author = {De~Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
and Campbell, Jason D. and Pillai, Padmanabhan},
title = {Scalable Shape Sculpting via Hole Motion: Motion Planning
in Lattice-Constrained Module Robots},
month = {May},
booktitle = {Proceedings of the 2006 {IEEE} International Conference
on Robotics and Automation (ICRA '06)},
year = {2006},
keywords = {Claytronics, Programmable Matter, Planning, Modular
Robotics},
url = {http://www.cs.cmu.edu/~seth/papers/derosa-icra06.pdf},
abstract = {We describe a novel shape formation algorithm for
ensembles of 2-dimensional lattice-arrayed modular robots, based
on the manipulation of regularly shaped voids within the lattice
(``holes''). The algorithm is massively parallel and fully
distributed. Constructing a goal shape requires time propor-
tional only to the complexity of the desired target geometry.
Construction of the shape by the modules requires no global
communication nor broadcast floods after distribution of the
target shape. Results in simulation show 97.3\% shape compliance
in ensembles of approximately 60,000 modules, and we believe that
the algorithm will generalize to 3D and scale to handle millions
of modules.}
}
|
|
Ultralight Modular Robotic Building blocks for the Rapid Deployment of Planetary Outposts | pdf bib | |
Mustafa Emre Karagozler, Brian Kirby, W.J. Lee, Eugene Marinelli, T.C. Ng, Michael Weller, and Seth Copen Goldstein.
In Revolutionary Aerospace Systems Concepts Academic Linkage (RASC-AL) Forum 2006,
May, 2006.
|
| @inproceedings{karagozler-rascal06,
title = {Ultralight Modular Robotic Building blocks for the Rapid
Deployment of Planetary Outposts},
booktitle = {Revolutionary Aerospace Systems Concepts Academic
Linkage (RASC-AL) Forum 2006},
author = {Karagozler, Mustafa Emre and Kirby, Brian and Lee, W.J.
and Marinelli, Eugene and Ng, T.C. and Weller, Michael and
Goldstein, Seth Copen},
year = {2006},
month = {May},
address = {Cape Canaveral, FL},
url = {http://www.cs.cmu.edu/~seth/papers/karagozler-rascal06.pdf},
keywords = {Claytronics,Modular Robotics,Robotics}
}
|
|
An Analysis of Graph Coloring Register Allocation | pdf bib abstract | |
David Ryan Koes and Seth Copen Goldstein.
Carnegie Mellon University Technical Report No. CMU-CS-06-111,
pages 10, March, 2006.
|
| hide Abstract | Graph coloring is the de facto standard technique for register allocation within a compiler. In this paper we examine the importance of the quality of the coloring algorithm and various extensions of the basic graph coloring technique by replacing the coloring phase of the GNU compiler’s register allocator with an optimal coloring algorithm. We then extend this optimal algorithm to incorporate various extensions such as coalescing and preferential register assignment. We find that using an optimal coloring algorithm has surprisingly little benefit and empirically demonstrate the benefit of the various extensions. |
| | @techreport{koes-tr06,
author = {Koes, David Ryan and Goldstein, Seth Copen},
title = {An Analysis of Graph Coloring Register Allocation},
institution = {Carnegie Mellon University},
year = {2006},
number = {CMU-CS-06-111},
pages = {10},
month = {March},
url = {http://www.cs.cmu.edu/~seth/papers/koes-tr06.pdf},
abstract = {Graph coloring is the de facto standard technique for
register allocation within a compiler. In this paper we examine
the importance of the quality of the coloring algorithm and
various extensions of the basic graph coloring technique by
replacing the coloring phase of the GNU compiler's register
allocator with an optimal coloring algorithm. We then extend this
optimal algorithm to incorporate various extensions such as
coalescing and preferential register assignment. We find that
using an optimal coloring algorithm has surprisingly little
benefit and empirically demonstrate the benefit of the various
extensions.},
keywords = {Compilers:Register Allocation}
}
|
2005 |
Demo Abstract: Claytronics---highly scalable communications, sensing, and actuation networks. | pdf bib | |
Burak Aksak, Preethi Srinivas Bhat, Jason D. Campbell, Michael De Rosa, Stanislav Funiak, Phillip B. Gibbons, Seth Copen Goldstein, Carlos Guestrin, Ashish Gupta, Casey Helfrich, James F. Hoburg, Brian Kirby, James Kuffner, Peter Lee, Todd C. Mowry, Padmanabhan Pillai, Ram Ravichandran, Benjamin D. Rister, Srinivasan Seshan, Metin Sitti, and Haifeng Yu.
In Proceedings of the 3rd international conference on Embedded networked sensor systems (SenSys),
pages 299, 2005.
|
| @inproceedings{aksak-sensys05,
author = {Aksak, Burak and Bhat, Preethi Srinivas and Campbell,
Jason D. and De~Rosa, Michael and Funiak, Stanislav and Gibbons,
Phillip B. and Goldstein, Seth Copen and Guestrin, Carlos and
Gupta, Ashish and Helfrich, Casey and Hoburg, James F. and Kirby,
Brian and Kuffner, James and Lee, Peter and Mowry, Todd C. and
Pillai, Padmanabhan and Ravichandran, Ram and Rister, Benjamin D.
and Seshan, Srinivasan and Sitti, Metin and Yu, Haifeng},
title = {Demo Abstract: Claytronics---highly scalable
communications, sensing, and actuation networks.},
booktitle = {Proceedings of the 3rd international conference on
Embedded networked sensor systems (SenSys)},
year = {2005},
pages = {299},
url = {http://www.cs.cmu.edu/~seth/papers/aksak-sensys05.pdf},
doi = {http://doi.acm.org/10.1145/1098918.1098964},
keywords = {Claytronics, Programmable Matter}
}
|
|
The impact of the nanoscale on computing systems | pdf bib | |
Seth Copen Goldstein.
In IEEE/ACM International Conference on Computer-Aided Design, 2005 (ICCAD 2005),
pages 655–661, November, 2005.
|
| @inproceedings{goldstein-iccad05,
title = {The impact of the nanoscale on computing systems},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-iccad05.pdf},
booktitle = {IEEE/ACM International Conference on Computer-Aided
Design, 2005 (ICCAD 2005)},
author = {Goldstein, Seth Copen},
year = {2005},
pages = {655-661},
address = {San Jose, CA},
month = {November},
keywords = {Electronic Nanotechnology,molecular electronics}
}
|
|
The Ensemble Principle | pdf bib | |
Seth Copen Goldstein, Todd C. Mowry, Jason D. Campbell, Peter Lee, Padmanabhan Pillai, James F. Hoburg, Phillip B. Gibbons, Carlos Guestrin, James Kuffner, Brian Kirby, Benjamin D. Rister, Michael De Rosa, Stanislav Funiak, Burak Aksak, and Rahul Sukthankar.
In 13th Foresight Conference of Advanced Nanotechnogy,
October, 2005.
|
| @inproceedings{goldstein05,
author = {Goldstein, Seth Copen and Mowry, Todd C. and Campbell,
Jason D. and Lee, Peter and Pillai, Padmanabhan and Hoburg, James
F. and Gibbons, Phillip B. and Guestrin, Carlos and Kuffner,
James and Kirby, Brian and Rister, Benjamin D. and De~Rosa,
Michael and Funiak, Stanislav and Aksak, Burak and Sukthankar,
Rahul},
title = {The Ensemble Principle},
booktitle = {13th Foresight Conference of Advanced Nanotechnogy},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein05.pdf},
year = {2005},
month = {October},
address = {San Francisco, CA},
keywords = {Claytronics, Robotics}
}
|
|
SOMA: A Tool for Synthesizing and Optimizing Memory Accesses in ASICs | pdf bib abstract | |
Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, and Seth Copen Goldstein.
In IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS),
pages 231–236, September, 2005.
|
| hide Abstract | Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance. |
| | @inproceedings{venkataramani-isss05,
title = {SOMA: A Tool for Synthesizing and Optimizing Memory
Accesses in ASICs},
author = {Venkataramani, Girish and Bjerregaard, Tobias and Chelcea,
Tiberiu and Goldstein, Seth Copen},
booktitle = {IEEE/ACM/IFIP International Conference on
Hardware/Software Codesign and System Synthesis (CODES-ISSS)},
year = {2005},
isbn = {1-59593-161-9},
pages = {231-236},
address = {Jersey City, NJ, USA},
month = {September},
abstract = {Arbitrary memory dependencies and variable latency
memory systems are major obstacles to the synthesis of
large-scale ASIC systems in high-level synthesis. This paper
presents SOMA, a synthesis framework for constructing Memory
Access Network (MAN) architectures that inherently enforce memory
consistency in the presence of dynamic memory access
dependencies. A fundamental bottleneck in any such network is
arbitrating between concurrent accesses to a shared memory
resource. To alleviate this bottleneck, SOMA uses an
application-specific concurrency analysis technique to predict
the dynamic memory parallelism profile of the application. This
is then used to customize the MAN architecture. Depending on the
parallelism profile, the MAN may be optimized for latency,
throughput or both. The optimized MAN is automatically
synthesized into gate-level structural Verilog using a flexible
library of network building blocks. SOMA has been successfully
integrated into an automated C-to-hardware synthesis flow, which
generates standard cell circuits from unrestricted ANSI-C
programs. Post-layout experiments demonstrate that application
specific MAN construction significantly improves power and
performance.},
keywords = {Asychronous Circuits, Spatial Computing,Phoenix,
CAD,Compilers:Memory Optimizations},
url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-isss05.pdf}
}
|
|
The Robot is the Tether: Active, Adaptive Power Routing for Modular Robots With Unary Inter-robot Connectors | pdf bib | |
Jason D. Campbell, Padmanabhan Pillai, and Seth Copen Goldstein.
In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS 2005),
pages 4108–15, August, 2005.
|
| @inproceedings{campbell05,
author = {Campbell, Jason D. and Pillai, Padmanabhan and Goldstein,
Seth Copen},
title = {The Robot is the Tether: Active, Adaptive Power Routing for
Modular Robots With Unary Inter-robot Connectors},
booktitle = {IEEE/RSJ International Conference on Intelligent Robots
and Systems (IROS 2005)},
pages = {4108--15},
year = {2005},
address = {Edmonton, Alberta Canada},
month = {August},
keywords = {Claytronics, Robotics},
url = {http://www.cs.cmu.edu/~seth/papers/campbell05.pdf}
}
|
|
Catoms: Moving Robots Without Moving Parts | pdf bib | |
Brian Kirby, Jason D. Campbell, Burak Aksak, Padmanabhan Pillai, James F. Hoburg, Todd C. Mowry, and Seth Copen Goldstein.
In AAAI (Robot Exhibition),
pages 1730–1, July, 2005.
|
| @inproceedings{kirby-aaai05,
author = {Kirby, Brian and Campbell, Jason D. and Aksak, Burak and
Pillai, Padmanabhan and Hoburg, James F. and Mowry, Todd C. and
Goldstein, Seth Copen},
title = {Catoms: Moving Robots Without Moving Parts},
url = {http://www.cs.cmu.edu/~seth/papers/kirby-aaai05.pdf},
booktitle = {AAAI (Robot Exhibition)},
pages = {1730--1},
year = {2005},
month = {July},
address = {Pittsburgh, PA},
keywords = {Claytronics, Robotics}
}
|
|
HLS Support for Unconstrained Memory Accesses | pdf bib abstract | |
Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein.
In IEEE 14th International Workshop on Logic Synthesis (IWLS),
June, 2005.
|
| hide Abstract | A major obstacle in high-level synthesis (HLS) of large-scale ASIC systems is memory access patterns. Typically, most state-of-the-art HLS tools impose constraints on the memory references in the source application, requiring them to exhibit predictable access patterns, and/or requiring dependencies between them to be statically determinable. This paper addresses the HLS problem when such constraints are relaxed. We present an analysis infrastructure that can be used within any HLS toolflow for synthesizing circuits from high-level abstractions, such as ANSI-C, where no assumptions can be made about memory access latencies, and where dependencies between memory references can only be disambiguated dynamically at runtime (pointer aliasing). We start by describing a generic framework to build a dependence-aware, fully distributed, although often conservative, memory-access network (MAN) for a given memory-dependence graph. Then, we propose a suite of optimizations to customize the MAN for the given specification. All these techniques guarantee memory coherency. Experimental results on Mediabench benchmarks, show that such an approach succeeds in maintaining high levels of parallelism, while ensuring memory coherency. The optimizations succeed in lowering the synchronization overhead by as much as 4x. |
| | @inproceedings{venkataramani-iwls05,
title = {{HLS} Support for Unconstrained Memory Accesses},
author = {Venkataramani, Girish and Chelcea, Tiberiu and Goldstein,
Seth Copen},
booktitle = {IEEE 14th International Workshop on Logic Synthesis
(IWLS)},
year = {2005},
address = {Lake Arrowhead, CA},
month = {June},
abstract = {A major obstacle in high-level synthesis (HLS) of
large-scale ASIC systems is memory access patterns. Typically,
most state-of-the-art HLS tools impose constraints on the memory
references in the source application, requiring them to exhibit
predictable access patterns, and/or requiring dependencies
between them to be statically determinable. This paper addresses
the HLS problem when such constraints are relaxed. We present an
analysis infrastructure that can be used within any HLS toolflow
for synthesizing circuits from high-level abstractions, such as
ANSI-C, where no assumptions can be made about memory access
latencies, and where dependencies between memory references can
only be disambiguated dynamically at runtime (pointer aliasing).
We start by describing a generic framework to build a
dependence-aware, fully distributed, although often conservative,
memory-access network (MAN) for a given memory-dependence graph.
Then, we propose a suite of optimizations to customize the MAN
for the given specification. All these techniques guarantee
memory coherency. Experimental results on Mediabench benchmarks,
show that such an approach succeeds in maintaining high levels of
parallelism, while ensuring memory coherency. The optimizations
succeed in lowering the synchronization overhead by as much as
4x.},
keywords = {Asychronous Circuits, Spatial Computing,Phoenix},
url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iwls05.pdf}
}
|
|
Programmable Matter | pdf bib | |
Seth Copen Goldstein, Jason D. Campbell, and Todd C. Mowry.
IEEE Computer,
38(6):99–101,June, 2005.
|
| @article{goldstein-computer05,
author = {Goldstein, Seth Copen and Campbell, Jason D. and Mowry,
Todd C.},
title = {Programmable Matter},
journal = {IEEE Computer},
volume = {38},
number = {6},
pages = {99--101},
year = {2005},
month = {June},
keywords = {Claytronics, Programmable Matter},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-computer05.pdf}
}
|
|
Adding Faster with Application Specific Early Termination | pdf bib abstract | |
David Ryan Koes, Tiberiu Chelcea, Charles Onyeama, and Seth Copen Goldstein.
Carnegie Mellon University Technical Report No. CMU-CS-05-101,
pages 20, May, 2005.
|
| hide Abstract | This paper presents a methodology for improving the speed of high-speed adders. As a starting point, a previously proposed method, called speculative completion, is used in which fast- terminating additions are automatically detected. Unlike the previous design, the method proposed in this paper is able to adapt dynamically to (1) application-specific behavior and (2) to adder- specific behavior, resulting in a higher detection rate of fast additions and, consequently, a faster average-case speed for addition. Our experimental results show detection rates of over 99%, and adder average-case speed improvements of up to 14.%. |
| | @techreport{koes-tr05,
author = {Koes, David Ryan and Chelcea, Tiberiu and Onyeama, Charles
and Goldstein, Seth Copen},
title = {Adding Faster with Application Specific Early Termination},
institution = {Carnegie Mellon University},
year = {2005},
number = {CMU-CS-05-101},
pages = {20},
month = {May},
url = {http://www.cs.cmu.edu/~seth/papers/koes-tr05.pdf},
abstract = {This paper presents a methodology for improving the
speed of high-speed adders. As a starting point, a previously
proposed method, called speculative completion, is used in which
fast- terminating additions are automatically detected. Unlike
the previous design, the method proposed in this paper is able to
adapt dynamically to (1) application-specific behavior and (2) to
adder- specific behavior, resulting in a higher detection rate of
fast additions and, consequently, a faster average-case speed for
addition. Our experimental results show detection rates of over
99\%, and adder average-case speed improvements of up to 14.\%.},
keywords = {Asychronous Circuits}
}
|
|
Why area might reduce power in nanoscale CMOS | pdf bib abstract | |
Paul Beckett and Seth Copen Goldstein.
In IEEE International Symposium on Circuits and Systems, 2005, (ISCAS 2005),
volume 3, pages 2329–2332,May, 2005.
|
| hide Abstract | In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reduction in VDD which results in a reduction in power. Under a scaling regime which allows threshold voltage to increase as VDD decreases we find that dynamic and subthreshold power loss in CMOS exhibit a dependence on area proportional to A^((\sigma^-3)/\sigma) while gate leakage power proportional to A^((\sigma^-6)/\sigma) and short circuit power A^((\sigma^-6)/\sigma). Thus, with the large number of devices at our disposal we can exploit techniques such as spatial computing--tailoring the program directly to the hardware--to overcome the negative effects of scaling. The value of s describes the effectiveness of the technique for a particular circuit and/or algorithm--for circuits that exhibit a value of \sigma <= 3, power will be a constant or reducing function of area. We briefly speculate on how \sigma might be influenced by a move to nanoscale technology. |
| | @inproceedings{beckett-iscas05,
title = {Why area might reduce power in nanoscale CMOS},
url = {http://www.cs.cmu.edu/~seth/papers/beckett-iscas05.pdf},
booktitle = {IEEE International Symposium on Circuits and Systems,
2005, (ISCAS 2005)},
author = {Beckett, Paul and Goldstein, Seth Copen},
year = {2005},
pages = {2329-2332},
volume = {3},
month = {May},
address = {Kobe, Japan},
abstract = {In this paper we explore the relationship between power
and area. By exploiting parallelism (and thus using more area)
one can reduce the switching frequency allowing a reduction in
VDD which results in a reduction in power. Under a scaling regime
which allows threshold voltage to increase as VDD decreases we
find that dynamic and subthreshold power loss in CMOS exhibit a
dependence on area proportional to A^((\sigma^-3)/\sigma) while
gate leakage power proportional to A^((\sigma^-6)/\sigma) and
short circuit power A^((\sigma^-6)/\sigma). Thus, with the large
number of devices at our disposal we can exploit techniques such
as spatial computing--tailoring the program directly to the
hardware--to overcome the negative effects of scaling. The value
of s describes the effectiveness of the technique for a
particular circuit and/or algorithm--for circuits that exhibit a
value of \sigma <= 3, power will be a constant or reducing
function of area. We briefly speculate on how \sigma might be
influenced by a move to nanoscale technology.},
keywords = {Electronic Nanotechnology,Power,Energy}
}
|
|
2029 The 3-D Fax Machine Brings Back the House Call | pdf bib | |
Seth Copen Goldstein.
In Headline from the Future, Popular Science Magazine,
pages 34, March, 2005.
|
| @misc{goldstein-popsci05,
title = {2029 The 3-D Fax Machine Brings Back the House Call},
howpublished = {Headline from the Future, Popular Science Magazine},
author = {Goldstein, Seth Copen},
year = {2005},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-popsci05.pdf},
month = {March},
pages = {34},
keywords = {Claytronics}
}
|
|
A Progressive Register Allocator for Irregular Architectures | pdf bib abstract | |
David Ryan Koes and Seth Copen Goldstein.
In Proceedings of the International Symposium on Code Generation and Optimization (CGO'05),
pages 269–280, March, 2005.
|
| hide Abstract | Register allocation is one of the most important optimizations a compiler performs. Conventional graph-coloring based register allocators are fast and do well on regular, RISC-like, architectures, but perform poorly on irregular, CISC-like, architectures with few registers and non-orthogonal instruction sets. At the other extreme, optimal register allocators based on integer linear programming are capable of fully modeling and exploiting the peculiarities of irregular architectures but do not scale well. We introduce the idea of a progressive allocator which finds an initial allocation of quality comparable to a conventional allocator, but as more time is allowed for computation the quality of the allocation approaches optimal. This paper presents a progressive register allocator which uses a multi-commodity network flow model to elegantly represent the intricacies of irregular architectures. We evaluate our allocator substituted for gcc’s local register allocation pass. |
| | @inproceedings{koes-cgo05,
author = {Koes, David Ryan and Goldstein, Seth Copen},
title = {A Progressive Register Allocator for Irregular
Architectures},
booktitle = {Proceedings of the International Symposium on Code
Generation and Optimization {(CGO'05)}},
month = {March},
year = {2005},
isbn = {0-7695-2298-X},
pages = {269--280},
doi = {http://dx.doi.org/10.1109/CGO.2005.4},
publisher = {IEEE Computer Society},
address = {Washington, DC},
abstract = {Register allocation is one of the most important
optimizations a compiler performs. Conventional graph-coloring
based register allocators are fast and do well on regular,
RISC-like, architectures, but perform poorly on irregular,
CISC-like, architectures with few registers and non-orthogonal
instruction sets. At the other extreme, optimal register
allocators based on integer linear programming are capable of
fully modeling and exploiting the peculiarities of irregular
architectures but do not scale well. We introduce the idea of a
\textit{progressive allocator} which finds an initial allocation
of quality comparable to a conventional allocator, but as more
time is allowed for computation the quality of the allocation
approaches optimal. This paper presents a progressive register
allocator which uses a multi-commodity network flow model to
elegantly represent the intricacies of irregular architectures.
We evaluate our allocator substituted for {\tt gcc}'s local
register allocation pass.},
keywords = {Compilers:Register Allocation},
url = {http://www.cs.cmu.edu/~seth/papers/koes-cgo05.pdf}
}
|
|
Dataflow: A Complement to Superscalar | pdf bib abstract | |
Mihai Budiu, Pedro V. Artigas, and Seth Copen Goldstein.
In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS),
pages 177–186, March, 2005.
|
| hide Abstract | There has been a resurgence of interest in dataflow architectures, because of their potential for exploiting parallelism with low overhead. In this paper we analyze the performance of a class of static dataflow machines on integer media and control-intensive programs and we explain why a dataflow machine, even with unlimited resources, does not always outperform a superscalar processor on general-purpose codes, under the assumption that both machines take the same time to execute basic operations. We compare a program-specific dataflow machine with unlimited parallelism to a superscalar processor running the same program. While the dataflow machines provide very good performance on most data-parallel programs, we show that the dataflow machine cannot always take advantage of the available parallelism. Using the dynamic critical path we investigate the mechanisms used by superscalar processors to provide a performance advantage and their impact on a dataflow model. |
| | @inproceedings{budiu-ispass05,
author = {Budiu, Mihai and Artigas, Pedro V. and Goldstein, Seth
Copen},
title = {Dataflow: A Complement to Superscalar},
booktitle = {IEEE International Symposium on Performance Analysis of
Systems and Software (ISPASS)},
month = {March},
year = {2005},
pages = {177--186},
address = {Austin, TX},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-ispass05.pdf},
abstract = {There has been a resurgence of interest in dataflow
architectures, because of their potential for exploiting
parallelism with low overhead. In this paper we analyze the
performance of a class of static dataflow machines on integer
media and control-intensive programs and we explain why a
dataflow machine, even with unlimited resources, does not always
outperform a superscalar processor on general-purpose codes,
under the assumption that both machines take the same time to
execute basic operations. We compare a program-specific dataflow
machine with unlimited parallelism to a superscalar processor
running the same program. While the dataflow machines provide
very good performance on most data-parallel programs, we show
that the dataflow machine cannot always take advantage of the
available parallelism. Using the dynamic critical path we
investigate the mechanisms used by superscalar processors to
provide a performance advantage and their impact on a dataflow
model.},
confweb = {http://www.ispass.org/ispass2005},
keywords = {Spatial Computing,Phoenix}
}
|
|
Inter-iteration Scalar Replacement in the Presence of Conditional Control Flow | pdf bib | |
Mihai Budiu and Seth Copen Goldstein.
In 3rd Workshop on Optimizations for DSO and Embedded Systems,
March, 2005.
Also appeared as CMU CS Technical Report, CMU-CS-04-103.
|
| @inproceedings{budiu-odes05,
title = {Inter-iteration Scalar Replacement in the Presence of
Conditional Control Flow},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-odes05.pdf},
booktitle = {3rd Workshop on Optimizations for DSO and Embedded
Systems},
author = {Budiu, Mihai and Goldstein, Seth Copen},
year = {2005},
address = {San Jose, CA},
month = {March},
also = {CMU CS Technical Report, CMU-CS-04-103},
keywords = {Phoenix,Compilers:Loop Optimizations,Compilers:Scalar
Replacement}
}
|
|
Nonphotolithographic Nanoscale Memory Density Prospects | pdf bib abstract | |
Andre DeHon, Seth Copen Goldstein, Phil Kuekes, and Patrick Lincoln.
IEEE Transactions on Nanotechnology,
volume 4, pages 215–228,March, 2005.
|
| hide Abstract | Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations. |
| | @article{lincoln-tnano05,
title = {Nonphotolithographic Nanoscale Memory Density Prospects},
abstract = {Technologies are now emerging to construct
molecular-scale electronic wires and switches using bottom-up
self-assembly. This opens the possibility of constructing
nanoscale circuits and memories where active devices are just a
few nanometers square and wire pitches may be on the order of ten
nanometers. The features can be defined at this scale without
using photolithography. The available assembly techniques have
relatively high defect rates compared to conventional
lithographic integrated circuits and can only produce very
regular structures. Nonetheless, with proper memory organization,
it is reasonable to expect these technologies to provide memory
densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
power requirements under 0.6 W/Tb/s for random read operations.},
url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
journal = {IEEE Transactions on Nanotechnology},
author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
and Lincoln, Patrick},
year = {2005},
month = {March},
volume = {4},
issue = {2},
pages = {215-228},
keywords = {Fault and Defect Tolerance, electronic nanotechnology,
memory density, memory organization, molecular electronics},
doi = {10.1109/TNANO.2004.837849}
}
|
2004 |
Defect Tolerance at the End of the Roadmap | bib | |
Mahim Mishra and Seth Copen Goldstein.
In Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation,
2004.
|
| @incollection{mishra-nqmc04,
title = {Defect Tolerance at the End of the Roadmap},
booktitle = {Nano, Quantum and Molecular Computing: Implications to
High Level Design and Validation},
author = {Mishra, Mahim and Goldstein, Seth Copen},
year = {2004},
editor = {Sandeep K. Shukla and R. Iris Bahar},
publisher = {Kluwer Academic Publishers},
isbn = {1-4020-80670},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Reconfigurable Computing,Phoenix,molecular electronics}
}
|
|
Claytronics: A scalable basis for future robots | pdf bib | |
Seth Copen Goldstein and Todd C. Mowry.
In RoboSphere 2004,
November, 2004.
|
| @inproceedings{goldstein-robosphere04,
author = {Goldstein, Seth Copen and Mowry, Todd C.},
title = {Claytronics: A scalable basis for future robots},
booktitle = {RoboSphere 2004},
address = {Moffett Field, CA},
month = {November},
year = {2004},
keywords = {Claytronics, Robotics},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-robosphere04.pdf}
}
|
|
Claytronics: An Instance of Programmable Matter | pdf bib abstract | |
Seth Copen Goldstein and Todd C. Mowry.
In Wild and Crazy Ideas Session of ASPLOS,
October, 2004.
|
| hide Abstract | Programmable matter refers to a technology that will allow one to
control and manipulate three-dimensional physical artifacts (similar
to how we already control and manipulate two-dimensional images with computer graphics). In other words, programmable matter will allow us
to take a (big) step beyond virtual reality, to synthetic reality, an
environment in which all the objects in a user’s environment (including the ones inserted by the computer) are physically realized.
Note that the idea is not to transport objects nor is it to recreate an objects chemical composition, but rather to create a physical artifact that will mimic the shape, movement, visual appearance, sound, and tactile qualities of the original object. |
| | @inproceedings{goldstein-waci04,
author = {Goldstein, Seth Copen and Mowry, Todd C.},
title = {Claytronics: An Instance of Programmable Matter},
booktitle = {Wild and Crazy Ideas Session of ASPLOS},
year = {2004},
month = {October},
address = {Boston, MA},
keywords = {Claytronics},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-waci04.pdf},
abstract = {Programmable matter refers to a technology that will
allow one to control and manipulate three-dimensional physical
artifacts (similar to how we already control and manipulate
two-dimensional images with computer graphics). In other words,
programmable matter will allow us to take a (big) step beyond
virtual reality, to synthetic reality, an environment in which
all the objects in a user's environment (including the ones
inserted by the computer) are physically realized. Note that the
idea is not to transport objects nor is it to recreate an objects
chemical composition, but rather to create a physical artifact
that will mimic the shape, movement, visual appearance, sound,
and tactile qualities of the original object.}
}
|
|
Spatial Computation | pdf bib abstract | |
Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein.
In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS),
pages 14–26, October, 2004.
|
| hide Abstract | This paper describes a computer architecture that relies on the direct translation of high-level language programs into Spatial Computation (SC) hardware structures. SC program implementations are completely distributed, without any centralized control. SC circuits are optimized for wires at the expense of computation units. In this paper we investigate a particular implementation SC structures called ASH (Application-Specific Hardware). Under the assumption that computation is cheaper than communication, ASH replicates computation units to simplify interconnect, building a system which uses very simple, completely dedicated communication channels. As a consequence, communication on the datapath never requires arbitration; the only arbitration required is for accessing memory. ASH relies on very simple hardware primitives, using no associative structures, no multiported register files, no scheduling logic, no broadcast, and no clocks. As a consequence, ASH hardware is fast and extremely power efficient. In this work we demonstrate three features of ASH: (1) that such architectures can be built by automatic compilation of C programs, (2) that distributed computation is in some respects fundamentally different from monolithic superscalar processors and (3) that ASIC implementations of ASH use 3 orders of magnitude less energy compared to high-end superscalar processors, while being within a factor of two in performance. |
| | @inproceedings{budiu-asplos04,
author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
Tiberiu and Goldstein, Seth Copen},
title = {Spatial Computation},
booktitle = {International Conference on Architectural Support for
Programming Languages and Operating Systems (ASPLOS)},
pages = {14--26},
month = {October},
address = {Boston, MA},
year = {2004},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-asplos04.pdf},
abstract = {This paper describes a computer architecture that relies
on the direct translation of high-level language programs into
{\em Spatial Computation} (SC) hardware structures. SC program
implementations are completely distributed, without any
centralized control. SC circuits are optimized for {\em wires} at
the expense of computation units. \par In this paper we
investigate a particular implementation SC structures called ASH
(Application-Specific Hardware). Under the assumption that
computation is cheaper than communication, ASH replicates
computation units to simplify interconnect, building a system
which uses very simple, completely dedicated communication
channels. As a consequence, communication on the datapath never
requires arbitration; the only arbitration required is for
accessing memory. ASH relies on very simple hardware primitives,
using no associative structures, no multiported register files,
no scheduling logic, no broadcast, and no clocks. As a
consequence, ASH hardware is fast and extremely power efficient.
\par In this work we demonstrate three features of ASH: (1) that
such architectures can be built by automatic compilation of C
programs, (2) that distributed computation is in some respects
fundamentally different from monolithic superscalar processors
and (3) that ASIC implementations of ASH use 3 orders of
magnitude less energy compared to high-end superscalar
processors, while being within a factor of two in performance.},
keywords = {Asychronous Circuits, Spatial Computing,Phoenix}
}
|
|
Methods of chemically assembled electronic nanotechnology circuit fabrication | pdf bib abstract | |
Seth Copen Goldstein and Daniel L. Rosewater.
In United States Patent No. 7,064,000. Issued June 20, 2006,
July, 2004.
|
| hide Abstract | Chemically assembled electronic nanotechnology (CAEN) provides an alternative to using Complementary Metal Oxide Semiconductor (CMOS) for constructing circuits with feature sizes in the tens of nanometers. A molecular latch and a method using the latch that enables it to act as a state holding device, perform voltage restoration, and to provide I/O isolation is disclosed. |
| | @misc{patent06,
author = {Goldstein, Seth Copen and Rosewater, Daniel L.},
title = {Methods of chemically assembled electronic nanotechnology
circuit fabrication},
howpublished = {United States Patent No. 7,064,000. Issued June 20,
2006},
month = {July},
year = {2004},
url = {http://www.cs.cmu.edu/~seth/papers/patent06.pdf},
keywords = {Molecular Electronics,Two-Terminal Devices},
abstract = {Chemically assembled electronic nanotechnology (CAEN)
provides an alternative to using Complementary Metal Oxide
Semiconductor (CMOS) for constructing circuits with feature sizes
in the tens of nanometers. A molecular latch and a method using
the latch that enables it to act as a state holding device,
perform voltage restoration, and to provide I/O isolation is
disclosed.},
url = {http://www.cs.cmu.edu/~seth/papers/patent06.pdf}
}
|
|
C to Asynchronous Dataflow Circuits: An End-to-End Toolflow | pdf bib abstract | |
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, and Seth Copen Goldstein.
In IEEE 13th International Workshop on Logic Synthesis (IWLS),
June, 2004.
|
| hide Abstract | We present a complete toolflow that translates ANSI-C programs into asynchronous circuits. The toolflow is built around a compiler that converts C into a functional dataflow intermediate representation, exposing instruction-level, pipeline and memory parallelism. The compiler performs optimizations and converts the intermediate representation into pipelined asynchronous circuits, with no centralized controllers. In the resulting circuits, control is distributed, communication is achieved through local wires, and arbitration for datapath resources is unnecessary. Circuits automatically synthesized from Mediabench kernels exhibit substantially better energy-delay than either single-issue processors or aggressive superscalar cores. |
| | @inproceedings{venkataramani-iwls04,
title = {{C} to Asynchronous Dataflow Circuits: An End-to-End
Toolflow},
author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
Tiberiu and Goldstein, Seth Copen},
booktitle = {IEEE 13th International Workshop on Logic Synthesis
(IWLS)},
address = {Temecula, CA},
month = {June},
year = {2004},
url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iwls04.pdf},
abstract = {We present a complete toolflow that translates ANSI-C
programs into asynchronous circuits. The toolflow is built around
a compiler that converts C into a functional dataflow
intermediate representation, exposing instruction-level, pipeline
and memory parallelism. The compiler performs optimizations and
converts the intermediate representation into pipelined
asynchronous circuits, with no centralized controllers. In the
resulting circuits, control is distributed, communication is
achieved through local wires, and arbitration for datapath
resources is unnecessary. Circuits automatically synthesized from
Mediabench kernels exhibit substantially better energy-delay than
either single-issue processors or aggressive superscalar cores.},
keywords = {Asychronous Circuits,Spatial Computing,Phoenix,CAD}
}
|
|
Computing Without Processors | bib abstract | |
Seth Copen Goldstein.
In International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'04),
pages 29–32, June, 2004.
|
| hide Abstract | The continuation of the remarkable exponential increases in processing power over the recent past faces imminent challenges due in part rising cost of design and manufacturing and the physics of deep-submicron semiconductor devices. In this talk we will discuss a promising alternative to ever more complex processors, application specific hardware (ASH). The ASH model is based on compiling high-level programs directly into circuits, which can either be fabricated as ASICs or more reasonably converted in configurations for reconfigurable devices. We will discuss the challenges involved in compiling sequential programming languages into circuits and the challenges in implementing those circuits in a scalable and power efficient manner. |
| | @inproceedings{goldstein04-ersa04,
author = {Goldstein, Seth Copen},
title = {Computing Without Processors},
booktitle = {International Conference on Engineering of
Reconfigurable Systems and Algorithms (ERSA'04)},
abstract = {The continuation of the remarkable exponential increases
in processing power over the recent past faces imminent
challenges due in part rising cost of design and manufacturing
and the physics of deep-submicron semiconductor devices. In this
talk we will discuss a promising alternative to ever more complex
processors, application specific hardware (ASH). The ASH model is
based on compiling high-level programs directly into circuits,
which can either be fabricated as ASICs or more reasonably
converted in configurations for reconfigurable devices. We will
discuss the challenges involved in compiling sequential
programming languages into circuits and the challenges in
implementing those circuits in a scalable and power efficient
manner.},
address = {Las Vegas, NV},
month = {June},
year = {2004},
pages = {29--32},
keywords = {Reconfigurable Computing, Electronic Nanotechnology,
Fault and Defect Tolerance}
}
|
|
Programmer Specified Pointer Independence | pdf bib abstract | |
David Ryan Koes, Mihai Budiu, Girish Venkataramani, and Seth Copen Goldstein.
In Proceedings of the 2004 workshop on Memory system performance (MSP),
pages 51–59, June, 2004.
Also appeared as Carnegie Mellon University TR CMU-CS-03-123.
|
| hide Abstract | Good alias analysis is essential in order to achieve high performance on modern processors, yet precise interprocedural analysis does not scale well. We present a source code annotation, \#pragma independent, which provides precise pointer aliasing information to the compiler, and describe a tool which highlights the most important and most likely correct locations at which a programmer should insert these annotations. Using this tool we perform a limit study on the effectiveness of pointer independence in improving program performance through improved compilation. |
| | @inproceedings{koes-msp2004,
author = {Koes, David Ryan and Budiu, Mihai and Venkataramani,
Girish and Goldstein, Seth Copen},
title = {Programmer Specified Pointer Independence},
booktitle = {Proceedings of the 2004 workshop on Memory system
performance (MSP)},
month = {June},
year = {2004},
isbn = {1-58113-941-1},
pages = {51--59},
address = {Washington, D.C.},
doi = {http://doi.acm.org/10.1145/1065895.1065905},
also = {Carnegie Mellon University TR CMU-CS-03-123},
url = {http://www.cs.cmu.edu/~seth/papers/koes-msp2004.pdf},
confweb = {http://cs.anu.edu.au/~Steve.Blackburn/msp2004},
publisher = {ACM Press},
abstract = {Good alias analysis is essential in order to achieve
high performance on modern processors, yet precise
interprocedural analysis does not scale well. We present a source
code annotation, {\tt \#pragma independent}, which provides
precise pointer aliasing information to the compiler, and
describe a tool which highlights the most important and most
likely correct locations at which a programmer should insert
these annotations. Using this tool we perform a limit study on
the effectiveness of pointer independence in improving program
performance through improved compilation.},
keywords = {Compilers:Alias Analysis,Phoenix}
}
|
|
Translating ANSI C to Asynchronous Circuits | pdf bib | |
Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein.
In 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '04),
April, 2004.
|
| @inproceedings{budiu-async04,
title = {Translating ANSI C to Asynchronous Circuits},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
booktitle = {10th IEEE International Symposium on Asynchronous
Circuits and Systems (ASYNC '04)},
author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
Tiberiu and Goldstein, Seth Copen},
address = {Crete, Greece},
year = {2004},
month = {April},
keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
Computing}
}
|
|
The Challenges and Opportunities of Nanoelectronics | pdf bib | |
Seth Copen Goldstein.
In Proceedings of Government Microcircuit Applications and Critical Technology Conference (GOMAC Tech 04),
March, 2004.
|
| @inproceedings{goldstein-gomac04,
title = {The Challenges and Opportunities of Nanoelectronics},
author = {Goldstein, Seth Copen},
booktitle = {Proceedings of Government Microcircuit Applications and
Critical Technology Conference (GOMAC Tech 04)},
year = {2004},
address = {Monterey, CA},
keywords = {Electronic Nanotechnology},
month = {March},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-gomac04.pdf}
}
|
|
Inter-Iteration Scalar Replacement in the Presence of Conditional Control-Flow | pdf bib | |
Mihai Budiu and Seth Copen Goldstein.
Carnegie Mellon University Technical Report,
February, 2004.
See budiu-odes05.
|
| @techreport{budiu-tr04,
title = {Inter-Iteration Scalar Replacement in the Presence of
Conditional Control-Flow},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr04.pdf},
booktitle = {CMU CS Technical Report, CMU-CS-04-103},
month = {February},
year = {2004},
author = {Budiu, Mihai and Goldstein, Seth Copen},
institution = {Carnegie Mellon University},
see = {budiu-odes05},
keywords = {Phoenix,Compilers:Loop Optimizations,Compilers:Scalar
Replacement}
}
|
2003 |
Reconfigurable Nanoelectronics and Defect Tolerance | bib | |
Seth Copen Goldstein.
In Proceedings of High-level design, verification, and test,
2003.
|
| @inproceedings{goldstein-hldvt03,
title = {Reconfigurable Nanoelectronics and Defect Tolerance},
author = {Goldstein, Seth Copen},
booktitle = {Proceedings of High-level design, verification, and
test},
year = {2003},
keywords = {Reconfigurable Computing, Electronic Nanotechnology,
Fault and Defect Tolerance}
}
|
|
Molecular Electronics: From Devices and Interconnect to Circuits and Architecture | pdf bib | |
Mircea R Stan, Paul D Franzon, Seth Copen Goldstein, John C Lach, and Matthew M Ziegler.
Proceedings of the IEEE,
91(11),November, 2003.
|
| @article{mircea-ieee03,
title = {Molecular Electronics: From Devices and Interconnect to
Circuits and Architecture},
author = {Stan, Mircea R and Franzon, Paul D and Goldstein, Seth
Copen and Lach, John C and Ziegler, Matthew M},
journal = {Proceedings of the IEEE},
year = {2003},
volume = {91},
number = {11},
month = {November},
keywords = {Electronic Nanotechnology},
url = {http://www.cs.cmu.edu/~seth/papers/mircea-ieee03.pdf}
}
|
|
Nano, Quantum, and Molecular Computing: Are We Ready for the Validation and Test Challenges | pdf bib talk | |
Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forest Brewer, Kaustav Banerjee, and Sankar Basu.
In Eighth IEEE International High-Level Design Validation and Test Workshop,
pages 307, November, 2003.
|
| @inproceedings{shukla-hldvt03,
title = {Nano, Quantum, and Molecular Computing: Are We Ready for
the Validation and Test Challenges},
url = {http://www.cs.cmu.edu/~seth/papers/shukla-hldvt03.pdf},
booktitle = {Eighth IEEE International High-Level Design Validation
and Test Workshop},
author = {Shukla, Sandeep K. and Karri, Ramesh and Goldstein, Seth
Copen and Brewer, Forest and Banerjee, Kaustav and Basu, Sankar},
year = {2003},
month = {November},
pages = {307},
address = {San Francisco, CA},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,molecular electronics}
}
|
|
Defect Tolerance at the End of the Roadmap | pdf bib abstract | |
Mahim Mishra and Seth Copen Goldstein.
In Proceedings of the International Test Conference (ITC), 2003,
September, 2003.
|
| hide Abstract | Defect tolerance will become more important as feature sizes shrink closer to single digit nanometer dimensions. This is true whether the chips are manufactured using top-down methods (e.g., photolithography) or bottom-up methods (e.g., chemically assembled electronic nanotechnology, or CAEN). In this paper, we propose a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. Our methodology is particularly well suited for CAEN. |
| | @inproceedings{mishra-itc03,
author = {Mishra, Mahim and Goldstein, Seth Copen},
title = {Defect Tolerance at the End of the Roadmap},
booktitle = {Proceedings of the International Test Conference
({ITC}), 2003},
month = {September},
year = {2003},
address = {Charlotte, {NC}},
url = {http://www.cs.cmu.edu/~seth/papers/mishra-itc03.pdf},
abstract = {Defect tolerance will become more important as feature
sizes shrink closer to single digit nanometer dimensions. This is
true whether the chips are manufactured using top-down methods
(e.g., photolithography) or bottom-up methods (e.g., chemically
assembled electronic nanotechnology, or CAEN). In this paper, we
propose a defect tolerance methodology centered around
reconfigurable devices, a scalable testing method, and dynamic
place-and-route. Our methodology is particularly well suited for
CAEN.},
keywords = {Spatial Computing, Reconfigurable
Computing,Phoenix,Fault and Defect Tolerance}
}
|
|
Models and Abstractions for Nanoelectronics | bib | |
Seth Copen Goldstein and Y Zhu.
In Third IEEE Conference on Nanotechnology (IEEE-NANO 2003),
August, 2003.
|
| @inproceedings{goldstein-inano03,
title = {Models and Abstractions for Nanoelectronics},
booktitle = {Third IEEE Conference on Nanotechnology (IEEE-NANO
2003)},
author = {Goldstein, Seth Copen and Zhu, Y},
address = {San Francisco, CA},
year = {2003},
month = {August},
keywords = {Electronic Nanotechnology}
}
|
|
Reconfigurable Computing and Electronic Nanotechnology | pdf bib abstract | |
Seth Copen Goldstein, Mihai Budiu, Mahim Mishra, and Girish Venkataramani.
In Proceedings of the IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2003),
pages 132–143, June, 2003.
|
| hide Abstract | In this paper we examine the opportunities brought about by recent progress in electronic nanotechnology and describe the methods needed to harness them for building a new computer architecture. In this process we decompose some traditional abstractions, such as the transistor, into fine-grain pieces, such as signal restoration and input-output isolation. We also show how we can forgo the extreme reliability of CMOS circuits for low-cost chemical self-assembly at the expense of large manufacturing defect densities. We discuss advanced testing methods which can be used to recover perfect functionality from unreliable parts. We proceed to show how the molecular switch, the regularity of the circuits created by self-assembly and the high defect densities logically require the use of reconfigurable hardware as a basic building block for hardware design. We then capitalize on the convergence of compilation and hardware synthesis (which takes place when programming reconfigurable hardware) to propose the complete elimination of the instruction-set architecture from the system architecture, and the synthesis of asynchronous dataflow machines directly from high-level programming languages, such as C. We discuss in some detail a scalable compilation system that perform this task. |
| | @inproceedings{goldstein-asap03,
title = {Reconfigurable Computing and Electronic Nanotechnology},
author = {Goldstein, Seth Copen and Budiu, Mihai and Mishra, Mahim
and Venkataramani, Girish},
booktitle = {Proceedings of the {IEEE} 14th International Conference
on Application-specific Systems, Architectures and Processors
({ASAP} 2003)},
year = {2003},
address = {The Hague, Netherlands},
month = {June},
pages = {132-143},
abstract = {In this paper we examine the opportunities brought about
by recent progress in electronic nanotechnology and describe the
methods needed to harness them for building a new computer
architecture. In this process we decompose some traditional
abstractions, such as the transistor, into fine-grain pieces,
such as signal restoration and input-output isolation. We also
show how we can forgo the extreme reliability of CMOS circuits
for low-cost chemical self-assembly at the expense of large
manufacturing defect densities. We discuss advanced testing
methods which can be used to recover perfect functionality from
unreliable parts. We proceed to show how the molecular switch,
the regularity of the circuits created by self-assembly and the
high defect densities logically require the use of reconfigurable
hardware as a basic building block for hardware design. We then
capitalize on the convergence of compilation and hardware
synthesis (which takes place when programming reconfigurable
hardware) to propose the complete elimination of the
instruction-set architecture from the system architecture, and
the synthesis of asynchronous dataflow machines directly from
high-level programming languages, such as C. We discuss in some
detail a scalable compilation system that perform this task.},
keywords = {Reconfigurable Computing, Electronic Nanotechnology},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asap03.pdf}
}
|
|
Defect Tolerance After the Roadmap | pdf bib | |
Mahim Mishra and Seth Copen Goldstein.
In Proceedings of the 10th International Test Synthesis Workshop (ITSW),
March, 2003.
|
| @inproceedings{mishra-itsw03,
author = {Mishra, Mahim and Goldstein, Seth Copen},
title = {Defect Tolerance After the Roadmap},
booktitle = {Proceedings of the 10th International Test Synthesis
Workshop (ITSW)},
month = {March},
year = {2003},
address = {Santa Barbara, {CA}},
keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
Fault and Defect Tolerance},
url = {http://www.cs.cmu.edu/~seth/papers/mishra-itsw03.pdf}
}
|
|
Optimizing Memory Accesses For Spatial Computation | pdf bib | |
Mihai Budiu and Seth Copen Goldstein.
In Proceedings of the 1st International ACM/IEEE Symposium on Code Generation and Optimization (CGO 03),
pages 216–227, March, 2003.
|
| @inproceedings{budiu-cgo03,
title = {Optimizing Memory Accesses For Spatial Computation},
author = {Budiu, Mihai and Goldstein, Seth Copen},
booktitle = {Proceedings of the 1st International ACM/IEEE Symposium
on Code Generation and Optimization (CGO 03)},
year = {2003},
address = {San Francisco, CA},
month = {March},
pages = {216-227},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-cgo03.pdf},
keywords = {Spatial Computing, Reconfigurable
Computing,Phoenix,Compilers:Memory Optimizations}
}
|
|
Molecules, Gates, Circuits, Computer | pdf bib | |
Seth Copen Goldstein and Mihai Budiu.
In Molecular Nanoelectronics,,
January, 2003.
|
| @incollection{goldstein-mn03,
title = {Molecules, Gates, Circuits, Computer},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
booktitle = {Molecular Nanoelectronics,},
author = {Goldstein, Seth Copen and Budiu, Mihai},
year = {2003},
editor = {Mark A. Reed and Takhee Lee},
publisher = {American Scientific Publishers},
address = {Stevenson Ranch, CA},
month = {January},
isbn = {1-588883-006-3},
keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
and Defect Tolerance,Reconfigurable Computing,Spatial
Computing,electronic nanotechnology,molecular electronics}
}
|
2002 |
Scalable Defect Tolerance for Molecular Electronics | pdf bib abstract | |
Mahim Mishra and Seth Copen Goldstein.
In Proceedings of the 1st Workshop on Non-Silicon Computing (NSC-1),
2002.
|
| hide Abstract | Chemically assembled electronic nanotechnology (CAEN) is a promising alternative to CMOS-based computing. However, CAEN-based circuits are expected to have huge defect densities. To solve this problem CAEN can be used to build reconfigurable fabrics which, assuming the defects can be found, are inherently defect tolerant. In this paper, we propose a scalable testing methodology for finding defects in reconfigurable devices. |
| | @inproceedings{mishra_goldstein_nsc1,
author = {Mishra, Mahim and Goldstein, Seth Copen},
title = {Scalable Defect Tolerance for Molecular Electronics},
booktitle = {Proceedings of the 1st Workshop on Non-Silicon
Computing (NSC-1)},
address = {{Cambridge, MA}},
year = {2002},
url = {http://www.cs.cmu.edu/~seth/papers/mishra_goldstein_nsc1.pdf},
abstract = {Chemically assembled electronic nanotechnology (CAEN) is
a promising alternative to CMOS-based computing. However,
CAEN-based circuits are expected to have huge defect densities.
To solve this problem CAEN can be used to build reconfigurable
fabrics which, assuming the defects can be found, are inherently
defect tolerant. In this paper, we propose a scalable testing
methodology for finding defects in reconfigurable devices.},
keywords = {Reconfigurable Computing, Phoenix,Fault and Defect
Tolerance}
}
|
|
From Molecules to Computers | pdf bib | |
Seth Copen Goldstein.
In Tutorial at 35th Annual International Symposium on Microarchitecture (Micro 35),
November, 2002.
|
| @inproceedings{micro02,
title = {From Molecules to Computers},
author = {Goldstein, Seth Copen},
year = {2002},
address = {Istanbul, Turkey},
booktitle = {Tutorial at 35th Annual International Symposium on
Microarchitecture (Micro 35)},
url = {http://www.cs.cmu.edu/~seth/papers/micro02.pdf},
month = {November},
keywords = {Electronic Nanotechnology}
}
|
|
Molecular electronics: devices, systems and tools for gigagate,gigabit chips | pdf bib abstract | |
Michael Butts, Andre DeHon, and Seth Copen Goldstein.
In International Conference on Computer-Aided Design ( ICCAD '02),
pages 433–440, November, 2002.
|
| hide Abstract | New electronics technologies are emerging which may carry us beyond the limits of lithographic processing down to molecular-scale feature sizes. Devices and interconnects can be made from a variety of molecules and materials including bistable and switchable organic molecules, carbon nanotubes, and, single-crystal semiconductor nanowires. They can be self-assembled into organized structures and attached onto lithographic substrates. This tutorial reviews emerging molecular-scale electronics technology for CAD and system designers and highlights where ICCAD research can help support this technology. |
| | @inproceedings{butts-iccad02,
title = {Molecular electronics: devices, systems and tools for
gigagate,gigabit chips},
url = {http://www.cs.cmu.edu/~seth/papers/butts-iccad02.pdf},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167569},
booktitle = {International Conference on Computer-Aided Design (
ICCAD '02)},
author = {Butts, Michael and DeHon, Andre and Goldstein, Seth
Copen},
abstract = {New electronics technologies are emerging which may
carry us beyond the limits of lithographic processing down to
molecular-scale feature sizes. Devices and interconnects can be
made from a variety of molecules and materials including bistable
and switchable organic molecules, carbon nanotubes, and,
single-crystal semiconductor nanowires. They can be
self-assembled into organized structures and attached onto
lithographic substrates. This tutorial reviews emerging
molecular-scale electronics technology for CAD and system
designers and highlights where ICCAD research can help support
this technology.},
address = {San Jose, CA},
year = {2002},
pages = {433-440},
month = {November},
keywords = {Electronic Nanotechnology,Reconfigurable
Computing,molecular electronics}
}
|
|
Compiling Application-Specific Hardware | pdf bib abstract | |
Mihai Budiu and Seth Copen Goldstein.
In Proceedings of the 12th International Conference on Field Programmable Logic and Applications,
pages 853–863, September, 2002.
|
| hide Abstract | In this paper we describe ASH, an architectural framework for implementing Application-Specific Hardware. ASH is based on automatic hardware synthesis from high-level languages. The generated circuits use only localized computation structures; in consequence, we expect these circuits to be fast, to use little power and to scale well with program complexity. We present in detail CASH, a scalable compiler framework for ASH, which generates hardware from programs written in C. Our compiler exploits instruction level parallelism by using aggressive speculation and dynamic scheduling. Based on this compilation scheme, we evaluate the computational resources necessary for implementing complex integer-based programs, and we suggest architectural features that would support the ASH framework. |
| | @inproceedings{budiu-fpl02,
author = {Budiu, Mihai and Goldstein, Seth Copen},
title = {Compiling Application-Specific Hardware},
booktitle = {Proceedings of the 12th International Conference on
Field Programmable Logic and Applications},
year = {2002},
address = {Montpellier (La Grande-Motte), France},
month = {September},
pages = {853--863},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-fpl02.pdf},
abstract = {In this paper we describe ASH, an architectural
framework for implementing Application-Specific Hardware. ASH is
based on automatic hardware synthesis from high-level languages.
The generated circuits use only localized computation structures;
in consequence, we expect these circuits to be fast, to use
little power and to scale well with program complexity. \par We
present in detail CASH, a scalable compiler framework for ASH,
which generates hardware from programs written in C. Our compiler
exploits instruction level parallelism by using aggressive
speculation and dynamic scheduling. Based on this compilation
scheme, we evaluate the computational resources necessary for
implementing complex integer-based programs, and we suggest
architectural features that would support the ASH framework.},
keywords = {Spatial Computing,Phoenix,Compilers:CASH}
}
|
|
Factors Influencing the Performance of a CPU-RFU Hybrid Architecture | pdf bib abstract | |
Girish Venkataramani, Suraj Sudhir, Mihai Budiu, and Seth Copen Goldstein.
In Proceedings of the 12th International Conference on Field Programmable Logic and Applications (FPL),
pages 955–965, September, 2002.
|
| hide Abstract | Closely coupling a reconfigurable fabric with a conventional processor has been shown to successfully improve the system performance. However, today s superscalar pro-cessors are both complex and adept at extracting Instruction Level Parallelism (ILP), which introduces many complex issues to the design of a hybrid CPU-RFU system. This paper examines the design of a superscalar processor augmented with a closely-coupled recon-figurable fabric. It identifies architectural and compiler issues that affect the performance of the overall system. Previous efforts at combining a processor core with a reconfigurable fabric are examined in the light of these issues. We also present simulation results that emphasize the impact of these factors. |
| | @inproceedings{venkataramani-fpl02,
title = {Factors Influencing the Performance of a CPU-RFU Hybrid
Architecture},
author = {Venkataramani, Girish and Sudhir, Suraj and Budiu, Mihai
and Goldstein, Seth Copen},
booktitle = {Proceedings of the 12th International Conference on
Field Programmable Logic and Applications (FPL)},
year = {2002},
address = {Montpellier (La Grande-Motte), France},
month = {September},
url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-fpl02.pdf},
abstract = {Closely coupling a reconfigurable fabric with a
conventional processor has been shown to successfully improve the
system performance. However, today s superscalar pro-cessors are
both complex and adept at extracting Instruction Level
Parallelism (ILP), which introduces many complex issues to the
design of a hybrid CPU-RFU system. This paper examines the design
of a superscalar processor augmented with a closely-coupled
recon-figurable fabric. It identifies architectural and compiler
issues that affect the performance of the overall system.
Previous efforts at combining a processor core with a
reconfigurable fabric are examined in the light of these issues.
We also present simulation results that emphasize the impact of
these factors.},
pages = {955-965},
isbn = {3-540-44108-5},
publisher = {Springer-Verlag},
keywords = {Spatial Computing,Reconfigurable Computing,Phoenix}
}
|
|
What makes a good molecular computing device? | pdf bib | |
Daniel L. Rosewater and Seth Copen Goldstein.
Carnegie Mellon University Technical Report No. CMU-CS-02-181,
September, 2002.
|
| @techreport{rg01,
author = {Rosewater, Daniel L. and Goldstein, Seth Copen},
title = {What makes a good molecular computing device?},
institution = {Carnegie Mellon University},
year = {2002},
number = {CMU-CS-02-181},
month = {September},
keywords = {Electronic Nanotechnology},
url = {http://www.cs.cmu.edu/~seth/papers/rg01.pdf}
}
|
|
Assembly And Differentiation | pdf bib | |
Seth Copen Goldstein.
In CRA Conference on Grand Research Challenges,
June, 2002.
|
| @inproceedings{goldstein-cra02,
title = {Assembly And Differentiation},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-cra02.pdf},
booktitle = {CRA Conference on Grand Research Challenges},
author = {Goldstein, Seth Copen},
address = {Warrenton, Virginia},
year = {2002},
month = {June},
keywords = {Programmable Matter}
}
|
|
Pegasus: An Efficient Intermediate Representation | pdf bib abstract | |
Mihai Budiu and Seth Copen Goldstein.
Carnegie Mellon University Technical Report No. CMU-CS-02-107,
pages 20, May, 2002.
|
| hide Abstract | We present Pegasus, a compact and expressive intermediate representation for imperative languages. The representation is suitable for target architectures supporting predicated execution and aggressive speculation. In Pegasus information about the global dataflow of the program is encoded in local structures, enabling compact and efficient algorithms for program optimizations. As a proof of the versatility of Pegasus, we have used it in a compiler translating C programs to hardware implementations. |
| | @techreport{budiu-tr02,
author = {Budiu, Mihai and Goldstein, Seth Copen},
title = {Pegasus: An Efficient Intermediate Representation},
institution = {Carnegie Mellon University},
year = {2002},
number = {CMU-CS-02-107},
month = {May},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr02.pdf},
pages = {20},
abstract = {We present Pegasus, a compact and expressive
intermediate representation for imperative languages. The
representation is suitable for target architectures supporting
predicated execution and aggressive speculation. In Pegasus
information about the global dataflow of the program is encoded
in local structures, enabling compact and efficient algorithms
for program optimizations. As a proof of the versatility of
Pegasus, we have used it in a compiler translating C programs to
hardware implementations.},
keywords = {Spatial Computing, Reconfigurable Computing,Phoenix}
}
|
|
Memory: Improving Memory Locality in Very Large Reconfigurable Fabrics | pdf bib | |
Rong Yan and Seth Copen Goldstein.
In Proceedings of 2002 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM),
April, 2002.
|
| @inproceedings{yan-fccm02,
author = {Yan, Rong and Goldstein, Seth Copen},
title = {Memory: Improving Memory Locality in Very Large
Reconfigurable Fabrics},
booktitle = {Proceedings of 2002 IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM)},
year = {2002},
address = {Napa Valley, CA},
month = {April},
url = {http://www.cs.cmu.edu/~seth/papers/yan-fccm02.pdf},
keywords = {Reconfigurable Computing}
}
|
|
Molecular scale latch and associated clocking scheme to provide gain, memory and I/O isolation | pdf bib abstract | |
Seth Copen Goldstein and Daniel L. Rosewater.
In United States Patent No. 6,777,982. Issued August 17, 2004,
April, 2002.
|
| hide Abstract | Chemically assembled electronic nanotechnology (CAEN) provides an alternative to using Complementary Metal Oxide Semiconductor (CMOS) for constructing circuits with feature sizes in the tens of nanometers. A molecular latch and a method using the latch that enables it to act as a state holding device, perform voltage restoration, and to provide I/O isolation is disclosed. |
| | @misc{patent04,
author = {Goldstein, Seth Copen and Rosewater, Daniel L.},
title = {Molecular scale latch and associated clocking scheme to
provide gain, memory and I/O isolation},
howpublished = {United States Patent No. 6,777,982. Issued August
17, 2004},
month = {April},
url = {http://www.cs.cmu.edu/~seth/papers/patent04.pdf},
year = {2002},
keywords = {Molecular Electronics,Two-Terminal Devices},
abstract = {Chemically assembled electronic nanotechnology (CAEN)
provides an alternative to using Complementary Metal Oxide
Semiconductor (CMOS) for constructing circuits with feature sizes
in the tens of nanometers. A molecular latch and a method using
the latch that enables it to act as a state holding device,
perform voltage restoration, and to provide I/O isolation is
disclosed.},
url = {http://www.cs.cmu.edu/~seth/papers/patent04.pdf}
}
|
|
Peer-to-peer Hardware-Software Interfaces for Reconfigurable Fabrics | pdf bib abstract | |
Mihai Budiu, Mahim Mishra, Ashwin Bharambe, and Seth Copen Goldstein.
In Proceedings of 2002 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM),
pages 57–66, April, 2002.
|
| hide Abstract | In this paper we describe a peer-to-peer interface between processor cores and reconfigurable fabrics. The main advantage of the peer-to-peer model is that it greatly expands the scope of application for reconfigurable computing and hence its potential benefits. The primary extension in our model is that “code” on the reconfigurable hardware unit is allowed to invoke routines both on the reconfigurable unit itself and on the fixed logic processor. We describe the software constructs and compilation mechanisms needed for such an architecture, including a detailed description of the interface between the two parts of the application. |
| | @inproceedings{budiu-fccm02,
author = {Budiu, Mihai and Mishra, Mahim and Bharambe, Ashwin and
Goldstein, Seth Copen},
title = {Peer-to-peer Hardware-Software Interfaces for
Reconfigurable Fabrics},
booktitle = {Proceedings of 2002 IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM)},
year = {2002},
month = {April},
pages = {57-66},
address = {Napa Valley, CA},
abstract = {In this paper we describe a peer-to-peer interface
between processor cores and reconfigurable fabrics. The main
advantage of the peer-to-peer model is that it greatly expands
the scope of application for reconfigurable computing and hence
its potential benefits. The primary extension in our model is
that ``code'' on the reconfigurable hardware unit is allowed to
invoke routines both on the reconfigurable unit itself and on the
fixed logic processor. We describe the software constructs and
compilation mechanisms needed for such an architecture, including
a detailed description of the interface between the two parts of
the application.},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-fccm02.pdf},
keywords = {Reconfigurable Computing}
}
|
|
Digital Logic Using Molecular Electronics | pdf bib | |
Dan Rosewater and Seth Copen Goldstein.
In IEEE International Solid-State Circuits Conference (ISSCC),
February, 2002.
|
| @inproceedings{isscc02,
author = {Rosewater, Dan and Goldstein, Seth Copen},
title = {Digital Logic Using Molecular Electronics},
booktitle = {IEEE International Solid-State Circuits Conference
(ISSCC)},
year = {2002},
month = {February},
address = {San Francisco, CA},
keywords = {Electronic Nanotechnology,Molecular
Electronics,Two-Terminal Devices},
url = {http://www.cs.cmu.edu/~seth/papers/isscc02.pdf}
}
|
2001 |
MolSpice: Designing Molecular Logic Circuits | pdf bib | |
Seth Copen Goldstein, James Ellenbogen, David Almassiam, Matt Brown, Mark Cannarsa, Jesse Klein, Schuyler Schell, Geoff Washburn, and Matthew M Ziegler.
In Ninth Foresight Conference on Molecular Nanotechnology,
November, 2001.
|
| @inproceedings{goldstein-foresight01,
author = {Goldstein, Seth Copen and Ellenbogen, James and Almassiam,
David and Brown, Matt and Cannarsa, Mark and Klein, Jesse and
Schell, Schuyler and Washburn, Geoff and Ziegler, Matthew M},
title = {MolSpice: Designing Molecular Logic Circuits},
booktitle = {Ninth Foresight Conference on Molecular
Nanotechnology},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-foresight01.pdf},
year = {2001},
month = {November},
address = {Santa Clara, CA},
keywords = {Electronic Nanotechnology, Molecular Electronics, CAD}
}
|
|
Configuration Caching and Swapping | pdf bib | |
Suraj Sudhir, Suman Nath, and Seth Copen Goldstein.
In 11th International Conference on Field Programmable Logic and Applications,
August, 2001.
|
| @inproceedings{sudhir-fpl01,
author = {Sudhir, Suraj and Nath, Suman and Goldstein, Seth Copen},
title = {Configuration Caching and Swapping},
year = {2001},
booktitle = {11th International Conference on Field Programmable
Logic and Applications},
address = {Belfast, Northern Ireland},
month = {August},
keywords = {Reconfigurable Computing},
url = {http://www.cs.cmu.edu/~seth/papers/sudhir-fpl01.pdf}
}
|
|
Static Profile-driven Compilation for FPGAs | pdf bib | |
Srihari Cadambi and Seth Copen Goldstein.
In Proceedings of the 11th International Conference on Field-Programmable Logic and Applications,
August, 2001.
|
| @inproceedings{cadambi-fpl01,
title = {Static Profile-driven Compilation for FPGAs},
url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpl01.pdf},
booktitle = {Proceedings of the 11th International Conference on
Field-Programmable Logic and Applications},
author = {Cadambi, Srihari and Goldstein, Seth Copen},
address = {Belfast, Northern Ireland},
year = {2001},
month = {August},
keywords = {CAD,Reconfigurable Computing}
}
|
|
NanoFabrics: Spatial Computing Using Molecular Electronics | pdf bib abstract | |
Seth Copen Goldstein and Mihai Budiu.
In Proceedings of the 28th International Symposium on Computer Architecture (ISCA),
pages 178–189, July, 2001.
|
| hide Abstract | The continuation of the remarkable exponential increases in processing power over the recent past faces imminent challenges due in part to the physics of deep-submicron CMOS devices and the costs of both chip masks and future fabrication plants. A promising solution to these problems is offered by an alternative to CMOS-based computing, chemically assembled electronic nanotechnology (CAEN). In this paper we outline how CAEN based computing can become a reality. We briefly describe recent work in CAEN and how CAEN will affect computer architecture. We show how the inherently reconfigurable natures of CAEN devices can be exploited to provide high-density chips with defect tolerance which will significantly reduce the cost of manufacturing. After developing the basic building blocks of a CAEN based computing devices we present some preliminary results which indicate that CAEN based computing devices can meet or exceed the performance of CMOS based devices. |
| | @inproceedings{goldstein-isca01,
author = {Goldstein, Seth Copen and Budiu, Mihai},
title = {{NanoFabrics}: Spatial Computing Using Molecular
Electronics},
booktitle = {Proceedings of the 28th International Symposium on
Computer Architecture (ISCA)},
month = {July},
address = {{G\"{o}teborg, Sweden}},
year = {2001},
pages = {178--189},
abstract = {The continuation of the remarkable exponential increases
in processing power over the recent past faces imminent
challenges due in part to the physics of deep-submicron CMOS
devices and the costs of both chip masks and future fabrication
plants. A promising solution to these problems is offered by an
alternative to CMOS-based computing, chemically assembled
electronic nanotechnology (CAEN). In this paper we outline how
CAEN based computing can become a reality. We briefly describe
recent work in CAEN and how CAEN will affect computer
architecture. We show how the inherently reconfigurable natures
of CAEN devices can be exploited to provide high-density chips
with defect tolerance which will significantly reduce the cost of
manufacturing. After developing the basic building blocks of a
CAEN based computing devices we present some preliminary results
which indicate that CAEN based computing devices can meet or
exceed the performance of CMOS based devices.},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca01.pdf},
keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
Electronic Nanotechnology}
}
|
|
Electronic Nanotechnology and Reconfigurable Computing | pdf bib | |
Seth Copen Goldstein.
In Proceedings of the IEEE Computer Society Workshop VLSI 2001,
pages 10, April, 2001.
|
| @inproceedings{goldstein-wvlsi01,
title = {Electronic Nanotechnology and Reconfigurable Computing},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-wvlsi01.pdf},
booktitle = {Proceedings of the IEEE Computer Society Workshop VLSI
2001},
author = {Goldstein, Seth Copen},
year = {2001},
pages = {10},
month = {April},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Reconfigurable Computing}
}
|
2000 |
Interfacing Reconfigurable Logic with a CPU | pdf bib abstract | |
Kevin Walker, Mihai Budiu, and Seth Copen Goldstein.
In 2000 IEEE Symposium on Field-Programmable Custom Computing Machines,
pages 317–318, 2000.
|
| hide Abstract | Reconfigurable computing devices have achieved substantial performance improvements over conventional processors on some computational kernels. These benefits derive from hardware customization which avoids the mismatch between the basic requirements of the algorithms and the architectures of the processors. A reconfigurable fabric alone is not sufficient for general-purpose computing since it can be ill-suited to executing entire programs due to space limitations, dataflow-centricity, and inefficiency at implementing some operations (e.g. floating-point arithmetic). These observations have led to the appearance of numerous designs which place some form of reconfigurable logic under the control of a general-purpose processor. The authors explore the ways in which a reconfigurable fabric can be interfaced with a general-purpose processor. While off-chip reconfigurable fabrics have proven to be quite effective at performing streaming, data-intensive computations, they require large streams of data to overcome the latency between the devices. We explore the design space for an on-chip fabric, i.e., a reconfigurable function unit (RFU). An RFU allows smaller portions of application to be mapped to the fabric in the form of custom instructions. Though the speedups achieved for stream based computations will in general be much larger than those for custom instructions, they are limited to a smaller class of applications. Custom instructions, however, can be found in a larger class of programs, and compiler techniques can automatically create them. |
| | @inproceedings{walker-fccm00,
author = {Walker, Kevin and Budiu, Mihai and Goldstein, Seth Copen},
title = {Interfacing Reconfigurable Logic with a {CPU}},
booktitle = {2000 IEEE Symposium on Field-Programmable Custom
Computing Machines},
pages = {317--318},
year = {2000},
url = {http://www.cs.cmu.edu/~seth/papers/walker-fccm00.pdf},
abstract = {Reconfigurable computing devices have achieved
substantial performance improvements over conventional processors
on some computational kernels. These benefits derive from
hardware customization which avoids the mismatch between the
basic requirements of the algorithms and the architectures of the
processors. A reconfigurable fabric alone is not sufficient for
general-purpose computing since it can be ill-suited to executing
entire programs due to space limitations, dataflow-centricity,
and inefficiency at implementing some operations (e.g.
floating-point arithmetic). These observations have led to the
appearance of numerous designs which place some form of
reconfigurable logic under the control of a general-purpose
processor. The authors explore the ways in which a reconfigurable
fabric can be interfaced with a general-purpose processor. While
off-chip reconfigurable fabrics have proven to be quite effective
at performing streaming, data-intensive computations, they
require large streams of data to overcome the latency between the
devices. We explore the design space for an on-chip fabric, i.e.,
a reconfigurable function unit (RFU). An RFU allows smaller
portions of application to be mapped to the fabric in the form of
custom instructions. Though the speedups achieved for stream
based computations will in general be much larger than those for
custom instructions, they are limited to a smaller class of
applications. Custom instructions, however, can be found in a
larger class of programs, and compiler techniques can
automatically create them.},
keywords = {Reconfigurable Computing}
}
|
|
Pipeline Reconfigurable FPGAs | pdf bib | |
Herman Schmit, Seth Copen Goldstein, Srihari Cadambi, and Matthew Moe.
In Field-Programmable Custom Computing Technology: Architecture, Tools, and Applications,
2000.
|
| @incollection{schmit-fpcct00,
title = {Pipeline Reconfigurable FPGAs},
url = {http://www.cs.cmu.edu/~seth/papers/schmit-fpcct00.pdf},
booktitle = {Field-Programmable Custom Computing Technology:
Architecture, Tools, and Applications},
author = {Schmit, Herman and Goldstein, Seth Copen and Cadambi,
Srihari and Moe, Matthew},
year = {2000},
editor = {Arnold, Jeffrey and Luk, Wayne and Pocek, Ken},
publisher = {Kluwer Academic Publishers},
isbn = {0-7923-7803-2},
keywords = {PipeRench,Reconfigurable Computing}
}
|
|
NanoFabrics: Extending Moore's Law Beyond the CMOS Era | pdf bib | |
Seth Copen Goldstein.
In The 10th International Conference on Architectural Support for Programming Languages and Operating Systems. (ASPLOS 'IX),
November, 2000.
|
| @inproceedings{goldstein-asplos00,
title = {NanoFabrics: Extending Moore's Law Beyond the CMOS Era},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asplos00.pdf},
booktitle = {The 10th International Conference on Architectural
Support for Programming Languages and Operating Systems. (ASPLOS
'IX)},
author = {Goldstein, Seth Copen},
address = {Cambridge, MA},
year = {2000},
month = {November},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Molecular Electronics,Reconfigurable Computing}
}
|
|
Efficient Place and Route for Pipeline Reconfigurable Architectures | pdf bib | |
Srihari Cadambi and Seth Copen Goldstein.
In ICCD '00,
September, 2000.
|
| @inproceedings{cadambi-iccd00,
title = {Efficient Place and Route for Pipeline Reconfigurable
Architectures},
url = {http://www.cs.cmu.edu/~seth/papers/cadambi-iccd00.pdf},
booktitle = {ICCD '00},
author = {Cadambi, Srihari and Goldstein, Seth Copen},
address = {Austin, TX},
year = {2000},
month = {September},
keywords = {CAD,Place and Route}
}
|
|
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations | pdf bib abstract | |
Mihai Budiu, Majd Sakr, Kevin Walker, and Seth Copen Goldstein.
In Proceedings of the 2000 Europar Conference,
volume 1900, pages 969–979,August, 2000.
Also appeared as CMU CS Technical Report, CMU-CS-00-141, October 2000..
|
| hide Abstract | We present a compiler algorithm called BitValue, which can discover both unused and constant bits in dusty-deck C programs. BitValue uses forward and backward dataflow analyses, generalizing constant-folding and dead-code detection at the bit-level. This algorithm enables compiler optimizations which target special processor architectures for computing on non-standard bitwidths. Using this algorithm we show that up to 31% of the computed bytes are thrown away (for programs from SpecINT95 and Mediabench). A compiler for reconfigurable hardware uses this algorithm to achieve substantial reductions (up to 20-fold) in the size of the synthesized circuits. |
| | @inproceedings{budiu-europar00,
title = {{BitValue} Inference: Detecting and Exploiting Narrow
Bitwidth Computations},
author = {Budiu, Mihai and Sakr, Majd and Walker, Kevin and
Goldstein, Seth Copen},
booktitle = {Proceedings of the 2000 Europar Conference},
year = {2000},
volume = {1900},
pages = {969--979},
month = {August},
issn = {0302-9743},
series = {Lecture Notes in Computer Science},
publisher = {Springer Verlag},
address = {Munich, Germany},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-europar00.pdf},
also = {CMU CS Technical Report, CMU-CS-00-141, October 2000.},
abstract = {We present a compiler algorithm called BitValue, which
can discover both unused and constant bits in dusty-deck C
programs. BitValue uses forward and backward dataflow analyses,
generalizing constant-folding and dead-code detection at the
bit-level. This algorithm enables compiler optimizations which
target special processor architectures for computing on
non-standard bitwidths. Using this algorithm we show that up to
31\% of the computed bytes are thrown away (for programs from
SpecINT95 and Mediabench). A compiler for reconfigurable hardware
uses this algorithm to achieve substantial reductions (up to
20-fold) in the size of the synthesized circuits.},
keywords = {Spatial Computing,Reconfigurable
Computing,Phoenix,PipeRench,CAD}
}
|
|
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations | pdf bib | |
Mihai Budiu and Seth Copen Goldstein.
Carnegie Mellon University Technical Report,
June, 2000.
See budiu-europar00.
|
| @techreport{budiu-tr00,
title = {BitValue Inference: Detecting and Exploiting Narrow
Bitwidth Computations},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr00.pdf},
booktitle = {CMU CS Technical Report, CMU-CS-00-141},
author = {Budiu, Mihai and Goldstein, Seth Copen},
institution = {Carnegie Mellon University},
year = {2000},
month = {June},
see = {budiu-europar00},
keywords = {CAD,Compilers:CASH,Reconfigurable Computing}
}
|
|
Fault Tolerance in Run-time Reconfigurable Architectures | bib | |
Peter M. Kamarchik, Steven Sinha, and Seth Copen Goldstein.
In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '00),
April, 2000.
|
| @inproceedings{KSS00,
author = {Kamarchik, Peter M. and Sinha, Steven and Goldstein, Seth
Copen},
title = {Fault Tolerance in Run-time Reconfigurable Architectures},
booktitle = {IEEE Symposium on FPGAs for Custom Computing Machines
(FCCM '00)},
year = {2000},
month = {April},
address = {Napa, CA},
keywords = {PipeRench, Fault and Defect Tolerance}
}
|
|
Pipeline Reconfigurable FPGAs | pdf bib abstract | |
Herman Schmit, Srihari Cadambi, Matthew Moe, and Seth Copen Goldstein.
Journal of VLSI Signal Processing Systems,
33(4):70–77,April, 2000.
Also appeared as chapter in Field-Programmable Custom Computing Technology: Architecture, Tools, and Applications.
|
| hide Abstract | While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be achieved using the technique of pipeline reconfiguration. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis on PipeRench predicts that it will outperform commercial FPGAs and DSPs in both overall performance and in performance normalized for silicon area over a broad range of problem sizes. |
| | @article{schmit-jvlsi00,
author = {Schmit, Herman and Cadambi, Srihari and Moe, Matthew and
Goldstein, Seth Copen},
title = {Pipeline Reconfigurable FPGAs},
journal = {Journal of VLSI Signal Processing Systems},
volume = {33},
month = {April},
year = {2000},
pages = {70-77},
abstract = {While reconfigurable computing promises to deliver
incomparable performance, it is still a marginal technology due
to the high cost of developing and upgrading applications.
Hardware virtualization can be used to significantly reduce both
these costs. In this paper we describe the benefits of hardware
virtualization, and show how it can be achieved using the
technique of pipeline reconfiguration. The result is PipeRench,
an architecture that supports robust compilation and provides
forward compatibility. Our preliminary performance analysis on
PipeRench predicts that it will outperform commercial FPGAs and
DSPs in both overall performance and in performance normalized
for silicon area over a broad range of problem sizes.},
number = {4},
url = {http://www.cs.cmu.edu/~seth/papers/schmit-jvlsi00.pdf},
doi = {},
also = {chapter in Field-Programmable Custom Computing Technology:
Architecture, Tools, and Applications},
keywords = {PipeRench,Reconfigurable Computing}
}
|
|
PipeRench: A Reconfigurable Architecture and Compiler | pdf bib abstract | |
Seth Copen Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matthew Moe, and R. Reed Taylor.
IEEE Computer,
33(4):70–77,April, 2000.
|
| hide Abstract | With the proliferation of highly specialized embedded computer systems has come a diversification of workloads for computing devices. General-purpose processors are struggling to efficiently meet these applications’ disparate needs, and custom hardware is rarely feasible. According to the authors, reconfigurable computing, which combines the flexibility of general-purpose processors with the efficiency of custom hardware, can provide the alternative. PipeRench and its associated compiler comprise the authors’ new architecture for reconfigurable computing. Combined with a traditional digital signal processor, microcontroller or general-purpose processor, PipeRench can support a system’s various computing needs without requiring custom hardware. The authors describe the PipeRench architecture and how it solves some of the pre-existing problems with FPGA architectures, such as logic granularity, configuration time, forward compatibility, hard constraints and compilation time. |
| | @article{goldstein-ieee00,
author = {Goldstein, Seth Copen and Schmit, Herman and Budiu, Mihai
and Cadambi, Srihari and Moe, Matthew and Taylor, R. Reed},
title = {{PipeRench}: A Reconfigurable Architecture and Compiler},
journal = {IEEE Computer},
year = {2000},
volume = {33},
number = {4},
month = {April},
pages = {70--77},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-ieee00.pdf},
abstract = {With the proliferation of highly specialized embedded
computer systems has come a diversification of workloads for
computing devices. General-purpose processors are struggling to
efficiently meet these applications' disparate needs, and custom
hardware is rarely feasible. According to the authors,
reconfigurable computing, which combines the flexibility of
general-purpose processors with the efficiency of custom
hardware, can provide the alternative. PipeRench and its
associated compiler comprise the authors' new architecture for
reconfigurable computing. Combined with a traditional digital
signal processor, microcontroller or general-purpose processor,
PipeRench can support a system's various computing needs without
requiring custom hardware. The authors describe the PipeRench
architecture and how it solves some of the pre-existing problems
with FPGA architectures, such as logic granularity, configuration
time, forward compatibility, hard constraints and compilation
time.},
keywords = {Reconfigurable Computing,PipeRench}
}
|
|
Tunable Fault Tolerance for Runtime Reconfigurable Architectures | pdf bib abstract | |
Steven K. Sinha, Peter M. Kamarchik, and Seth Copen Goldstein.
In 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000),
pages 185–192, April, 2000.
|
| hide Abstract | Fault tolerance is becoming an increasingly important issue, especially in mission-critical applications where data integrity is a paramount concern. Performance, however, remains a large driving force in the market place. Runtime reconfigurable hardware architectures have the power to balance fault tolerance with performance, allowing the amount of fault tolerance to be tuned at run-time. This paper describes a new built-in self-test designed to run on, and take advantage of, runtime reconfigurable architectures using the PipeRench architecture as a model. In addition, this paper introduces a new metric by which a user can set the desired fault tolerance of a runtime reconfigurable device |
| | @inproceedings{sinha-fccm00,
title = {Tunable Fault Tolerance for Runtime Reconfigurable
Architectures},
url = {http://www.cs.cmu.edu/~seth/papers/sinha-fccm00.pdf},
booktitle = {8th IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM 2000)},
author = {Sinha, Steven K. and Kamarchik, Peter M. and Goldstein,
Seth Copen},
abstract = {Fault tolerance is becoming an increasingly important
issue, especially in mission-critical applications where data
integrity is a paramount concern. Performance, however, remains a
large driving force in the market place. Runtime reconfigurable
hardware architectures have the power to balance fault tolerance
with performance, allowing the amount of fault tolerance to be
tuned at run-time. This paper describes a new built-in self-test
designed to run on, and take advantage of, runtime reconfigurable
architectures using the PipeRench architecture as a model. In
addition, this paper introduces a new metric by which a user can
set the desired fault tolerance of a runtime reconfigurable
device},
doi = {10.1109/FPGA.2000.903405},
year = {2000},
pages = {185-192},
isbn = {0-7695-0871-5},
address = {Napa Valley, CA},
month = {April},
keywords = {Fault And Defect Tolerance,PipeRench,Reconfigurable
Computing}
}
|
1999 |
A High-Performance Flexible Architecture for Cryptography | pdf bib abstract | |
R. Reed Taylor and Seth Copen Goldstein.
In Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems 1999 (CHES99),
pages 231–245, August, 1999.
|
| hide Abstract | Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on general-purpose processors. However, systems which use hardware implementations have significant drawbacks: they are unable to respond to flaws discovered in the implemented algorithm or to changes in standards. In this paper we show how reconfigurable computing offers high performance yet flexible solutions for cryptographic algorithms. We focus on PipeRench, a reconfigurable fabric that supports implementations which can yield better than custom-hardware performance and yet maintains all the flexibility of software based systems. PipeRench is a pipelined reconfigurable fabric which virtualizes hardware, enabling large circuits to be run on limited physical hardware. We present implementations for Crypton, IDEA, RC6, and Twofish on PipeRench and an extension of PipeRench, PipeRench+. We also describe how various proposed AES algorithms could be implemented on PipeRench. PipeRench achieves speedups of between 2x and 12x over conventional processors. |
| | @inproceedings{reed-ches99,
author = {Taylor, R. Reed and Goldstein, Seth Copen},
title = {A High-Performance Flexible Architecture for Cryptography},
booktitle = {Proceedings of the Workshop on Cryptographic Hardware
and Embedded Systems 1999 (CHES99)},
address = {Worcester, MA},
year = {1999},
pages = {231-245},
month = {August},
abstract = {Cryptographic algorithms are more efficiently
implemented in custom hardware than in software running on
general-purpose processors. However, systems which use hardware
implementations have significant drawbacks: they are unable to
respond to flaws discovered in the implemented algorithm or to
changes in standards. In this paper we show how reconfigurable
computing offers high performance yet flexible solutions for
cryptographic algorithms. We focus on PipeRench, a reconfigurable
fabric that supports implementations which can yield better than
custom-hardware performance and yet maintains all the flexibility
of software based systems. PipeRench is a pipelined
reconfigurable fabric which virtualizes hardware, enabling large
circuits to be run on limited physical hardware. We present
implementations for Crypton, IDEA, RC6, and Twofish on PipeRench
and an extension of PipeRench, PipeRench+. We also describe how
various proposed AES algorithms could be implemented on
PipeRench. PipeRench achieves speedups of between 2x and 12x over
conventional processors.},
url = {http://www.cs.cmu.edu/~seth/papers/reed-ches99.pdf},
keywords = {PipeRench,Reconfigurable Computing}
}
|
|
PipeRench: a Coprocessor for Streaming Multimedia Acceleration | pdf bib abstract | |
Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, and Ronald Laufer.
In Proceedings of the 26th International Symposium on Computer Architecture (ISCA),
pages 28–39, May, 1999.
|
| hide Abstract | Future computing workloads will emphasize an architecture’s ability to perform relatively simple calculations on massive quantities of mixed-width data. This paper describes a novel reconfigurable fabric architecture, PipeRench, optimized to accelerate these types of computations. PipeRench enables fast, robust compilers, supports forward compatibility, and virtualizes configurations, thus removing the fixed size constraint present in other fabrics. For the first time we explore how the bit-width of processing elements affects performance and show how the PipeRench architecture has been optimized to balance the needs of the compiler against the realities of silicon. Finally, we demonstrate extreme performance speedup on certain computing kernels (up to 190x versus a modern RISC processor), and analyze how this acceleration translates to application speedup. |
| | @inproceedings{goldstein-isca99,
author = {Goldstein, Seth Copen and Schmit, Herman and Moe, Matthew
and Budiu, Mihai and Cadambi, Srihari and Taylor, R. Reed and
Laufer, Ronald},
title = {{PipeRench}: a Coprocessor for Streaming Multimedia
Acceleration},
booktitle = {Proceedings of the 26th International Symposium on
Computer Architecture (ISCA)},
month = {May},
year = {1999},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca99.pdf},
pages = {28--39},
abstract = {Future computing workloads will emphasize an
architecture's ability to perform relatively simple calculations
on massive quantities of mixed-width data. This paper describes a
novel reconfigurable fabric architecture, PipeRench, optimized to
accelerate these types of computations. PipeRench enables fast,
robust compilers, supports forward compatibility, and virtualizes
configurations, thus removing the fixed size constraint present
in other fabrics. For the first time we explore how the bit-width
of processing elements affects performance and show how the
PipeRench architecture has been optimized to balance the needs of
the compiler against the realities of silicon. Finally, we
demonstrate extreme performance speedup on certain computing
kernels (up to 190x versus a modern RISC processor), and analyze
how this acceleration translates to application speedup.},
address = {Atlanta, GA},
keywords = {Reconfigurable Computing,PipeRench}
}
|
|
CPR: A Configuration Profiling Tool | pdf bib | |
Srihari Cadambi and Seth Copen Goldstein.
In 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99),
pages 104, April, 1999.
|
| @inproceedings{cadambi-fccm99,
title = {CPR: A Configuration Profiling Tool},
url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fccm99.pdf},
booktitle = {7th Annual IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM '99)},
author = {Cadambi, Srihari and Goldstein, Seth Copen},
year = {1999},
pages = {104},
address = {Napa Valley, CA},
month = {April},
keywords = {CAD,Reconfigurable Computing,Place And Route}
}
|
|
Fast Compilation for Pipelined Reconfigurable Fabrics | pdf bib abstract | |
Mihai Budiu and Seth Copen Goldstein.
In Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays (FPGA '99),
pages 195–205, February, 1999.
|
| hide Abstract | In this paper we describe a compiler which quickly synthesizes high quality pipelined datapaths for pipelined reconfigurable devices. The compiler uses the same internal representation to perform synthesis, module generation, optimization, and place and route. The core of the compiler is a linear time place and route algorithm more than two orders of magnitude faster than traditional CAD tools. The key behind our approach is that we never backtrack, rip-up, or re-route. Instead, the graph representing the computation is preprocessed to guarantee routability by inserting lazy noops. The preprocessing steps provides enough information to make a greedy strategy feasible. The compilation speed is approximately 3000 bit-operations/second (on a PII/400Mhz) for a wide range of applications. The hardware utilization averages 60% on the target device, PipeRench. |
| | @inproceedings{budiu-fpga99,
author = {Budiu, Mihai and Goldstein, Seth Copen},
title = {Fast Compilation for Pipelined Reconfigurable Fabrics},
booktitle = {Proceedings of the 1999 ACM/SIGDA Seventh International
Symposium on Field Programmable Gate Arrays (FPGA '99)},
month = {February},
year = {1999},
pages = {195-205},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-fpga99.pdf},
abstract = {In this paper we describe a compiler which quickly
synthesizes high quality pipelined datapaths for pipelined
reconfigurable devices. The compiler uses the same internal
representation to perform synthesis, module generation,
optimization, and place and route. The core of the compiler is a
linear time place and route algorithm more than two orders of
magnitude faster than traditional CAD tools. The key behind our
approach is that we never backtrack, rip-up, or re-route.
Instead, the graph representing the computation is preprocessed
to guarantee routability by inserting lazy noops. The
preprocessing steps provides enough information to make a greedy
strategy feasible. The compilation speed is approximately 3000
bit-operations/second (on a PII/400Mhz) for a wide range of
applications. The hardware utilization averages 60\% on the
target device, PipeRench.},
keywords = {Reconfigurable Computing,PipeRench,Place and Route}
}
|
1998 |
The Lazy Multithreaded Implementation Design Space | bib | |
Seth Copen Goldstein and David E. Culler.
In The Yale Multithreaded Workshop,
June, 1998.
|
| @inproceedings{goldstein-ymw98,
title = {The Lazy Multithreaded Implementation Design Space},
booktitle = {The Yale Multithreaded Workshop},
author = {Goldstein, Seth Copen and Culler, David E.},
address = {New Haven, CT},
year = {1998},
month = {June},
keywords = {Lazy Threads,Parallel Computing}
}
|
|
Tunable Fault Tolernace via Test and Reconfiguration | pdf bib | |
Shawn Blanton, Seth Copen Goldstein, and Herman Schmit.
In Digest of FastAbstracts of the 28th Annual International Symposium on Fault-Tolerant Computing,
pages 9–10, June, 1998.
|
| @inproceedings{blanton-ftc98,
author = {Blanton, Shawn and Goldstein, Seth Copen and Schmit,
Herman},
title = {Tunable Fault Tolernace via Test and Reconfiguration},
booktitle = {Digest of FastAbstracts of the 28th Annual
International Symposium on Fault-Tolerant Computing},
year = {1998},
month = {June},
pages = {9--10},
keywords = {PipeRench, Fault and Defect Tolerance},
url = {http://www.cs.cmu.edu/~seth/papers/blanton-ftc98.pdf}
}
|
|
Characterization and Parameterization of a Pipeline Reconfigurable FGPA | pdf bib | |
Matthew Moe, Herman Schmit, and Seth Copen Goldstein.
In 6th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98),
pages 294–295, April, 1998.
|
| @inproceedings{moe-fccm98,
author = {Moe, Matthew and Schmit, Herman and Goldstein, Seth
Copen},
title = {{Characterization and Parameterization of a Pipeline
Reconfigurable {FGPA}}},
booktitle = {6th Annual IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM '98)},
month = {April},
address = {Napa, CA},
year = {1998},
pages = {294--295},
keywords = {PipeRench, Reconfigurable Computing},
url = {http://www.cs.cmu.edu/~seth/papers/moe-fccm98.pdf}
}
|
|
Managing pipeline-reconfigurable FPGAs | pdf bib abstract | |
Srihari Cadambi, J. Weener, Seth Copen Goldstein, Herman Schmit, and Donald E Thomas.
In Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays,
pages 55–64, February, 1998.
|
| hide Abstract | While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. In this paper we describe the benefits of hardware virtualization, and show how it can be acheived using a combination of pipeline reconfiguration and run-time scheduling of both configuration streams and data streams. The result is PipeRench, an architecture that supports robust compilation and provides forward compatibility. Our preliminary performance analysis predicts that PipeRench will outperform commercial FPGAs and DSPs in both overall performance and in performance per mm2. |
| | @inproceedings{cadambi-fpga98,
author = {Cadambi, Srihari and Weener, J. and Goldstein, Seth Copen
and Schmit, Herman and Thomas, Donald E},
title = {{Managing pipeline-reconfigurable FPGAs}},
booktitle = {Proceedings of the 1998 ACM/SIGDA Sixth International
Symposium on Field Programmable Gate Arrays},
year = {1998},
month = {February},
pages = {55--64},
address = {Monterey, CA},
abstract = {While reconfigurable computing promises to deliver
incomparable performance, it is still a marginal technology due
to the high cost of developing and upgrading applications.
Hardware virtualization can be used to significantly reduce both
these costs. In this paper we describe the benefits of hardware
virtualization, and show how it can be acheived using a
combination of pipeline reconfiguration and run-time scheduling
of both configuration streams and data streams. The result is
PipeRench, an architecture that supports robust compilation and
provides forward compatibility. Our preliminary performance
analysis predicts that PipeRench will outperform commercial FPGAs
and DSPs in both overall performance and in performance per
mm$^2$.},
keywords = {PipeRench, Reconfigurable Computing},
url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpga98.pdf}
}
|
1997 |
Lazy Threads Compiler and Runtime Structures for Fine-Grained Parallel Programming | pdf bib | |
Seth Copen Goldstein.
PhD Thesis, University of California--Berkeley,
1997.
|
| @phdthesis{goldstein-phd97,
title = {Lazy Threads Compiler and Runtime Structures for
Fine-Grained Parallel Programming},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-phd97.pdf},
author = {Goldstein, Seth Copen},
school = {University of California--Berkeley},
year = {1997},
address = {Berkeley, CA},
keywords = {Lazy Threads,Parallel Computing,Split-C,Threaded
Abstract Machine (TAM)}
}
|
|
Order-sorted feature theory unification | pdf bib abstract | |
Ait-Kaci Hassan, Andreas Podelski, and Seth Copen Goldstein.
The Journal of Logic Programming,
30(2):99–124,February, 1997.
Also appeared as Proceedings of the International Symposium on Logic Programming (ILPS), 1993 and as DEC Technical Report PRL-RR-32.
|
| hide Abstract | Order-sorted feature (OSF) terms provide an adequate representation for objects as flexible records. They are sorted, attributed, possibly nested structures, ordered thanks to a subsort ordering. Sorts definitions offer the functionality of classes imposing structural constraints on objects. These constraints involve variable sorting and equations among feature paths, including self-reference. Formally, sort definitions may be seen as axioms forming an OSF theory. OSF theory unification is the process of normalizing an OSF term taking into account sort definitions, enforcing structural constraints imposed by an OSF theory. It allows objects to inherit, and thus abide by, constraints from their classes. We propose a formal system that logically models record objects with (possibly recursive) class definitions accommodating multiple inheritance. We show that OSF theory unification is undecidable in general. However, we give a set of confluent normalization rules which is complete for detecting the inconsistency of an object with respect to an OSF theory. Furthermore, a subset consisting of all rules but one is confluent and terminating. This yields a practical complete normalization strategy, as well as an effective compilation scheme. |
| | @article{ait-kaci-jlp97,
author = {Hassan, Ait-Kaci and Podelski, Andreas and Goldstein, Seth
Copen},
title = {Order-sorted feature theory unification},
journal = {The Journal of Logic Programming},
volume = {30},
month = {February},
year = {1997},
abstract = {Order-sorted feature (OSF) terms provide an adequate
representation for objects as flexible records. They are sorted,
attributed, possibly nested structures, ordered thanks to a
subsort ordering. Sorts definitions offer the functionality of
classes imposing structural constraints on objects. These
constraints involve variable sorting and equations among feature
paths, including self-reference. Formally, sort definitions may
be seen as axioms forming an OSF theory. OSF theory unification
is the process of normalizing an OSF term taking into account
sort definitions, enforcing structural constraints imposed by an
OSF theory. It allows objects to inherit, and thus abide by,
constraints from their classes. We propose a formal system that
logically models record objects with (possibly recursive) class
definitions accommodating multiple inheritance. We show that OSF
theory unification is undecidable in general. However, we give a
set of confluent normalization rules which is complete for
detecting the inconsistency of an object with respect to an OSF
theory. Furthermore, a subset consisting of all rules but one is
confluent and terminating. This yields a practical complete
normalization strategy, as well as an effective compilation
scheme.},
pages = {99--124},
number = {2},
url = {http://www.cs.cmu.edu/~seth/papers/ait-kaci-jlp97.pdf},
doi = {doi:10.1016/S0743-1066(96)00053-2},
also = {Proceedings of the International Symposium on Logic
Programming (ILPS), 1993 and as DEC Technical Report PRL-RR-32},
keywords = {Logic Programming}
}
|
1996 |
Lazy threads: implementing a fast parallel call | pdf bib abstract | |
Seth Copen Goldstein, Klaus Erik Schauser, and David E. Culler.
Journal of Parallel and Distributed Computing,
37(1):5–20,1996.
|
| hide Abstract | In this paper, we describe lazy threads, a new approach for implementing multithreaded execution models on conventional machines. We show how they can implement a parallel call at nearly the efficiency of a sequential call. The central idea is to specialize the representation of a parallel call so that it can execute as a parallel-ready sequential call. This allows excess parallelism to degrade into sequential calls with the attendant efficient stack management and direct transfer of control and data, yet a call that truly needs to execute in parallel, gets its own thread of control. The efficiency of lazy threads is achieved through a careful attention to storage management and a code generation strategy that allows us to represent potential parallel work with no overhead. |
| | @article{goldstein96-jpdc,
author = {Goldstein, Seth Copen and Schauser, Klaus Erik and Culler,
David E.},
title = {Lazy threads: implementing a fast parallel call},
journal = {Journal of Parallel and Distributed Computing},
volume = {37},
number = {1},
year = {1996},
pages = {5--20},
publisher = {Academic Press, Inc.},
address = {Orlando, FL, USA},
keywords = {Lazy Threads, Parallel Computing},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein96-jpdc.pdf},
abstract = {In this paper, we describe lazy threads, a new approach
for implementing multithreaded execution models on conventional
machines. We show how they can implement a parallel call at
nearly the efficiency of a sequential call. The central idea is
to specialize the representation of a parallel call so that it
can execute as a parallel-ready sequential call. This allows
excess parallelism to degrade into sequential calls with the
attendant efficient stack management and direct transfer of
control and data, yet a call that truly needs to execute in
parallel, gets its own thread of control. The efficiency of lazy
threads is achieved through a careful attention to storage
management and a code generation strategy that allows us to
represent potential parallel work with no overhead.}
}
|
1995 |
Lazy Threads, Stacklets, and Synchronizers: Enabling primitives for compiling parallel languages | bib | |
Seth Copen Goldstein, David E. Culler, and Klaus Erik Schauser.
University of California at Berkeley Technical Report,
1995.
|
| @techreport{GSC95,
author = {Goldstein, Seth Copen and Culler, David E. and Schauser,
Klaus Erik},
title = {{Lazy Threads, Stacklets, and Synchronizers: Enabling
primitives for compiling parallel languages}},
institution = {University of California at Berkeley},
year = {1995},
keywords = {Lazy Threads, Parallel Computing}
}
|
|
How Much Non-Strictness Do Lenient Programs Require? | pdf bib | |
Klaus Erik Schauser and Seth Copen Goldstein.
In Conference on Functional Programming Languages and Computer Architecture,
June, 1995.
|
| @inproceedings{schauser-fplca95,
title = {How Much Non-Strictness Do Lenient Programs Require?},
url = {http://www.cs.cmu.edu/~seth/papers/schauser-fplca95.pdf},
booktitle = {Conference on Functional Programming Languages and
Computer Architecture},
author = {Schauser, Klaus Erik and Goldstein, Seth Copen},
address = {La Jolla, CA},
year = {1995},
month = {June},
keywords = {Functional Programming, Parallel Computing}
}
|
|
NIFDY: A Low Overhead, High Throughput Network Interface | pdf bib | |
Timothy J Callahan and Seth Copen Goldstein.
In Proceedings of the 22nd International Symposium on Computer Architecture,
June, 1995.
|
| @inproceedings{callahan-isca95,
title = {NIFDY: A Low Overhead, High Throughput Network Interface},
url = {http://www.cs.cmu.edu/~seth/papers/callahan-isca95.pdf},
booktitle = {Proceedings of the 22nd International Symposium on
Computer Architecture},
author = {Callahan, Timothy J and Goldstein, Seth Copen},
address = {Santa Margherita Ligure, Italy},
year = {1995},
month = {June},
keywords = {parallel Computing, NIFDY}
}
|
|
Enabling Primitives for Compiling Parallel Languages | pdf bib | |
Seth Copen Goldstein, David E. Culler, and Klaus Erik Schauser.
In Third Workshop on Languages, Compilers, and Run-Time Systems for Scalable Computers,
May, 1995.
|
| @inproceedings{goldstein-lcr95,
title = {Enabling Primitives for Compiling Parallel Languages},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-lcr95.pdf},
booktitle = {Third Workshop on Languages, Compilers, and Run-Time
Systems for Scalable Computers},
author = {Goldstein, Seth Copen and Culler, David E. and Schauser,
Klaus Erik},
address = {Rochester, NY},
year = {1995},
month = {May},
keywords = {Parallel Computing,Lazy Threads}
}
|
|
Introduction to Split-C | pdf bib | |
David E. Culler, Andrea Dusseau, Seth Copen Goldstein, Arvind Krishnamurthy, Steven Lumetta, Thorsten von Eicken, and Katherine Yelick.
University of California--Berkeley Technical Report,
April, 1995.
|
| @techreport{dusseau-tr92,
title = {Introduction to Split-C},
url = {http://www.cs.cmu.edu/~seth/papers/dusseau-tr92.pdf},
author = {Culler, David E. and Dusseau, Andrea and Goldstein, Seth
Copen and Krishnamurthy, Arvind and Lumetta, Steven and
von~Eicken, Thorsten and Yelick, Katherine},
month = {April},
institution = {University of California--Berkeley},
year = {1995},
keywords = {Parallel Computing,Split-C}
}
|
|
Separation Constraint Partitioning --- A New Algorithm for Partitioning non-Strict Programs Into Sequential Threads | pdf bib | |
Klaus Erik Schauser, David E. Culler, and Seth Copen Goldstein.
In Proceedings of the Principles of Programming Languages,
January, 1995.
|
| @inproceedings{SCG95,
author = {Schauser, Klaus Erik and Culler, David E. and Goldstein,
Seth Copen},
booktitle = {Proceedings of the Principles of Programming
Languages},
title = {Separation Constraint Partitioning --- A New Algorithm for
Partitioning non-Strict Programs Into Sequential Threads},
year = {1995},
address = {San Francisco, CA},
month = {January},
keywords = {Parallel Computing},
url = {http://www.cs.cmu.edu/~seth/papers/SCG95.pdf}
}
|
1994 |
The Implementation of a Threaded Abstract Machine | pdf bib | |
Seth Copen Goldstein.
EECS Department, University of California, Berkeley Technical Report No. UCB/CSD-94-818,
1994.
See goldstein94.
|
| @techreport{goldstein-tr94,
author = {Goldstein, Seth Copen},
title = {The Implementation of a Threaded Abstract Machine},
institution = {EECS Department, University of California, Berkeley},
year = {1994},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-tr94.pdf},
number = {UCB/CSD-94-818},
see = {goldstein94},
keywords = {Threaded Abstract Machine (TAM)}
}
|
|
The Implementation of a Threaded Abstract Machine | bib | |
Seth Copen Goldstein.
Master's Thesis, University of California at Berkeley,
May, 1994.
Also appeared as UC-Berkeley Technical Report UCB/CSD-94-818.
|
| @mastersthesis{goldstein94,
author = {Goldstein, Seth Copen},
title = {The Implementation of a Threaded Abstract Machine},
school = {University of California at Berkeley},
year = {1994},
address = {Computer Science Division, University of California,
Berkeley, Ca 94720},
month = {May},
also = {UC-Berkeley Technical Report UCB/CSD-94-818},
keywords = {Parallel Computing, Threaded Abstract Machine (TAM)}
}
|
|
Active Messages: A Communication Foundation for Parallel Programming Models | bib | |
Seth Copen Goldstein.
In CM-5 Users Group,
February, 1994.
|
| @misc{goldstein-cm5users94,
title = {Active Messages: A Communication Foundation for Parallel
Programming Models},
howpublished = {CM-5 Users Group},
author = {Goldstein, Seth Copen},
address = {Santa Fe, NM},
year = {1994},
month = {February},
keywords = {Active Messages,Parallel Computing}
}
|
1993 |
Order-sorted feature theory unification | pdf bib | |
Ait-Kaci Hassan, Andreas Podelski, and Seth Copen Goldstein.
DEC Paris Research Labs Technical Report No. PRL-RR-32,
1993.
See ait-kaci-jlp97.
|
| @techreport{ait-kaci-prl93,
author = {Hassan, Ait-Kaci and Podelski, Andreas and Goldstein, Seth
Copen},
title = {Order-sorted feature theory unification},
institution = {DEC Paris Research Labs},
number = {PRL-RR-32},
year = {1993},
see = {ait-kaci-jlp97},
keywords = {Logic Programming},
url = {http://www.cs.cmu.edu/~seth/papers/ait-kaci-prl93.pdf}
}
|
|
Parallel Programming in Split-C | pdf bib | |
David E. Culler, Andrea Dusseau, Seth Copen Goldstein, Arvind Krishnamurthy, Steven Lumetta, Thorsten von Eicken, and Katherine Yelick.
In Proceedings of the Supercomputing '93 Conference,
pages 262–273, November, 1993.
|
| @inproceedings{culler-sc93,
author = {Culler, David E. and Dusseau, Andrea and Goldstein, Seth
Copen and Krishnamurthy, Arvind and Lumetta, Steven and
von~Eicken, Thorsten and Yelick, Katherine},
title = {Parallel Programming in Split-C},
booktitle = {Proceedings of the Supercomputing '93 Conference},
pages = {262-273},
year = {1993},
address = {Portland, OR},
month = {November},
keywords = {Active Messages,Parallel Computing},
url = {http://www.cs.cmu.edu/~seth/papers/culler-sc93.pdf}
}
|
|
TAM --- a compiler controlled threaded abstract machine | pdf bib abstract | |
David E. Culler, Seth Copen Goldstein, Klaus Erik Schauser, and Thorsten von Eicken.
Journal of Parallel and Distributed Computing,
volume 18, pages 347–370,July, 1993.
|
| hide Abstract | The Threaded Abstract Machine (TAM) refines dataflow execution models to address the critical constraints that modern parallel architectures place on the compilation of general-purpose parallel programming languages. TAM defines a self-scheduled machine language of parallel threads, which provides a path from dataflow-graph program representations to conventional control flow. The most important feature of TAM is the way it exposes the interaction between the handling of asynchronous message events, the scheduling of computation, and the utilization of the storage hierarchy. This paper provides a complete description of TAM and codifies the model in terms of a pseudo machine language TL0. Issues in compilation from a high level parallel language to TL0 are discussed in general and specifically in regard to the Id90 language. The implementation of TL0 on the CM-5 multiprocessor is explained in detail. Using this implementation, a cost model is developed for the various TAM primitives. The TAM approach is evaluated on sizable Id90 programs on a 64 processor system. The scheduling hierarchy of quanta and threads is shown to provide substantial locality while tolerating long latencies. This allows the average thread scheduling cost to be extremely low. |
| | @article{CullerGSvE93,
author = {Culler, David E. and Goldstein, Seth Copen and Schauser,
Klaus Erik and von~Eicken, Thorsten},
title = {{TAM --- a compiler controlled threaded abstract machine}},
journal = {Journal of Parallel and Distributed Computing},
year = {1993},
volume = {18},
pages = {347-370},
month = {July},
abstract = {The Threaded Abstract Machine (TAM) refines dataflow
execution models to address the critical constraints that modern
parallel architectures place on the compilation of
general-purpose parallel programming languages. TAM defines a
self-scheduled machine language of parallel threads, which
provides a path from dataflow-graph program representations to
conventional control flow. The most important feature of TAM is
the way it exposes the interaction between the handling of
asynchronous message events, the scheduling of computation, and
the utilization of the storage hierarchy. This paper provides a
complete description of TAM and codifies the model in terms of a
pseudo machine language TL0. Issues in compilation from a high
level parallel language to TL0 are discussed in general and
specifically in regard to the Id90 language. The implementation
of TL0 on the CM-5 multiprocessor is explained in detail. Using
this implementation, a cost model is developed for the various
TAM primitives. The TAM approach is evaluated on sizable Id90
programs on a 64 processor system. The scheduling hierarchy of
quanta and threads is shown to provide substantial locality while
tolerating long latencies. This allows the average thread
scheduling cost to be extremely low.},
url = {http://www.cs.cmu.edu/~seth/papers/CullerGSvE93.pdf},
keywords = {Active Messages, Parallel Computing,Threaded Abstract
Machine (TAM)}
}
|
|
Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5 | pdf bib | |
Ellen Spertus, Seth Copen Goldstein, Klaus Erik Schauser, Thorsten von Eicken, David E. Culler, and William J. Dally.
In Proceedings of the 20th International Symposium on Computer Architecture (ISCA),
May, 1993.
|
| @inproceedings{SpertusGSvECD93,
author = {Spertus, Ellen and Goldstein, Seth Copen and Schauser,
Klaus Erik and von~Eicken, Thorsten and Culler, David E. and
Dally, William J.},
title = {{Evaluation of Mechanisms for Fine-Grained Parallel
Programs in the J-Machine and the CM-5}},
booktitle = {Proceedings of the 20th International Symposium on
Computer Architecture (ISCA)},
address = {San Diego, CA},
month = {May},
year = {1993},
keywords = {Active Messages, Parallel Computing,Threaded Abstract
Machine (TAM)},
url = {http://www.cs.cmu.edu/~seth/papers/SpertusGSvECD93.pdf}
}
|
1992 |
An Abstract Machine to Implement Functions in LIFE | pdf bib | |
Seth Copen Goldstein.
DEC Paris Research Lab Technical Report No. Note 18,
1992.
|
| @techreport{goldstein-prl92,
author = {Goldstein, Seth Copen},
title = {An Abstract Machine to Implement Functions in LIFE},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-prl92.pdf},
institution = {DEC Paris Research Lab},
year = {1992},
number = {Note 18},
keywords = {Logic Programming}
}
|
|
Studying Dynamic Program Behavior `In the Large' | bib | |
Seth Copen Goldstein.
In ID Workshop,
November, 1992.
|
| @inproceedings{goldstein-id92,
title = {Studying Dynamic Program Behavior `In the Large'},
booktitle = {ID Workshop},
author = {Goldstein, Seth Copen},
address = {Minneapolis, MN},
year = {1992},
month = {November},
keywords = {Parallel Computing,Threaded Abstract Machine (TAM),
Id90}
}
|
|
Active Messages: A Mechanism for Integrated Communication and Computation | pdf bib abstract | |
Thorsten von Eicken, David E. Culler, Seth Copen Goldstein, and Klaus Erik Schauser.
In Proceedings of the 19th International Symposium on Computer Architecture (ISCA),
pages 430–440, May, 1992.
|
| hide Abstract | The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without sacrificing processor cost/performance. We show that existing message passing multiprocessors have unnecessarily high communication costs. Research prototypes of message driven machines demonstrate low communication overhead, but poor processor cost/performance. We introduce a simple communication mechanism, Active Messages, show that it is intrinsic to both architectures, allows cost effective use of the hardware, and offers tremendous flexibility. Implementations on nCUBE/2 and CM-5 are described and evaluated using a split-phase shared-memory extension to C, Split-C. We further show that active messages are sufficient to implement the dynamically scheduled languages for which message driven machines were designed. With this mechanism, latency tolerance becomes a programming/compiling concern. Hardware support for active messages is desirable and we outline a range of enhancements to mainstream processors. |
| | @inproceedings{voneicken-isca92,
author = {von~Eicken, Thorsten and Culler, David E. and Goldstein,
Seth Copen and Schauser, Klaus Erik},
title = {{Active Messages}: A Mechanism for Integrated Communication
and Computation},
month = {May},
booktitle = {Proceedings of the 19th International Symposium on
Computer Architecture (ISCA)},
address = {Gold Coast, Australia},
pages = {430--440},
year = {1992},
url = {http://www.cs.cmu.edu/~seth/papers/voneicken-isca92.pdf},
abstract = {The design challenge for large-scale multiprocessors is
(1) to minimize communication overhead, (2) allow communication
to overlap computation, and (3) coordinate the two without
sacrificing processor cost/performance. We show that existing
message passing multiprocessors have unnecessarily high
communication costs. Research prototypes of message driven
machines demonstrate low communication overhead, but poor
processor cost/performance. We introduce a simple communication
mechanism, {\em Active Messages}, show that it is intrinsic to
both architectures, allows cost effective use of the hardware,
and offers tremendous flexibility. Implementations on nCUBE/2 and
CM-5 are described and evaluated using a split-phase
shared-memory extension to C, {\em Split-C}. We further show that
active messages are sufficient to implement the dynamically
scheduled languages for which message driven machines were
designed. With this mechanism, latency tolerance becomes a
programming/compiling concern. Hardware support for active
messages is desirable and we outline a range of enhancements to
mainstream processors.},
keywords = {Active Messages, Parallel Computing}
}
|
|
Empirical Study of a Dataflow Language on the CM-5 | pdf bib | |
David E. Culler, Seth Copen Goldstein, Klaus Erik Schauser, and Thorsten von Eicken.
In Proc. of the Dataflow Workshop, 19th Int'l Symposium on Computer Architecture,
pages 187–210, May, 1992.
|
| @inproceedings{culler-wdc92,
author = {Culler, David E. and Goldstein, Seth Copen and Schauser,
Klaus Erik and von~Eicken, Thorsten},
title = {{Empirical Study of a Dataflow Language on the CM-5}},
booktitle = {Proc. of the Dataflow Workshop, 19th Int'l Symposium on
Computer Architecture},
address = {Gold Coast, Australia},
month = {May},
year = {1992},
pages = {187--210},
keywords = {Parallel Computing,Threaded Abstract Machine (TAM),
Id90, Dataflow},
url = {http://www.cs.cmu.edu/~seth/papers/culler-wdc92.pdf}
}
|
|
Supporting Implicitly Parallel Languages | bib | |
Seth Copen Goldstein.
In 14th Annual Industrial Liaison Program Conference,
March, 1992.
|
| @inproceedings{goldstein-ilpc92,
title = {Supporting Implicitly Parallel Languages},
booktitle = {14th Annual Industrial Liaison Program Conference},
author = {Goldstein, Seth Copen},
address = {Berkeley, CA},
year = {1992},
month = {March},
keywords = {Parallel Computing,Threaded Abstract Machine (TAM),
Id90}
}
|
1991 |
Hardware-Assisted Replay of Multiprocessor Programs | pdf bib | |
David F. Bacon and Seth Copen Goldstein.
In Proceedings of the ACM/ONR Workshop on Parallel and Distributed Debugging,
May, 1991.
|
| @inproceedings{bacon-wpdd91,
title = {Hardware-Assisted Replay of Multiprocessor Programs},
url = {http://www.cs.cmu.edu/~seth/papers/bacon-wpdd91.pdf},
booktitle = {Proceedings of the ACM/ONR Workshop on Parallel and
Distributed Debugging},
author = {Bacon, David F. and Goldstein, Seth Copen},
year = {1991},
address = {Santa Cruz, CA},
month = {May},
keywords = {Debugging,Parallel Computing}
}
|
1990 |
The Future of Object-Oriented Programming | bib | |
Seth Copen Goldstein.
In TOOLS 1990,
May, 1990.
|
| @inproceedings{goldstein-tools90,
title = {The Future of Object-Oriented Programming},
booktitle = {TOOLS 1990},
author = {Goldstein, Seth Copen},
address = {Paris, France},
year = {1990},
month = {May},
keywords = {Object-Oriented Programming}
}
|
|