Abstract: Design validation is rapidly becoming a limiter in designing new microprocessors. Not only is the resource requirements escalating rapidly, the coverage of the validation performed is also rapidly diminishing, as the designs are becoming ever more concurrent and complex. In this context, a new way of doing the design is critically needed. In this talk we introduce the Integrated Design and Validation (IDV) thrust currently pursued in Strategic CAD Labs at Intel Corp. In IDV the design and validation efforts are tied together so that when the design is completed, then so is the implementation validation (did we implement what we intended). Furthermore, the design validation (did we capture what we actually wanted) is significantly simplified since it has to be done on a much smaller and much more stable model.

Biography: Dr. Carl Seger received his Ph.D. degree in Computer Science from University of Waterloo, Canada, in 1988. After an academic career at Carnegie Mellon and the University of British Columbia, ending as Associate Professor, he joined Intel in 1995 and is now a Senior Principal Engineer in Design Technology's Strategic CAD Labs. His main research interests are formal hardware verification and asynchronous circuits. Recently, he has baranched out and is now working on developing new design flows that integrate the validation effort with the design effort. He is the author of the Forte (nee Voss) formal verification system and has published over 40 papers and books and holds 4 patents.