Three-Dimensional Monte Carlo Semiconductor Device Simulation

H. Sheng and A. Sangiovanni-Vincentelli
Department of Electrical Engineering and Computer Sciences
211-202 Cory Hall #1772
University of California, Berkeley
Berkeley, CA 94720-1772


Among the Grand Challenges for high performance computing, semiconductor device simulation is of particular interest for its role in developing a key industrial technology. Advances in semiconductor process technology have allowed the continual reduction of minimum feature sizes consistent with Moore's Law, which asserts that device sizes are reduced exponentially with time. The Semiconductor Industry Association has projected this trend to continue for at least the next 15 years, aggressively pushing the bit count of dynamic random access memory (DRAM) by a factor of four every three years. This continual downscaling of device sizes has placed tremendous demands on predicting the behavior of designs. CAD tools for device simulation can considerably reduce the development cost and turnaround time for new devices. However, aggressive scaling of semiconductor technology is pushing the capabilities of today's simulation tools.

The Monte Carlo method for device simulation, which is based on a microscopic treatment of electron behavior in semiconductors, offers a solution that is becoming increasingly important as process technology now focuses on the deep-submicron ULSI (Ultra Large Scale Integration) regime, where minimum feature sizes are less than 0.25 microns. The large computational requirements of Monte Carlo, which may be on the order of hours or days of CPU time even for two-dimensional treatments on high performance architectures, prohibit its direct use in practical device engineering. Applications of Monte Carlo have therefore remained either for research or as a method of parameter extraction for higher-level models. In our previous work, this problem was addressed by developing algorithms for SIMD architectures.

In this paper, we present a scalable three-dimensional Monte Carlo semiconductor device simulation algorithm for stationary solutions using PVM on a heterogeneous network of workstations. The workstations include MIPS, Intel486, SUN, ALPHA, and ALPHAMP-based architectures. The core software engine for this simulator includes a particle manager, which maintains a centralized event queue for dispatching simulations of electrons, and a single simulation engine on each physical processor in the network. Each simulation engine calculates and tracks carrier trajectories for a single electron. The local statistics which are gathered during the simulation are combined at its conclusion. The algorithms scale well with the number of host processors. Hence, the distributed approach not only offers faster simulation speeds, but also provides the ability to simulate much larger structures than is possible with current parallel architectures because of the increased amount of available memory.