Test plan for DM and CM circuits =================================== Part 1. Test objects ==================== 1. PCC interface to DM and CM - configuration registers. - other registers: constant, error counters. 2. Memory - Head, Tail, and Link memories of CLM. - ALID, Credit, and Cell meories of COMBO. - Head, Tail, and Link memories of ALM. - Bmem, Smem, and Tmem memories of CM. - Head, Tail, and Link memories of CALM. 3. CLM - Input FIFOs for W_IVC and W_CADR. - Parity checking circuit. - Ownership checking circuit. - Enqueue operation. - Dequeue operation. - Alignment of W_IVC, W_CADR, W_NULL, W_LOG, and W_ID. - Bit 13 of W_IVC. - Parity error counting. - CLM dequeue error detect. - CLM input FIFO full error counting. - VAR FIFO full error counting. - Interrupt masking and generating. - Null insertion to the VAR FIFO. - hadr_r match with hadr_l 4. COMBO - Cell counting. - Credit counting. - Credit setting. - Credit express bit functioning. - ALID null bit disabling. - ALID table unchanged after long operation. - Credit enqueue due to incoming credit cell. - Credit enqueue due to FCV_IVC. - Data enqueue operation, a sequence of more than 16 IVCs. - Null insertion of Credit enqueue. - Data enqueues with identical ALIDs in adjacent IVCs, or in IVCs separated by a third IVC. - Dequeue and re-enqueue operations. Updates of the cell count and credit count. - Values of W_LOG and W_ID in different situations. - ALM dequeue error. - Interrupt enabling and generating. (ALM error and VAR FIFO full) 5. Stauts handler - Acceptance of the SCH instruction. - GGcnt and BGcnt reading. - Status bits reading from Scheduller. - Burst mode. - 8 mode and 4 mode. - Pending instruction. - Credit dequeue instruction. - Disable the status bits by TX_FF, LF_CNTR, or sta_dis from PCC. 6. CM - R_IVC FIFO functioning. - FCT_IVC insertion to the R_IVC FIFO. - R_IVC parity checking. Error counting. - R_IVC ownership checking. External or internal. - _FC disabling R_IVC. - Dropping cells on a) null in; b) cr_cell; c) buf_sta==3; d) clp & bufsta>0; e) exceed; f) fuse; - Alignment of W_NULL, W_IVC, W_LOG, and W_ID. - "drop" signal to IPATH. - The arrive() operation. Bcnt increment and Ccnt increment. - The enqueue() operation. Bcnt decrement and Scnt increment. - The dequeue() operation. Scnt resetting. - The delayline() operation. Ccnt increment and Tcnt counting. - Check Ccnt counting and resetting. - Delay line pointer advancing. - C_IVC and C_CR value. - CCR_DIS disabling. - CALM dequeue error. - E_IVC, E_NULL, and E_CR values and alignment. - CALM dequeue and status change. - CM interrupt enabling and generating. Part 2. Test methold ==================== Note: The following test procedure should be executed in the sequence as listed. A test is executed only if the tests previous to it had successful result. Earlier tests provide data for the later tests. Therefore a later test depends on the success of the early tests. 1. Initialization (1) Run software to set up connections toward the PCC on the portcard. It includes to set up links between the GPU and the PCC, etc. (2) Configure the FLEXes on the portcard, including at least the following chips: CLM, DMI, DMS, CMC, CMI, and all FLEXes in the PCC (3) Download the scheduller software for test purposes. (4) Run available verification and memory test software. 2. PCC interface to DM and CM (1) Write FE to the CLM configuration register. Read value should be FE. FE is the value that every bit except the reset bit being 1. (2) Write 02 to the COMBO configuration register. Read value should be 02. (3) Write 7E to the CM configuration register. Read value should be 7E. 7E is the value that every bit except the reset bit being 1. (4) Write 01 in the CLM configuration register. Read value should be 00. 01 is the value that only the reset bit being 1. This reset will reset the configuration register itself, therefore reading 00. (5) Write 01 to the COMBO configuration register. Read value should be 00. 01 is the value that only the reset bit being 1. This reset will reset the configuration register itself, therefore reading 00. The high bits (error flags) may be different. (6) Write 01 to the CM configuration register. Read value should be 00. 01 is the value that only the reset bit being 1. This reset will reset the configuration register itself, therefore reading 00. The high bits (error flags) may be different. (7) Read from CLM error registers. They should be zero (after reset). (8) Read from CM configuration register again. The high bits should be zero (after reset). (9) Write a value into FCT_IVC register. Read value should match. Read from the FCT flag. It should be 1. (10) Write a value into OWN_ID register. Read value should match. (11) Read twice from WP counter. The second read should be 0 since the first read clears the counter. (12) Write an initial value into N2 register. (13) Write an initial value into R register. 3. Memory tests Note: The software may already provided memory tests in 1. If that is the case the following tests would not be necessary. (1) Write values in the CLM Head memory. Read values and compare. (2) Write values in the CLM Tail memory. Read values and compare. (3) Write values in the CLM Link memory. Read values and compare. (4) Write values in the ALID memory. Read values and compare. (5) Write values in the Credit memory. Read values and compare. (6) Write values in the Cell memory. Read values and compare. (7) Write values in the ALM Head memory. Read values and compare. (8) Write values in the ALM Tail memory. Read values and compare. (9) Write values in the ALM Link memory. Read values and compare. (10) Write values in the Bmem memory of the CM. Read values and compare. (11) Write values in the Smem memory of the CM. Read values and compare. (12) Write values in the Tmem memory of the CM. Read values and compare. (13) Write values in the CALM Head memory. Read values and compare. (14) Write values in the CALM Tail memory. Read values and compare. (15) Write values in the CALM Link memory. Read values and compare. 4. CLM Enqueue (1) Write memories with the following initialization values. Initialize the ownership bit in the Head memory being "0" for addresses XXX1 and XXX9, "1" for others. Initialize the head memory and tail memory with "1FFFF" at any address. Initialize the link memory with "1FFFF" for all addresses. (2) Generate a sequence of W_IVC, W_NULL, and W_CADR, as shown as follows: ============================================================= W_IVC W_IVC_P W_NULL W_CADR W_CADR_P purpose ------------------------------------------------------------- 0100 ? 0 ???? ? TLG inserted, not controllable 1000 0 0 6000 1 1001 1 0 6010 0 1002 1 0 6020 0 1003 0 1 6030 1 Null 1004 1 0 6040 0 1005 1 0 6050 1 IVC parity error 1006 0 0 6060 1 1007 1 0 6070 1 CADR parity error 1008 0 0 6080 1 Both parity error 1009 0 0 6090 1 100A 0 0 60A0 1 100B 0 0 60B0 0 IVC p.e. 100C 1 0 60C0 0 Both p.e. 100D 0 0 60D0 0 IVC p.e. 100E 1 0 60E0 1 CADR p.e. 100F 0 0 60F0 0 CADR p.e. 0F0F 1 0 1F00 0 0F1F 0 1 1F01 1 Null 0F2F 1 0 1F02 1 IVC p.e. 0F3F 1 0 1F03 0 0F4F 0 1 1F04 0 Null, CADR p.e. 0F5F 0 1 1F05 0 Null, IVC p.e. 0F6F 1 0 1F06 0 0F7F 0 0 1F07 1 0F8F 0 0 1F08 1 1000 0 0 6A00 1 Second on the queue 1001 1 0 6A10 0 1002 1 0 6A20 0 1003 0 0 6A30 1 1004 1 0 6A40 0 1005 0 0 6A50 1 1006 0 0 6A60 1 1007 1 0 6A70 0 1008 1 0 6A80 0 1009 0 0 6A90 1 1000 0 0 6C00 1 Third on the queue 1001 1 0 6C10 0 1002 1 0 6C20 0 1003 0 0 6C30 1 1004 1 0 6C40 0 1005 0 0 6C50 1 ============================================================= (3) Continue generating W_IVC and W_CADR for 600 more values without having the same IVC values and CADR values in the above table. Parity of the generated signals should be correct. (4) Check empty flags and full flags of the CLM input FIFOs. The empty flags should be false. The full flags should be true. (5) Write 4E into CLM configuration register to set CLM active. Wait for 3 cell cycles or longer. (6) Write 0 into CLM configuration register to set the CLM idle. (7) Read from the Head, Tail, and Link memories of the CLM to check the correctness of the enqueue operations. Head and Tail memory content: ========================================= Address Head Data Tail Data ----------------------------------------- 0100 XXXXX XXXXX CADR: some value 0F0F 21F00 21F00 0F1F 3FFFF 3FFFF 0F2F 3FFFF 3FFFF 0F3F 21F03 21F03 0F4F 3FFFF 3FFFF 0F5F 3FFFF 3FFFF 0F6F 21F06 21F06 0F7F 21F07 21F07 0F8F 21F08 21F08 1000 26000 06C00 1001 1FFFF 1FFFF 1002 26020 06C20 1003 26A30 06C30 1004 26040 06C40 1005 26A50 06C50 1006 26060 06A60 1007 26A70 06A70 1008 26A80 06A80 1009 1FFFF 1FFFF 100A 260A0 060A0 100B 3FFFF 1FFFF 100C 3FFFF 1FFFF 100D 3FFFF 1FFFF 100E 3FFFF 1FFFF 100F 3FFFF 1FFFF all others XFFFF 1FFFF ========================================= Link memory content: =========================== Address Data --------------------------- 6000 06A00 6010 1FFFF 6020 06A20 6030 1FFFF 6040 06A40 6050 1FFFF 6060 06A60 6070 1FFFF 6080 1FFFF 6090 1FFFF 60A0 1FFFF 60B0 1FFFF 60C0 1FFFF 60D0 1FFFF 60E0 1FFFF 60F0 1FFFF 6A00 06C00 6A10 1FFFF 6A20 06C20 6A30 06C30 6A40 06C40 6A50 06C50 6A60 1FFFF 6A70 1FFFF 6A80 1FFFF 6A90 1FFFF 6C10 1FFFF 6C20 1FFFF 6C30 1FFFF 6C40 1FFFF 6C50 1FFFF all others 1FFFF =========================== (8) Read from the parity error counters to check if the parity errors were detected by the circuit. The expected values are: IVC parity errors: 6 CADR parity errors: 5 It is also accepted to have the following values since the first CADR value is unknown. IVC parity errors: 7 CADR parity errors: 5 Refer to (2) for original data that caused the parity erorrs. (9) Monitor hadr_l and hadr_r using a logic analyzer to ensure their relationship being correct. hadr_r should be two clock cycles delayed from hadr_l. 5. COMBO Enqueue Note: Tests in this part rely on correct execution of the previouse part. (1) Check the empty flag and full flag of the VAR FIFO. They should be non-empty and non-full, respectively. (2) Write a "1" in the PCC configuration register at the "sch_dis" bit to disable the scheduller. (3) Initialize the Credit memory with 08s and the Cell memory with 0s, Head, Tail and Link memories with 7FFFs. Initializa ALID with the following values: ===================== address data --------------------- 0000-01FF 03 0F00-0FFF 25 1000-1003 00 1004-1005 1D 1006-100F 01 others 02 ===================== (4) Write 02 to the COMBO configuration register to set the COMBO active. Wait for 5 cell cycles or longer. (5) Use logic analyzer to monitor the output of the VAR FIFO to check if the NULL insertion are correct. (6) Write 00 to the COMBO configuration register to set COMBO to idle. (7) Read from the Credit and Cell memories for the following expected values. Credit: Cell: ====================== ===================== address data address data ---------------------- --------------------- 0100 107 0100 00 1000 107 1000 02 1001 008 1001 00 1002 107 1002 02 1003 107 1003 01 1004 107 1004 02 1005 107 1005 01 1006 107 1006 01 1007 107 1007 00 1008 107 1008 00 1009 008 1009 00 100A 107 100A 00 others 008 others 00 ====================== ===================== (8) Read from the ALID memory. The content should not be different as initialized. (9) Read from the Head, Tail, and Link memories for the following expected values. =============================== address Head Tail ------------------------------- 00 1000 1003 01 1006 1008 02 1FFF 1FFF 03 0100 0100 1D 1004 1005 others 7FFF 7FFF =============================== Link: ======================== address data ------------------------ 1000 1002 1001 7FFF 1002 1003 1003 7FFF 1004 1005 1005 7FFF 1006 100A 1007 1008 1008 7FFF 1009 7FFF 100A 1007 others 7FFF ======================== (10) From the Scheduller, read the status register. The expected value is 2000000BH. 6. COMBO and CLM Dequeue Note: Tests in this part rely on correct execution of the previouse part. (1) Test the algorithm (program) downloaded in the scheduller. The methold depends on the algorithm. Verify that the scheduller does the correct responds. (2) Write a "0" in the PCC status disable register bit. (3) Write 4E into CLM configuration register while keep W_NULL being "1". This sets the CLM active. (4) Write 02 into the COMBO configuration register to set the COMBO active. Wait for 5 cell cycles or longer. (5) Depending on the program downloaded, the Scheduller should start sending dequeue instruction to the status handler. For example, the instruction can be 0400. Monitor this value using a logic analyzer. (6) Monitor on R_IVC, R_NULL, R_CADR, R_LOG, and R_ID. Their values in first 19 cell cycles after active should be as follows. ===================================== R_IVC R_NULL R_CADR R_LOG R_ID ------------------------------------- 3FFF 1 1FFFF XX 0 1000 0 0A000 02 0 1002 0 0A020 02 0 1003 0 0AA30 01 0 1000 0 0AA00 01 0 1002 0 0AA20 01 0 1003 0 0AC30 00 0 1000 0 0AC00 00 0 1002 0 0AC20 00 0 1006 0 0A060 01 0 1007 0 0AA70 00 0 1008 0 0AA80 00 0 100A 0 0A0A0 00 0 1004 0 0A040 02 0 1005 0 0AA50 01 0 1004 0 0AA40 01 0 1005 0 0AC50 00 0 1004 0 0AC50 00 0 3FFF 1 1FFFF XX 0 ===================================== (7) Read the status bits from the Scheduller. It should be all 0s after the previous reading of R_IVC, R_NULL, and R_LOG. (8) Read the dequeue counters (ggcnt and bgcnt) from the Scheduller. The expected values are: ggcnt= bgcnt= (real values depends on Scheduller algorithm) 7. CM Arrive (1) Configue the portcard for loopback from EPATH to IPATH. Send signals from the Test Module such that the required signals in (4) will be available. (2) Initialize the Bmem, Smem and Tmem with the following values. Bmem and Smem: ========================================== Address Bmem data Smem data ------------------------------------------ 1000 40 00 1001 40 00 1002 40 00 1003 40 00 1004 40 00 1005 40 40 1006 40 40 1007 40 40 1008 40 40 1009 40 40 1500 40 00 1501 40 00 1502 40 00 1503 40 00 1504 40 00 1505 40 00 1506 40 00 1507 40 00 1508 40 00 1509 40 40 150A 40 40 150B 40 40 150C 40 40 150D 40 40 150E 40 40 150F 40 40 others 40 00 ========================================== Tmem: ===================== Address Data --------------------- 01000-01006 0560 01007 2030 01008 0560 01500 10C0 01501 10C1 01502 10C2 01503 10C3 01504 10C4 01505 10C5 01506 10C6 01507 10C7 01508 10C8 01509 10C9 0150A 10CA 0150B 10CB 0150C 10CC 0150D 10CD 0150E 10CE 0150F 10CF 1XXXX 0000 2XXXX 7FFF 31000 0005 31001 0005 31002 0005 31003 0004 31004 0005 31005 0005 31006 0005 31007 0001 31008 0005 31500-3150F 0001 others 0000 ===================== (3) Write 3A to the CM configuration register to set the CM active and to enable the interrupts. (4) Generate data from the Test Module such that the following pattern of signals appears at the interface between the CM and IPATH. ================================================================== W_IVC cr_cell in_cr ni eop clp buf_sta purpose ------------------------------------------------------------------ 1000 0 XX 0 0 0 0 1001 0 XX 1 0 0 0 Null 1002 0 XX 0 0 1 0 clp 1003 0 XX 0 0 1 1 clp 1004 0 XX 0 0 0 2 1005 0 XX 0 0 0 3 1003 0 XX 0 1 0 0 eop 1006 1 D6 0 0 0 0 Credit cell 1007 0 XX 0 1 0 0 Exceed 1008 0 XX 1 0 0 0 Null =================================================================== (5) Monitor the signal "drop" by a logic analyzer. The expected pattern is shown as follows. ======================= W_IVC drop W_NULL ----------------------- 1000 0 0 1001 0 1 1002 0 0 1003 1 1 1004 0 0 1005 1 1 1003 1 1 1006 0 1 1007 1 1 1008 0 1 ======================= Note that the signals drop and W_NULL are delayed from the cell cycle that the corresponding W_IVC is provided. 7A. CM Arrive (with unchangeable signal Buf_sta) (1) Configue the portcard for loopback from EPATH to IPATH. Send signals from the Test Module such that the required signals in (4) will be available. (2) Initialize the Bmem, Smem and Tmem with the following values. Bmem and Smem: ========================================== Address Bmem data Smem data ------------------------------------------ 1000 40 00 1001 40 00 1002 40 00 1003 40 00 1004 40 00 1005 40 40 1006 40 40 1007 40 40 1008 40 40 1009 40 40 1500 40 00 1501 40 00 1502 40 00 1503 40 00 1504 40 00 1505 40 00 1506 40 00 1507 40 00 1508 40 00 1509 40 40 150A 40 40 150B 40 40 150C 40 40 150D 40 40 150E 40 40 150F 40 40 others 40 00 ========================================== Tmem: ===================== Address Data --------------------- 01000-01006 0560 01007 2030 01008 0560 01500 10C0 01501 10C1 01502 10C2 01503 10C3 01504 10C4 01505 10C5 01506 10C6 01507 10C7 01508 10C8 01509 10C9 0150A 10CA 0150B 10CB 0150C 10CC 0150D 10CD 0150E 10CE 0150F 10CF 1XXXX 0000 2XXXX 7FFF 31000 0005 31001 0005 31002 0005 31003 0004 31004 0005 31005 0005 31006 0005 31007 0001 31008 0005 31500-3150F 0001 others 0000 ===================== (3) Write 3A to the CM configuration register to set the CM active and to enable the interrupts. (4) Hard wire the backplane signal BUF_STA to be "00". Generate data from the Test Module such that the following pattern of signals appears at the interface between the CM and IPATH. ================================================================== W_IVC cr_cell in_cr ni eop clp purpose ------------------------------------------------------------------ 1000 0 XX 0 0 0 1001 0 XX 1 0 0 Null 1002 0 XX 0 0 1 clp 1003 0 XX 0 0 1 clp 1004 0 XX 0 0 0 1005 0 XX 0 0 0 1003 0 XX 0 1 0 eop 1006 1 D6 0 0 0 Credit cell 1007 0 XX 0 1 0 Exceed 1008 0 XX 1 0 0 Null =================================================================== (5) Repeat (4) with different hard-wired values of BUF_STA=1, 2, and 3. (6) Monitor the signal "drop" by a logic analyzer. The expected pattern is shown as follows. ==================================================================== BUF_STA= 0 1 2 3 -------------------------------------------------------------------- W_IVC drop W_NULL drop W_NULL drop W_NULL drop W_NULL -------------------------------------------------------------------- 1000 0 0 0 0 0 0 1 1 1001 0 1 0 1 0 1 0 1 1002 0 0 0 0 0 0 1 1 1003 0 0 1 1 1 1 1 1 1004 0 0 0 0 0 0 1 1 1005 0 0 0 0 0 0 1 1 1003 1 1 1 1 1 1 1 1 1006 0 1 0 1 0 1 1 1 1007 1 1 1 1 1 1 1 1 1008 0 1 0 1 0 1 0 1 ==================================================================== Note that the signals drop and W_NULL are delayed from the cell cycle that the corresponding W_IVC is provided. 8. CM Enqueue Note: Tests in this part rely on correct execution of the previouse part. (1) Write into the ownid register with the value 14. Write into the N2 register with the value 01. (2) Generate a sequence of R_IVC at the back plane by the Test Module, with the following values: ========================================================== R_IVC R_NULL _FC _CSID purpose ---------------------------------------------------------- 1500 0 0 14 1501 0 0 14 1502 1 0 14 Null 1503 0 1 14 FC 1504 0 0 34 not owned 1505 0 0 16 not owned 1506 0 0 14 1507 1 0 14 Null 1508 0 0 14 1509 0 1 14 FC 150A 0 1 14 FC 150B 0 0 14 150C 0 0 15 not owned 150D 0 0 14 150E 0 0 14 150F 0 0 14 1500 0 0 14 Second set 1501 0 0 14 1502-1506 0 0 14 7FFF 1 1 FF 10 idles 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 1507-150F 0 0 14 7FFF 1 1 FF 22 idles 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF 7FFF 1 1 FF ======================================================= (3) Use a logic analyzer to monitor the output signals of the R_IVC FIFO. The following sequence should be found. ================ R_IVC R_NULL ---------------- 1500 0 1501 0 1506 0 1508 0 150B 0 150D 0 150E 0 150F 0 1500 0 1501 0 1502 0 1503 0 1504 0 1505 0 1506 0 3FFF 1 3FFF 1 3FFF 1 1507 0 1508 0 1509 0 150A 0 150B 0 150C 0 150D 0 150E 0 150F 0 3FFF 1 3FFF 1 3FFF 1 .... .... More idle cells after ================ (4) Read from the Bmem and Smem to check the following expected values. ========================================== Address Bmem data Smem data ------------------------------------------ 1500 3E 22 1501 3E 22 1502 3F 01 1503 3F 01 1504 3F 01 1505 3F 01 1506 3E 22 1507 3F 01 1508 3E 21 1509 3F 41 150A 3F 41 150B 3E 62 150C 3F 41 150D 3E 62 150E 3E 62 150F 3E 62 ========================================== (5) Read from the Head, Tail, and Link memories of the CM to check the following expected values. Head and Tail: ===================================== Address Head Tail ------------------------------------- 0 1500 1508 1 150B 150F ===================================== Link: =================== Address Data ------------------- 1500 1501 1501 1506 1502 7FFF 1503 7FFF 1504 7FFF 1505 7FFF 1506 1508 1507 7FFF 1508 7FFF 1509 7FFF 150A 7FFF 150B 150D 150C 7FFF 150D 150E 150E 150F 150F 7FFF =================== 8A. CM Enqueue (with unchangeable signals _FC and CS_ID) Note: Tests in this part rely on correct execution of the previouse part. (1) Write into the ownid register with the value 14. Write into the N2 register with the value 01. (2) Hard wire the backplane signal _FC to 0, and the signal CS_ID to 14 Generate a sequence of R_IVC at the back plane by the Test Module, with the following values: ========================================================== R_IVC R_NULL purpose ---------------------------------------------------------- 1500 0 1501 0 1502 1 Null 1503 0 FC 1504 0 not owned 1505 0 not owned 1506 0 1507 1 Null 1508 0 1509 0 FC 150A 0 FC 150B 0 150C 0 not owned 150D 0 150E 0 150F 0 1500 0 Second set 1501 0 1502-1506 0 7FFF 1 10 idles 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 1507-150F 0 7FFF 1 22 idles 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 7FFF 1 ======================================================= (3) Repeat (2) with different hard-wired values of _FC and CS_ID, as shown as follows ============================= _FC CS_ID ----------------------------- 1 14 0 16 0 34 0 15 1 00 ============================= (4) Use a logic analyzer to monitor the output signals of the R_IVC FIFO. The following sequence should be found with backplane signal values in (2). All nulls should be found for other values listed in (3). ================ R_IVC R_NULL ---------------- 1500 0 1501 0 1506 0 1508 0 150B 0 150D 0 150E 0 150F 0 1500 0 1501 0 1502 0 1503 0 1504 0 1505 0 1506 0 3FFF 1 3FFF 1 3FFF 1 1507 0 1508 0 1509 0 150A 0 150B 0 150C 0 150D 0 150E 0 150F 0 3FFF 1 3FFF 1 3FFF 1 .... .... More idle cells after ================ (5) Read from the Bmem and Smem to check the following expected values. (for backplane signals given in 2 only) ========================================== Address Bmem data Smem data ------------------------------------------ 1500 3E 22 1501 3E 22 1502 3F 01 1503 3F 01 1504 3F 01 1505 3F 01 1506 3E 22 1507 3F 01 1508 3E 21 1509 3F 41 150A 3F 41 150B 3E 62 150C 3F 41 150D 3E 62 150E 3E 62 150F 3E 62 ========================================== (6) Read from the Head, Tail, and Link memories of the CM to check the following expected values. (for backplane signal values given in 2) Head and Tail: ===================================== Address Head Tail ------------------------------------- 0 1500 1508 1 150B 150F ===================================== Link: =================== Address Data ------------------- 1500 1501 1501 1506 1502 7FFF 1503 7FFF 1504 7FFF 1505 7FFF 1506 1508 1507 7FFF 1508 7FFF 1509 7FFF 150A 7FFF 150B 150D 150C 7FFF 150D 150E 150E 150F 150F 7FFF =================== 9. CM Dequeue Note: Tests in this part rely on correct execution of the previouse part. (1) Through the Scheduller, send instructions to the DM to dequeue from the glass 30 and 31. (Depending on the code loaded in the Scheduller, the dequeue parttern in the following test may be different.) (2) Monitor the signals R_IVC, R_LOG, R_ID, e_ivc, e_cr, and e_null. The expected values are as follows. Note that the signals R_NULL, R_IVC, R_LOG, and R_ID are one cell cycle later than the signals e_ivc, e_null, and e_cr. And e_ivc is one cell cycle later than cd_alid. ============================================================== cd_alid e_null e_ivc e_cr R_IVC R_NULL R_LOG R_ID -------------------------------------------------------------- 0 0 1500 82 1500 1 82 1 0 0 1501 83 1501 1 83 1 0 0 1506 88 1506 1 88 1 0 0 1508 8A 1508 1 8A 1 1 0 150B 8D 150B 1 8D 1 1 0 150D 8F 150D 1 8F 1 1 0 150E 90 150E 1 90 1 1 0 150F 91 150F 1 91 1 - 1 XXXX XX XXXX 1 XX 0 ============================================================== (3) Read from the Bmem and Smem memories. The expected values are as follows. ========================================= Address Bmem Data Smem Data ----------------------------------------- 1500 3E 00 1501 3E 00 1502 3F 01 1503 3F 01 1504 3F 01 1505 3F 01 1506 3E 00 1507 3F 01 1508 3E 00 1509 3F 41 150A 3F 41 150B 3E 40 150C 3F 41 150D 3E 40 150E 3E 40 150F 3E 40 ========================================= (4) Read from the Head, Tail, and Link memories. They should have all nulls as content. (5) Write 01 to the CM configuration register to reset the CM. 10. Integrated Test (Detailed data patterns will be developed in Lab) (1) Write 01 to the CLM configuration register to reset the CLM. Write 01 to the COMBO configuration register to reset the COMBO. (2) Following the initialization procedure for the DM and CM to initialize the circuits and set the active mode of the circuits in the correct sequence. (3) Generate more than 32K continuous W_IVC and W_CADR values on the backplane. In the mean time generate more than 32K continuous R_IVC values on the backplane. The following signals are also generated in a pattern for testing: BUF_STA, _FC, CS_ID (4) Monitor the following signals in the time slot for the local portcard for correctness of data flow: R_IVC, R_CADR, R_LOG, R_ID, R_NULL, W_NULL, W_LOG, W_ID, LASTCELL, e_null, e_ivc, e_cr (5) Monitor the following signals: cff1_err, cff2_err, vff_err, kff_err The signals cff1_err and cff2_err should be always "1". The signals vff_err and kff_err should be "1" first and become "0" after about 32K continuous data has been processed. (6) Monitor the interrupt signals dm_int and cm_int. They should be low when the FIFO full error signals are active. (7) Check other error counters for correct counting of inserted parity errors, and for any dequeue errors. (8) Monitor on the signals civcbit and ccrbit to detect credit enqueue operations in the COMBO. Then monitor the signal ivcren in the COMBO to check its correctness. Verify that nulls are inserted. Read from the credit memory to verify that the new credit value is correct. (9) Write FCV_IVC and FCV_CR from the PCC to the COMBO. Monitor the operation of the forced credit enqueue in the COMBO. (10) Write FCT_IVC to the register. Monitor that this IVC is pushed into the R_IVC FIFO in the CM and get into the CM circuit.