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From: monty@watson.open.ac.uk (Tony Hirst)
Subject: Evolutionary Electronics W/s Papers
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Message-ID: <monty-120896103307@uu-igor-mac.open.ac.uk>
Date: Mon, 12 Aug 1996 10:33:07 GMT
Organization: HCRL, The Open University, UK
Followup-To: comp.ai
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The 1st On-line Workshop for Soft Computation is now open for business....

******************************************************
      CALL FOR PARTICIPATION & DISCUSSION

                  Special Session
               Evolutionary Electronics
-------------------------------------------------------------
http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/papers/Evol_Elec.html
******************************************************
DISCUSSION PROCEDURE:

1. Read the abstracts.
2. Copy the main texts ( ps files ) of interested papers.
3. Send questions and comments to
     wsc@bioele.nuee.nagoya-u.ac.jp
     (The steering committee will send the questions to the authors
      and receive answers from the authors, and make the Q&A visible
      on the Internet.) 
4. Read the answers from the authors on 
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/
5. Repeat the above steps 3 and 4 until you are satisfied.
******************************************************
Analogue Circuits:

       COMPONENT VALUE SELECTION FOR ACTIVE FILTERS USING
         GENETIC ALGORITHMS
       D.H. Horrocks, M.C. Spittle
       University Of Wales, Cardiff. School Of Engineering,

       Genetically Derived Filter Circuits Using Preferred Value
           Components
       David H. Horrocks, Yaser M.A. Khalifa
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.

       Genetically Evolved FDNR and Leap-Frog Active Filters Using
          Preferred Component Values
       David H. Horrocks, Yaser M.A. Khalifa
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.

       Genetic Algorithms Design of Electronic Analogue circuits 
          Including Parasitic Effects
       David H. Horrocks, Yaser M.A. Khalifa
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.


Co-Design:

       An Evolutionary Approach to System-Level Synthesis
       Juergen Teich, Tobias Blickle, Lothar Thiele
       Institute TIK

       Evolving Adaptive Computer Systems
       Tony Hirst
       HCRL, Gardiner Bldg, Walton Hall, Open University


Digital Logic Synthesis:

       Experiences of using Evolutionary Techniques in Logic Minimisation
       Julian F. Miller, Peter V. G. Bradbeer, Peter Thomson
       Dept. of Computer Studies, Napier University

       Genetic Synthesis Techniques for Low-Power Digital Signal 
            Processing Circuits
       T. Arslan, E Ozdemir, M. S. Bright, D.H. Horrocks
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.


Fault Tolerance:

       EVOLUTIONARY TECHNIQUES FOR FAULT TOLERANCE
       Adrian Thompson
       School of Cognitive and Computing Sciences, University of Sussex


Hardware Evolution:

       SILICON EVOLUTION
       Adrian Thompson
       School of Cognitive and Computing Sciences, University of Sussex


Hardware Implementations:

       Implementing a Generic Systolic Array for Genetic Algorithms 
       I. M. Bland, G. M. Megson
       Algorithm Engineering Research Group, Dept. of Computer Science,
       University of Reading

       HGA:A Hardware-Based Genetic Algorithm
       Stephen D. Scott, Ashok Samal, Sharad Seth
       Washington University in St. Louis, University of Nebraska-Lincoln
         and University of Nebraska-Lincoln

       A HARDWARE ARCHITECTURE FOR A PARALLEL GENETIC
       ALGORITHM FOR IMAGE REGISTRATION
       B.C.H. Turton, T. Arslan, D.H. Horrocks
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.

        An Architecture for Enhancing Image Processing via Parallel
          Genetic Algorithms & Data Compression
       B.C.H. Turton, T. Arslan
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.

       A Parallel Genetic VLSI Architecture for Combinatorial Real-Time
         Applications - Disc Scheduling
       B.C.H. Turton, T. Arslan
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.


VLSI Placement:

       A Genetic Framework For The High-Level Optimisation Of Low
         Power VLSI DSP Systems
       M.S. Bright, T. Arslan
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group.

       Structural Cell-based VLSI Circuit Design using a Genetic 
         Algorithm
       T. Arslan, D.H. Horrocks, E. Ozdemir
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.

       STRUCTURAL SYNTHESIS OF CELL-BASED VLSI CIRCUITS USING
          A MULTI-OBJECTIVE GENETIC ALGORITHM
       T. Arslan, D.H. Horrocks, E. Ozdemir
       University Of Wales, Cardiff. School Of Engineering,Circuits and
       Systems Group.


VLSI Test:

       Hierarchical Test Pattern Generation Using A Genetic Algorithm
         With A Dynamic Global Reference Table
       M. J. O'Dare, T. Arslan
       University Of Wales, Cardiff. School Of Engineering,

       GENERATING TEST PATTERNS FOR VLSI CIRCUITS USING A
         GENETIC ALGORITHM
       M. J. O'Dare, T. Arslan
       University Of Wales, Cardiff. School Of Engineering, Circuits and
       Systems Group

