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***  Co-HLEX:Experimental Parallel Hierarchical Recursive Layout System  ***
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1. Overview

 Thank you very match for down-loading Co-HLEX:Experimental Parallel 
Hierarchical Recursive Layout System.
  Co-HLEX generates a layout diagram of a given circuit under a 
prespecified planned chip shape and a set of module proximity conditions. 
Bipolar analog circuit is the current repertoire.
  The motivation of Co-HLEX development includes; the search for a new 
parallel layout algorithm, the representation power proof of KL1, and 
the problem solving power proof of parallel inference machines, Multi-PSI and 
PIM. The original flat circuit net data input is transformed into a 
hierarchical process network named CMPN. Then a hierarchical recursive 
concurrent theorem proving algorithm named HRCTL is applied to CMPN to 
generate a layout under the given planned chip shape. Due to the runtime 
co-operations among CMPN nodes running in parallel, module shape and 
wire abutments could newly be realized.

 
2. Installing the system

 Please refer to the installation file named INSTALL in which you can find a
step-by-step guidance.


3. Running the system

 To run the system, please open either the "shell window" or the "listener 
window" of PIMOS and enter the following goal:

	cd("cohlex").

	problem:go12(cir1,16).

 The argument "16" denotes the default number of available PEs. Please change
this value to meet your environment. The "cir1" denotes the file name 
containing an example bipolar analog circuit net data to be laid out.
 A dialog window will appear three times; two times during the layout 
generation and one time in the end. For each dialog, select one of the 
color_mode (if color="on" or if grey="off") and choose "do_it".


4. List of file names (kanji characters are contained in all the files) 

README		README.j	INSTALL		INSTALL.j	Makefile
Constr.com	Constr.data	Meta.com	Meta.data	Node.com
Node.data	Obj1.com	Obj1.data	Obj2.com	Obj2.data
Obj3.com	Obj3.data	Obj4.com	Obj4.data	layout1.mac
accept_net.kl1	adj_elem.kl1	agg_plines.kl1	agg_routes.kl1	aggr_place.kl1
alien3.kl1	arith_func.kl1	assign_pro.kl1	cho_lframe.kl1	conn_gen.kl1
cr_gp_objs.kl1	create_net.kl1	dat_proc.kl1	des_conn.kl1	disp_blk_m.kl1
disp_blk_s.kl1	disp_tool.kl1	disp_tr_m.kl1	disp_tr_s.kl1	dist_conts.kl1
dp_tool.kl1	eleleaf.kl1	evalute.kl1	expand.kl1	file_devic.kl1
filer.kl1	gen_cont.kl1	gen_goal_v.kl1	gen_mroute.kl1	gen_subpro.kl1
gen_tr_all.kl1	gen_tr_ex.kl1	gen_tree_j.kl1	hand_j.kl1	in_cirtr_j.kl1
init_gwn0.kl1	init_gwn1.kl1	init_gwn2.kl1	init_gwn3.kl1	init_gwn4.kl1
init_gwn5.kl1	init_gwn6.kl1	init_pqt0.kl1	init_pqt1.kl1	init_pqt2.kl1
init_pqt3.kl1	init_pqt4.kl1	init_pqt5.kl1	intool.kl1	investigat.kl1
io_buff.kl1	kmerger.kl1	lay_frame.kl1	lay_frame1.kl1	methdb.kl1
module_pro.kl1	obj_conver.kl1	obstacles.kl1	open_node.kl1	part_block.kl1
part_rule.kl1	path.kl1	pathdb.kl1	permute.kl1	place_sub.kl1
power_line.kl1	pre_dacin.kl1	pre_grn_tr.kl1	pre_part.kl1	pre_plac_j.kl1
pre_place.kl1	pre_route.kl1	problem.kl1	proc_node.kl1	procrule.kl1
pull_in.kl1	resource.kl1	send_data.kl1	set_n_cons.kl1	supvis.kl1
take_layou.kl1	take_route.kl1	to_string.kl1	tool.kl1	tr_branch.kl1
wire_a_net.kl1	disp_shape.esp	draw_shape.esp	gmemory.esp	io_call.esp
kio_data.esp	kio_main.esp	range_sele.esp	rect_draw.esp


5. References

[TR-631] T.Watanabe, et al., Co-operative Hierarchical Layout Problem Solver 
	on Parallel Inference Machine (1991-03) 
[TR-707] T.Watanabe, et al., Co-HLEX:LSI Layout System on Japan's Fifth 
	Generation Parallel Inference Machine (1991-10)
