The Shark Machines

You will be doing your Intro to Computer Systems (ICS) lab assignments on a cluster of rack-mounted Intel Nehalem-based servers called the shark machines. This cluster was donated by the Intel Labs Higher Education group for the ICS course. The original 15-213 cluster machines were known as the fish machines. Our new cluster systems are much bigger and faster, so it seems fitting to call them the shark machines.

Shark machines available to students

There are 10 machines available to students. They run the same RHEL 6.x operating system as the Andrew Linux cluster machines. ICS students and teaching staff can login to them using their Andrew credentials. For example, if your Andrew ID is bovik, then you can login to a random shark machine:

unix> ssh

or a specific machine:

unix> ssh

Frequently Asked Questions

Q: How do I get an account on a shark machine?
A: Accounts will be created for you automatically. If you can't login, please send mail to your instructor.

Help with the CMU computing environment

If you are new to CMU, here are some links to help you get started:

Technical specs

  • Head node (greatwhite)
    • Dell R710 with 2 x Intel E5620 CPUs, 2.67 GHz peak, 32 GB DRAM, 8 Nehalem cores, 8 TB SATA RAID.
    • 64-bit Enterprise Red Hat (Linux kernel 2.6.18)
  • 20 Compute nodes (autograding servers and student machines):
    • Dell R410, 2x Intel E5520 CPUS, 2.67 GHz peak, 24 GB DRAM, 8 Nehalem cores, 160 GB SATA disk
    • Student machines: 64-bit Enterprise Red Hat (Linux kernel 2.6.18)
    • Autograding servers: Ubuntu Linux running Ubuntu virtual machines managed by Tashi
  • Nehalem processor cores:
    • 2-way hyperthreading
    • L1 d-cache: 32 KB, 8-way associative (per core)
    • L1 i-cache: 32 KB, 8-way associative (per core)
    • L2 unified cache: 256 KB, 8-way associative (per core)
    • L3 cache: 8 MB, 16-way associative (shared by all cores)
    • 64-byte block size for L1, L2, and L3
    • L1 d-TLB: 64 entries, 4-way associative (per core)
    • L1 i-TLB: 128 entries, 4-way associative (per core)
    • L2 unified TLB: 512 entries, 4-way associative
    • DDR3 on-chip memory controller