Subash Shankar
Who am I?
I am a postdoctoral fellow at Carnegie Mellon University, working in
the model checking
group (led by Edmund Clarke).
My Research
My professional interests include:
- Formal Methods
- Software Engineering
- Temporal / Modal Logics
- Automated Reasoning / Theorem Proving
- Computer Security
- Parallel Processing
- Computer Architecture
- Education
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My current research involves the use of automated software engineering
techniques for program reduction, thus allowing for more efficient
formal verification. More specifically, I am developing concepts to
apply program slicing to hardware description languages.
Prior to this, I worked on
CV, a model checker for
automatic verification of VHDL designs.
My PhD dissertation (titled "Formal Verification of VHDL Designs Using
Temporal Logics") had two major facets:
- A formal semantics for VHDL in a new type of temporal logic
- Efficient reasoning in propositional temporal logic
Please see my
old home page
for more information about my thesis (and other publications).
Leave me mail! -
sshankar+{at}cs{dot}cmu{dot}edu