The backbone architecture of the system is provided by the iWarp computer, which is an 8x8 two-dimensional torus of processors, each of which is connected to its four neighbors, as shown below.
iWarp has several features that make it suitable for this application:
Exploiting these features, we designed the simple interface shown below. This interface takes the analog output from four sync'ed television-quality cameras, does A/D conversion, and presents the digital value of the result as a 32-bit word in iWarp's memory space. The iWarp processor to which this board is attached reads the word and sends it systolically to the processors with the large memories where the image is stored.
Since the iWarp can do synchronous memory reads at 10 MHz, exactly matching video rate, no buffering or FIFO is necessary on the video interface. As soon as the data is available, iWarp reads it and feeds it to the pathway.
Since iWarp makes it possible to reserve pathway bandwidth, we can guarantee that the video stream will never be interrupted, even momentarily, as it proceeds from the iWarp where the data is digitized to where it is stored. This makes it unnecessary to perform buffering at the digitizing iWarp cell. This is important because doing such buffering would use memory bandwidth, making it impossible for the iWarp to keep up with the video stream.
Our current system uses just one of these video interfaces, but it is readily possible to scale it to use as many as eight, which would support 32 cameras. One architecture for such an expanded system is: