%0 Generic %T TRW Monolithic Video A/D Converter %0 Book %D 1979 %T The 8086 Family User's Manual %0 Book %D 1988 %T Programming Parallel Processors %I Addison-Wesley %0 Book %D 1989 %T American National Standard for Information Systems Programming Language Fortran: S8(X3.9-198x) %0 Report %D 1993 %T Electrotechnical Laboraotory ETL %I Agency of Industrial Science and Technology, Ministry of International Trade and Industry %0 Edited Book %D 1993 %T Applications of Digital Image Processing XVI %B Proceedings of the Spie The International Society for Optical Engineering %V 2028 %P 14-16 %X The following topics were dealt with: image coding and compression; vision and imaging applications; restoration and enhancement; pattern recognition; architectures and simulation. %0 Edited Book %D 1994 %T Proceedings of 26th Southeastern Symposium on System Theory %B Los Alamitos, Ca, Usa: Ieee Comput. Soc. Press %I IEEE %P 5320-5 %X The following topics were dealt with: power systems; signal processing; control theory; algorithms and software; time-varying systems; modelling and simulation; radar systems and target tracking; electromagnetics; fuzzy systems; neural networks; detection and estimation; VLSI; image processing; system theory; communication networks; power distribution; optics; system identification; microprocessors and parallel processing; communications theory; control system applications;. %0 Journal Article %D 1994 %T Second International Meeting on Fully Three-Dimensional Image Reconstruction in Radiology and Nuclear Medicine %J Physics in Medicine and Biology %V 39 %N 3 %P 0031-9155 %K nuclear medicine; reconstruction algorithms comparison; medical diagnostic imaging ; 3D reconstruction algorithms; positron emission tomography; multi-slice rebinning; axial image filtering; human striation imaging ; oversampled filters; rotating positron tomographs; convolution-subtraction scatter correction method; pinhole collimation; cone-beam tomography; 3D compensation methods; SPECT; iterative reconstruction; massively parallel computers ; 3D computerized angiography; figures of merit COMPUTERISED TOMOGRAPHY; IMAGE RECONSTRUCTION; MEDICAL IMAGE PROCESSING ; RADIOISOTOPE SCANNING AND IMAGING %X The following topics were dealt with: 3D reconstruction algorithms for positron emission tomography; multi-slice rebinning and axial image filtering; statistically significant differences between algorithms; human striation imaging ; oversampled filters; rotating positron tomographs; a convolution-subtraction scatter correction method; pinhole collimation; cone-beam tomography; 3D compensation methods for SPECT; iterative reconstruction in SPECT; massively parallel computers for 3D SPECT; 3D computerized angiography; figures of merit for comparing reconstruction algorithms. %0 Edited Book %D 1994 %T IEE Colloquium on ' Parallel Architectures for Image Processing ' (Digest No.1994/135) %I IEE %C London, UK %V 60 %K TMS320C40; parallel architectures ; single chip processor; video signal processing architecture; coding; computer vision ; reconfigurable logic; parallel computing machine ; ASTRA; conceptual hierarchical image processor; optical computing; parallel image processing ; parallel volume rendering ; image data classification; transputers; produce inspection; image processing system DIGITAL SIGNAL PROCESSING CHIPS; ENCODING; IMAGE PROCESSING ; OPTICAL INFORMATION PROCESSING; PARALLEL ARCHITECTURES; TRANSPUTERS %X The following topics were dealt with: single chip video signal processing architecture for image processing ; coding and computer vision ; reconfigurable logic based parallel computing machine; ASTRA; conceptual hierarchical image processor; optical computing for parallel image processing ; parallel volume rendering; image data classification; transputers for produce inspection; and a parallel TMS320C40-based image processing system. %0 Edited Book %D 1994 %T Proceedings of SOUTHEASTCON '94 %I IEEE %C Miami, FL %P 492 %X The following topics were dealt with: bioengineering technology; multidimensional systems and signals; energy systems; optics and lasers; high speed communication networks; power electronics; modelling and simulation; neural networks; electromagnetics; circuits and systems; communications; power systems; reliability; computer networks; education; control systems; parallel and fault-tolerant systems; image processing ; digital systems; signal processing; robotics. %0 Journal Article %A Abelson, H. %A Andreae, P. %D 1980 %T Information Transfer and Area-Time Tradeoffs for VLSI Multiplication %J Communications of the ACM %V 23 %N 1 %P 20-23 %0 Conference Proceedings %A Acierno, A d' %A Stefano, C. de %A Tortorella, F. %A Vendo, M. %D 1994 %T Can a Sequential Thinning Algorithm be Parallelized %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 360-362 %0 Journal Article %A Agrawal, O.P. %A Laws, D.A. %D 1984 %T The Role of Programmable Logic in System Design %J VLSI Design %V V %N 3 %P 44-56 %0 Conference Proceedings %A Agrawal, A. %A Nekludova, L. %A Lim, W. %D 1987 %T A Parallel O(log N) Algorithm for Finding Connected Components in Planar Images %J International Conference on Parallel Processing %0 Journal Article %A Ahmed, N. %A Natarajan, T. %A Rao, K.R. %D 1974 %T Discrete Cosine Transform %J IEEE Trans. on Computers %V C-23 %N 1 %P 90-93 %0 Book %A Aho, A. %A Hopcroft, J.E. %A Ullman, J.D. %D 1975 %T The Design and Analysis of Computer Algorithms %I Addison-Wesley %C Reading, Massachusetts %0 Book %A Aho, A. V. %A Hopcroft, J. E. %A Ullman, J. D. %D 1983 %T Data Structures and Algorithms %I Addison-Wesley %0 Book %A Aho, A. V. %A Sethi, R. %A Ullman, J. D. %D 1986 %T Compilers: Principles, Techniques, and Tools %I Addison-Wesley %0 Conference Proceedings %A Ajiro, M. %A Miyata, H. %A Kan, T. %A Ono, M. %D 1993 %T Satellite image processing using cellular array processor (CAP) %J Igarss '93 %E Fujimura, S. %I IEEE %C Tokyo, Japan %P 1972-4 %X Since its successful launch in February of 1992, the Japan Earth Resources Satellite-1 (JERS-1) has been sending back high resolution images of the Earth for various studies, including the investigation of Earth resources, the preservation of environments and the observation of coastal lines. Currently, received images are processed using the Earth Resources Satellite Data Information System (ERSDIS). The ERSDIS is a high speed image processing system utilizing an extended cellular array processor as its main processing module. The extended cellular array processor (CAP), consisting of 4096 processing elements configured into a two-dimensional array, is designed to have many parallel processing optimizing capabilities targetting large-scale image processing at a high speed. This paper describes the structure of the ERSDIS and the details of the CAP design. %0 Conference Proceedings %A Akeley, K. %D 1993 %T RealityEngine graphics %J Computer Graphics Proceedings %I ACM %C Anaheim, CA %P 109-16 %K RealityEngine graphics system; rendering; texture mapped antialiased polygons; near-massively parallel ; antialiased texture mapped pixels; rendering performance; texture mapped triangles; high-end graphics workstation; real time; image generation; interactive image processing COMPUTER GRAPHIC EQUIPMENT; IMAGE PROCESSING ; PARALLEL PROCESSING; RENDERING (COMPUTER GRAPHICS); SOLID MODELLING; SYSTEMS ANALYSIS %X The RealityEngine graphics system is the first of a new generation of systems designed primarily to render texture mapped, antialiased polygons. This paper describes the architecture of the RealityEngine graphics system, then justifies some of the decisions made during its design. The implementation is near-massively parallel, employing 353 independent processors in its fullest configuration, resulting in a measured fill rate of over 240 million antialiased, texture mapped pixels per second. Rendering performance exceeds 1 million antialiased, texture mapped triangles per second. In addition to supporting the functions required of a general purpose, high-end graphics workstation, the system enables realtime, "out-the-window" image generation and interactive image processing . %0 Book %A Akl, S. G. %D 1985 %T Parallel Sorting Algorithms %I Academic Press %0 Conference Proceedings %A Alander, J. T. %D 1993 %T On robot navigation using a genetic algorithm %J Artificial Neural Nets and Genetic Algorithms. Proceedings of the International Conference %P 471-8 %X We study the possibility of using genetic algorithms in mobile robot navigation. The autonomous robot has a map of the room it moves within and some simulated sensors including range sensors to measure the distance between the robot and the other objects in the room. The location estimation method is based on minimizing the fitness function that depends on the measured data and the environment model by a genetic algorithm. The potential benefits of the genetic algorithms in this application area include robustness, parallel nature, generality, flexibility, incrementality, and simplicity. The obvious drawbacks include slow and stochastic processing. This work is a preliminary one in examining the applicability of genetic algorithms to solve computational problems of industrial and autonomous robots. In general the proposed method of finding the vector that gives the optimal fitting to the model used can be applied in may other calibration type problems as well in robotics as many other fields, too. %0 Conference Proceedings %A Albenesi, M. G. %A Ferretti, M. %A Leoni, S. %D 1994 %T A Hierarchical Compression Engine %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 391-394 %0 Journal Article %A Albert, E. %A Lukas, J. D. %A Steele, Jr., G. L. %D 1991 %T Data Parallel Computers and the FORALL Statement %J Journal of Parallel and Distributed Computing %V 13 %N 2 %P 185-192 %0 Journal Article %A Aleliunas, R. %A Rosenberg, A.L. %D 1982 %T On Embedding Rectangular Grids in Square Grids %J IEEE Transactions on Computers %V C-31 %N 9 %P 907-913 %0 Journal Article %A Ali, Z. %D 1980 %T FFT Algorithms Speed Digital-Signal Processing %J Electronic Design %V %P 111-118 %0 Conference Proceedings %A Ali, A. T. %A Dagless, E. L. %D 1990 %T Vehicle and Pedestrian Detection and Tracking %J IEE Colloquium on 'Image Analysis for Transport Applications' %P 5/1-7 %0 Conference Proceedings %A Allart, E. %A Zavidovique, B. %D 1988 %T Functional Computer for Low Level Image Processing %J 9th International Conference on Pattern Recognition %C Rome, Italy %P 830-2 %0 Conference Proceedings %A Allart, E. %A Zavidovique, B. %D 1989 %T Global Transforms in Real Time with the Functional Low Level Image Processor (FLLIP) %J 5th International Conference on Image Analysis and Processing. Progress in Image Analysis and Processing %C Positano, Italy %P 666-70 %0 Conference Proceedings %A Allen, J. R. %A Kennedy, K. %D 1984 %T Automatic Loop Interchange %J ACM SIGPLAN Symposium on Compiler Construction %C Montreal %P 233-46 %0 Conference Proceedings %A Allen, Robert %A Yasuda, Dean %A Tanimoto, Steven %A Shapiro, Linda %A Cinque, Luigi %D 1993 %T A Parallel Algorithm for Graph Matching and its MasPar Implementation %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 13-18 %0 Generic %A Alliant Computer Systems Corporation %D 1987 %T FX/Series Product Summary %0 Conference Proceedings %A Allinson, N. M. %A Howard, N. J. %A Kolcz, A. R. %A Tyrrell, A. M. %D 1994 %T Image processing applications using a novel parallel computing machine based on reconfigurable logic %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 2/1-7 %K parallel computing machine ; reconfigurable logic; Zelig; fine-grained computer; field-programmable gate arrays; binary morphology; speed-up results IMAGE PROCESSING EQUIPMENT; LOGIC ARRAYS; PARALLEL MACHINES %X Zelig is a 32 physical node fine-grained computer employing field-programmable gate arrays. Its application to the high speed implementation of various image pre-processing operations (in particular binary morphology) is described together with typical speed-up results. %0 Journal Article %A Alnuweiri, H. M. %A Kumar, V. K. P. %D 1991 %T Fast Image Labeling Using Local Operators on Mesh-Connected Computers %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 13 %N 2 %P 202-207 %0 Conference Proceedings %A Alnuweiri, Hussein M. %D 1991 %T Constant Time Image Component Labelling on a Reconfigurable Processor Array %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 565-572 %0 Conference Proceedings %A Alnuweri, H. %A Kumar, V. K. P. %D 1990 %T Optimal Image Algorithms on an Orthogonally-Connected Memory-Based Architecture %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 350-5 %0 Conference Proceedings %A Alverson, R. %A Callahan, D. %A Cummings, D. %A Koblenz, B. %A Porterfield, A. %A Smith, B. %D 1990 %T The Tera Computer System %J International Conference on Supercomputing %I ACM %C Amsterdam, Netherlands %P 1-6 %X The TERA architecture was designed with several major goals in mind. First, it needed to be suitable for very high speed implementations, i.e., admit a short clock period and be scalable to many processors. Second, it was important that the architecture be applicable to a wide spectrum of problems. A third goal was ease of compiler implementation. Although the instruction set does have a few unusual features, these do not seem to pose unduly hard problems for the code generator. The TERA architecture is derived from that of Horizon although they are highly similar multistream MIMD systems, there are many significant differences between the two designs. %0 Conference Proceedings %A Alves de Barros, Marcelo %A Akil, Mohamed %D 1994 %T Low Level Image Processing Operators on FPGA: Implementation Examples and Performance Evaluation %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 262-267 %0 Book Section %A American Microsystems Inc. %D 1980 %T Fast Fourier Transformer %B MOS Products Catalog %I American Microsystems Inc. %P 2.90 - 2.91 %0 Journal Article %A Amin, S. A. %A Evans, D. J. %D 1994 %T Systolic array design for low-level image processing %J Kybernetes %V 23 %N 1 %P 26-38 %K systolic array design; low-level image processing ; parallel algorithms ; low-level digital image processing ; gradient operator; double pipeline; system bus; Prewitt operators; Sobel operators IMAGE PROCESSING EQUIPMENT; PIPELINE PROCESSING; SYSTOLIC ARRAYS; TRANSPUTER SYSTEMS %X Systolic array designs of parallel algorithms for low-level digital image processing , and in particular the gradient operator, are described. Indicates how, to achieve high performance, a new systolic array can be designed in which all the cells in a double pipeline are interconnected to a system bus. The transputer implementation of the design is also considered and comments and conclusions that relate to the use of the systolic array on transputer networks are given. Subsequently it is shown that the systolic array design can be extended to handle the Prewitt and Sobel operators. %0 Edited Book %A Ammar, R. A. %D 1991 %T Proceedings of ISMM Symposium Parallel and Distributed Computing and Systems - II %I Acta Press %C Washington, DC, USA %P 111 %K neural networks; fault tolerance; multiprocessor interconnection; parallel architectures ; parallel algorithms ; image processing FAULT TOLERANT COMPUTING; MULTIPROCESSING SYSTEMS; MULTIPROCESSOR INTERCONNECTION NETWORKS; PARALLEL ALGORITHMS; PARALLEL ARCHITECTURES; PARALLEL PROGRAMMING %X The following topics were dealt with: neural networks, fault tolerance, multiprocessor interconnection; parallel architectures; parallel algorithms; and image processing . %0 Report %A Anderson, A. H. %D 1980 %T Restructurable VLSI Program %0 Conference Proceedings %A Anderson, Jennifer M. %A Lam, Monica S. %D 1993 %T Global Optimizations for Parallelism and Locality on Scalable Parallel Machines %J Programming Languages Design and Implementation %I ACM SIGPLAN %C Albuquerque, NM %P 112-125 %0 Conference Proceedings %A Angeniol, B. %A Treleaven, P. %D 1990 %T The Pygmalion Neural Network Programming Environment %J Advanced Neural Computers %I Air Force Office of Scientific Research %C Amsterdam, Netherlands %P 167-75 %0 Generic %A Annaratone, M. %D 1985 %T Warp Host Software Requirements and Deliverables %C Carnegie Mellon University Department of Computer Science %0 Conference Proceedings %A Annaratone, M. %A Arnould, E. %A Hsiung, P.K. %A Kung, H.T. %D 1985 %T Extending the CMU Warp Machine with a Boundary Processor %J Proceedings of SPIE Symposium, Vol. 564, Real-Time Signal Processing VIII %0 Conference Proceedings %A Annaratone, M. %A Arnould, E. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Menzilcioglu, O. %A Sarocky, K. %A Webb, J.A. %D 1986 %T Warp Architecture and Implementation %J Annual International Symposium on Computer Architecture %P 346-356 %0 Conference Proceedings %A Annaratone, M. %A Arnould, E. %A Kung, H. T. %A Menzilcioglu, O. %D 1986 %T Using Warp as a Supercomputer in Signal Processing %J Proceedings of ICASSP 86 %P 2895-2898 %0 Conference Proceedings %A Annaratone, M. %A Bitz, F. %A Clune, E. %A Kung, H. T. %A Maulik, P. %A Ribas, H. %A Tseng, P. %A Webb, J. %D 1987 %T Applications and Algorithm Partitioning on Warp %J COMPCON Spring '87 %C San Francisco, CA %P 272-275 %0 Conference Proceedings %A Annaratone, M %A Arnould, E. %A Cohn, R. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Menzilcioglu, O. %A Sarocky, K. %A Senko, J. %A Webb, J. %D 1987 %T Architecture of Warp %J COMPCON Spring '87 %C San Francisco, CA %P 264-267 %0 Conference Proceedings %A Annaratone, M. %A Bitz, F. %A Deutch, J. %A Hamey, L. %A Kung, H. T. %A Maulik, P. %A Ribas, H. %A Tseng, P. %A Webb, J. %D 1987 %T Applications Experience on Warp %J Proceedings of the 1987 National Computer Conference %I AFIPS Press %C Chicago, IL %P 149-158 %0 Conference Proceedings %A Annaratone, M %A Arnould, E. %A Cohn, R. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Menzilcioglu, O. %A Sarocky, K. %A Senko, J. %A Webb, J. %D 1987 %T Warp Architecture: From Prototype to Production %J Proceedings of the 1987 National Computer Conference %P 133-140 %0 Journal Article %A Annaratone, M. %A Arnould, E. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Menzilcioglu, O. %A Webb, J. A. %D 1987 %T The Warp Computer: Architecture, Implementation and Performance %J IEEE Transactions on Computers %V C-36 %N 12 %P 1523-1538 %0 Conference Proceedings %A Annaratone, M. %D 1988 %T Singular Value Decomposition on Warp %J SVD and SIGNAL PROCESSING Algrorithm, Applications and Architectures %0 Conference Proceedings %A Anyanwu, C. D. %A Jalowiecki, I. P. %A Krikelis, A. %D 1994 %T Evaluating ASTRA on image processing applications %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 3/1-6 %K associative string processor; image processing applications ; ASP System Testbed for Research and Applications; ASTRA; parallel processing system ; multilayer heterogeneous architecture; extendable linear array; associative processing elements; performance evaluation; vision-related benchmarks IMAGE PROCESSING EQUIPMENT; PARALLEL ARCHITECTURES; PERFORMANCE EVALUATION %X The ASP System Testbed for Research and Applications (ASTRA) is an associative processor-based parallel processing system developed for image processing applications. The machine implements a multilayer heterogeneous architecture with an extendable linear array of simple associative processing elements at its base and more powerful processors at higher levels. A model has been developed to assist in performance evaluation studies of the system on image processing applications with the aid of vision-related benchmarks. The machine and an analysis of some of the results obtained on one such benchmark are discussed in this paper. %0 Book %A Apostol, T. %D 1974 %T Mathematical Analysis %I Addison-Wesley %C Reading, Massachusetts %0 Journal Article %A Archibald, J. %A Baer, J-L. %D 1986 %T Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model %J ACM Transactions on Computer Systems %V 4 %N 4 %P 273-298 %0 Edited Book %A Arnold, D. %A Christie, R. %A Day, J. %A Roe, P. %D 1994 %T Proceedings of the 6th Australian Transputer and Occam User Group Conference. Parallel Computing and Transputers %I Ios Press %C Amsterdam, Netherlands %P 383 %X The following topics were dealt with: concurrent programming; graphics and image processing ; parallel algorithms; parallel applications; robotics and control; and software tools. %0 Conference Proceedings %A Arnould, E. %A Kung, H.T. %A Menzilcioglu, O. %A Sarocky, K. %D 1985 %T A Systolic Array Computer %J Proceedings of 1985 IEEE International Conference on Acoustics, Speech and Signal Processing %P 232-235 %0 Conference Proceedings %A Arnould, E. A. %A Bitz, F. J. %A Cooper, E. C. %A Kung, H. T. %A Sansom, R. %A Steenkiste, P. A. %D 1989 %T The Design of Nectar: A Network Backplane for Heterogeneous Multicomputers %J Proceedings of Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS III) %0 Journal Article %A Athas, W. C. %A Seitz, C. L. %D 1988 %T Multicomputers: Message-Passing Concurrent Computers %J Computer %V 21 %N 8 %P 9-24 %0 Conference Proceedings %A Atkinson, J. %A Hobson, C. A. %A Kshirsagar, S. %A Lilley, F. %A Pearson, J. D. %D 1993 %T Computer vision methods for the three-dimensional measurement of manufactured parts %J Computer Vision for Industry %I SPIE %C Munich, Germany %P 24-25 %K three-dimensional measurement; non-contact system; surface shape measurement; manufactured parts; coherent optical system; parallel processing hardware ; structured lighting; multi-stripe fringe pattern; parallel image processing system ; TMS320C40; MIMD message passing architecture; EISA bus; host interface; data acquisition; reliability; robustness AUTOMATIC OPTICAL INSPECTION; COMPUTER VISION ; PARALLEL ARCHITECTURES; SPATIAL VARIABLES MEASUREMENT %X Describes a non-contact system for surface shape measurement of manufactured parts. The technique consists of a coherent optical system combined with powerful parallel processing hardware, thus allowing rapid inspection rates to be realised. A 'structured lighting system is employed involving the projection of a multi-stripe fringe pattern onto the object surface thus enabling three dimensional data to be obtained. Phase measuring techniques are applied in order to increase accuracy and resolution. A comparison is made between two different phase measuring methodologies. These techniques require computationally intensive algorithms and processing of large amounts of image data. Image processing hardware should be fast enough to achieve results within a reasonable time scale. A parallel image processing system has been designed for such applications based on the Texas Instruments digital signal processor type TMS320C40. The system is based on MIMD message passing architecture and uses an EISA bus for the host interface. The issues of speed of data acquisition and processing, reliability and robustness of the technique and accuracy are discussed. %0 Journal Article %A Aubusson, R. C. %A Catt, I. %D 1978 %T Wafer Scale IntegrationA Fault Tolerant Procedure %J IEEE Journal of Solid-State Circuits %V SC-13 %N 3 %P 339-344 %0 Conference Proceedings %A Avila, J. %A Kuekes, P. %D 1983 %T One-Gigaflop VLSI Systolic Processor %J Proceedings of SPIE Symposium, Vol. 431, Real-Time Signal Processing VI %P 159-165 %0 Conference Proceedings %A Ayache, N. %A Hansen, C. %D 1988 %T Rectification of images for binocular and trinocular stereovision %J Proceedings of the Ninth International Conference on Pattern Recognition %C Rome, Italy %P 11-16 %0 Journal Article %A Azcarraga, A. %A Paugam-Moisy, H. %A Puzenat, D. %D 1994 %T An incremental neural classifier on a MIMD parallel computer %J Ifip Transactions A %V 44 %P 13-22 %X MIMD computers are among the best parallel architectures available. They are easily scalable with numerous processors and have potentially huge computing power. One area of application for such computers is the field of neural networks. The article presents a study, and two parallel implementations, of a specific neural incremental classifier of visual patterns. This neural network is incremental in that network units are created whenever the classifier is not able to recognize correctly a pattern. The dynamic nature of the model renders the parallel algorithms rather complex. %0 Conference Proceedings %A strand, Erik %A strm, Anders %D 1994 %T A Single Chip Multi-Function Sensor System for Wood Inspection %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 300-304 %0 Book %A Baase, S. %D 1988 %T Computer Algorithms: Introduction to Design and Analysis, Second Edition %I Addison-Wesley %0 Book Section %A Baer, J.-L. %D 1980 %T Computer Systems Architecture 7 %I Computer Science Press %S Digital System Design Series %0 Conference Proceedings %A Baig, M. S. %A Alexandridis, N. A. %A El-Ghazawi, T. A. %D 1991 %T A highly reconfigurable multiple SIMD/MIMD architecture %J Proceedings of the Fourth Ismm/iasted International Conference Parallel and Distributed Computing and Systems %E Ammar, R. A. %I Acta Press %C Washington, DC %P 35-6 %K reconfigurable; multiple SIMD/MIMD; MSIMD/MIMD; architecture; partitionable broadcasting interconnection network; high performance; performance/cost MULTIPROCESSOR INTERCONNECTION NETWORKS; PARALLEL ARCHITECTURES; PERFORMANCE EVALUATION %X Many partitionable SIMD/MIMD architectures were introduced in order to provide high performance for engineering and scientific applications, such as image processing . Such systems are referred to as Multiple SIMD/MIMD, MSIMD/MIMD, computers. The authors present a new MSIMD/MIMD architecture and an analytical study comparing it with its existing competitors. The high performance exhibited by this system is attributed to its partitioning flexibility. The system avoids the inherent rigidity in the existing systems through the use of a general purpose computing element and a partitionable broadcasting interconnection network. This network allows dynamic (run time) assignment of the role of processing element or control unit to each of the general purpose computing elements. Analytical models for the proposed system as well as for its comparables are developed. It is shown that the proposed architecture presents a significantly better performance/cost tradeoff when compared with the existing MSIMD/MIMD systems. %0 Journal Article %A Bal, H. E. %A Steiner, J. G. %A Tanenbaum, A. S. %D 1989 %T Programming Languages for Distributed Computing Systems %J Computing Surveys %V 21 %N 3 %P 261-322 %0 Book %A Ballard, D. H. %A Brown, D.M. %D 1982 %T Computer Vision %I Prentice-Hall %0 Journal Article %A Ballard, D. H. %D 1991 %T Animate Vision %J Artificial Intelligence %V 48 %N 1 %P 57-86 %0 Edited Book %A Baozong, Yuan %D 1993 %T Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation %I IEEE %C Beijing, China %V 5 %P 1206 %K advanced processor architecture; multimedia; parallel processing ; distributed systems; multiprocessing systems; object-oriented software; databases; programming languages; computation theory; network design; VLSI design; artificial intelligence; CAD/CAM; neural nets; image processing ; pattern recognition; telecommunication; spread spectrum communication; mobile radio; LAN; B-ISDN; speech coding; image communication; optical communication; DSP; stability analysis; CIM; robotics; optimal control; robust control; fuzzy control; intelligent control; adaptive control; power system control; energy management; power system dynamics; relay protection; voltage control; power system planning; high voltage techniques; motor drives ARTIFICIAL INTELLIGENCE; CIRCUIT CAD; COMPUTER SCIENCE; CONTROL ENGINEERING; POWER SYSTEMS; SIGNAL PROCESSING; TELECOMMUNICATION %X The following topics were dealt with: advanced processor architecture; multimedia and applications; parallel processing; distributed systems; multiprocessing systems; object-oriented software; databases; programming languages; computation theory; network design; VLSI design; artificial intelligence; CAD/CAM; neural nets; image processing ; pattern recognition; telecommunication; spread spectrum communication; mobile radio; LAN; B-ISDN; speech coding; image communication; optical communication; DSP; stability analysis; CIM; robotics; optimal control; robust control; fuzzy control; intelligent control; adaptive control; power system control; energy management; power system dynamics; relay protection; voltage control; power system planning; high voltage techniques; and motor drives. %0 Journal Article %A Barbacci, M.R. %D 1981 %T Instruction Set Processor Specifications (ISPS): The Notation and Its Application %J IEEE Transactions on Computers %V C-30 %N 1 %P 24-40 %0 Journal Article %A Barnard, S. T. %A Fischler, M. A. %D 1982 %T Computational stereo %J Computing Surveys %V 14 %N 4 %P 554-572 %0 Journal Article %A Barnard, E. %D 1988 %T Optimal error diffuction for computer-generated holograms %J Journal of the Optical Society of America (A) %V 5 %N 11 %P 1803-17 %0 Conference Proceedings %A Barnard, S. %D 1990 %T Recent Progress in CYCLOPS: A System for Stereo Cartography %J Image Understanding Workshop %I Defense Advanced Research Projects Agency %C Pittsburgh, PA %P 449-55 %0 Book %A Barnum, A.A. %A Knapp, M.A. (editors) %D 1963 %T Proceedings of the 1962 Workshop on Computer Organization %I Spartan Books, Inc. %0 Conference Proceedings %A Baron, Thierry %A Levine, Martin D. %A Yeshurun, Yehecekel %D 1994 %T Exploring with a Foveated Robot Eye System %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 377-380 %0 Conference Proceedings %A Barton, E. %A Roweth, D. %D 1988 %T The Computing Surface %J International Specialist Seminar on the Design and Application of Parallel Digital Processors %C Lisbon, Portugal %P 139-42 %0 Conference Proceedings %A Basille, J. L. %A Houatra, D. %A Padiou, G. %D 1993 %T A high-level MIMD programming tool for image understanding algorithms %J Proceedings Tencon '93 %E Baozong, Yuan %I IEEE %C Beijing, China %6 5 %P 898-901 %X Image understanding algorithms involve different parallel architectures. Among them, there is MIMD computers for the purpose of executing complex algorithms. Unfortunately, programming such computers is difficult. A high-level MIMD programming tool based on the Linda programming paradigm is presented which can be used to implement parallel image understanding algorithms easily and efficiently. We describe the implementation of this software on a message passing multicomputer. The overhead of the primitives and the experiences with two well known problems are presented for providing an idea of the practicability of the system. %0 Conference Proceedings %A Baskett, F. %D 1981 %T Designing a VLSI Processor - Aids and Architectures %J VLSI Systems and Computations %P 20 %0 Journal Article %A Bastiaens, K. %A Lemahieu, I. %A Desmedt, P. %D 1994 %T On the use of a multi-threaded operating system for an efficient parallel implementation of the ML-EM algorithm for PET image reconstruction %J Ifip Transactions A %V 44 %P 31-9 %X Multi-threaded operating systems were introduced in the quest to reduce the overhead caused by task manipulation and synchronization. An example is the recently introduced Solaris 2.2 multi-threaded operating system. In this paper, a parallel application in the domain of positron emission tomography (PET) image reconstruction is presented, for which a successful use of the multi-threaded approach has led to an implementation, with a nearly linear speedup, of the maximum likelihood expectation maximalization (ML-EM) algorithm. %0 Conference Proceedings %A Bastiaens, K. %A Lemahieu, I. %D 1994 %T A parallel implementation of the ML-EM reconstruction algorithm for PET images in a visual language %J Hybrid Image and Signal Processing IV %I SPIE %C Orlando, FL %P 176-83 %X Due to its iterative nature, the execution of the maximum likelihood expectation maximization (ML-EM) reconstruction algorithm requires a long computation time. To overcome this problem multiprocessor machines could be used. In this paper a parallel implementation of the algorithm for positron emission tomography (PET) images is presented. To cope with the difficulties involved with parallel programming a programming environment based on a visual language has been used. %0 Journal Article %A Batcher, K.E. %D 1968 %T Sorting Networks and Their Applications %J 1968 Spring Joint Computer Conference %V 32 %P 307-314 %0 Journal Article %A Batcher, K. E. %D 1980 %T Design of a Massively Parallel Processor %J IEEE Transactions on Computing %V C-29 %P 836-840 %0 Journal Article %A Batcher, K.E. %D 1982 %T Bit-serial Parallel Processing Systems %J IEEE Trans. Computer %V C-31 %N 5 %P 377-384 %0 Journal Article %A Baudet, G. %A Stevenson, D. %D 1978 %T Optimal Sorting Algorithms for Parallel Computers %J IEEE Transactions on Computers %V C-27 %N 1 %P 84-87 %0 Journal Article %A Baudet, G. %A Brent, R.P. %A Kung, H.T. %D 1980 %T parallel Execution of a Sequence of Tasks on an Asynchronous Multiprocessor %J The Australian Computer Journal %V 12 %P 105-112 %0 Conference Proceedings %A Baudet, G.M. %D 1981 %T On the Area Required by VLSI Circuits %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 100-107 %0 Journal Article %A Bauer, M. A. %A Feeney, S. T. %A Gargantini, I. %D 1994 %T Parallel 3-D filling with octrees %J Journal of Parallel and Distributed Computing %V 22 %N 1 %P 121-8 %X There are a number of different algorithms which attempt to perform the reconstruction of a volume representation (filling) of an object given some level of border representation for the object. These algorithms usually fall into two main categories: connectivity labeling, which digitizes polygons in space and fills the corresponding enclosed volumes, and filling by quadrants or octants which finds the interior of a previously digitized border. An algorithm in the second category presented by Atkinson, Gargantini and Walsh (1986) encodes information within the border elements of an object indicating in which direction the outer normal points at that point on the edge (for 2-D objects) or surface (for 3-D objects) of the object. This paper described a parallel algorithm that has been developed based on this approach using the shared memory, multiprocessor model and reports on its implementation. %0 Journal Article %A Baum, Daniel R. %A Winget, James M. %D 1990 %T Real Time Radiosity Through Parallel Processing and Hardware Accelaration %J Computer Graphics %V 24 %N 2 %P 67-75 %0 Conference Proceedings %A Baxter, B. %A Cox, G. %A Gross, T. %A Kung, H. T. %A O'Hallaron, D. %A Peterson, C. %A Webb, J. %A Wiley, P. %D 1990 %T Building Blocks for a New Generation of Application-Specific Computing Systems %J International Conference on Application Specific Array Processors %C Princeton, NJ %0 Journal Article %A Bayer, R. %A Haerder, T. %D 1978 %T Preplanning of Disk Merges %J Computing %V 21 %N 1 %P 1-16 %0 Generic %A BBN Laboratories %D 1985 %T The Uniform System Approach to Programming the Butterfly Parallel Processor %7 1 %9 Computer manual %0 Generic %A BBN Laboratories %D 1986 %T Butterfly Parallel Processor Overview %9 BBN Advanced Computers Inc. %0 Conference Proceedings %A Beke %A Herman %A Sansen, Willy %D 1979 %T CALMOS: A Portable Software System for the Automatic and Interactive Layout of MOS LSI %J Sixteenth Design Automation Conference %0 Report %A Belloch, G. E. %D 1992 %T A Nested Data-Parallel Language %I Carnegie Mellon University, School of Computer Science %R CMU-CS-92-103 %0 Generic %A Bentley, J.L. %A Ottmann, T. %A Widmayer, P. %T The complexity of manipulating hierarchically defined sets of rectangles %0 Conference Proceedings %A Bentley, J.L. %A Kung, H.T. %D 1979 %T A Tree Machine for Searching Problems %J Proceedings of 1979 International Conference on Parallel Processing %P 257-266 %0 Journal Article %A Bentley, J.L. %D 1980 %T A Parallel Algorithm for Constructing Minimum Spanning Trees %J Journal of Algorithms %V 1 %P 51-59 %0 Journal Article %A Bentley, J.L. %A Wood, D. %D 1980 %T An Optimal Worst-Case Algorithm for Reporting Intersections of Rectangles %J IEEE Transactions on Computers %V C-29 %0 Conference Proceedings %A Bentley, J.L. %A Haken, D. %A Hon, R. %D 1980 %T Fast Geometric Algorithms for VLSI Tasks %J COMPCON Spring '80 %0 Report %A Bentley, J.L. %A Haken, D. %A R.W., Hon %D 1980 %T Statistics on VLSI Designs %0 Conference Proceedings %A Bentley, J.L. %A Ottmann, T. %D 1981 %T The complexity of manipulating hierarchically defined sets of rectangles %J Tenth Symposium on Mathematical Foundations of Computer Science %0 Journal Article %A Bentley, J.L. %A Kung, H.T. %D 1983 %T An Introduction to Systolic Algorithms and Architectures %J Naval Research Reviews %V XXXV %N Two %P 3-16 %0 Journal Article %A Bentley, J. %D 1986 %T Little Languages %J Communications of the ACM %V 29 %N 8 %P 711-21 %0 Journal Article %A Berglend, Glenn D. %D 1969 %T Fast Fourier Transform Hardware Implementations - an Overview %J IEEE Transactions on Audio Electroacoustics %V AU-17 %P 104-108 %0 Conference Proceedings %A Bernard, T. %A Garda, P. %A Reichart, A. %A Zavidovique, B. %A Devos, F. %D 1988 %T Design of a Half-toning Integrated Circuit Based on Analog Quadratic Minimization by Non Linear Multistage Switched Capacitor Network %J IEEE International Symposium on Circuits and Systems %C Espoo, Finland %P 1217-20 %0 Report %A Bertero, M. %A Poggio, T. %A Torre, V. %D 1987 %T Ill-posed problems in early vision %I Artificial Intelligence Laboratory, Massachusetts Institute of Technology %R 924 %0 Conference Proceedings %A Bhandarkar, Suchendra M. %A Arabnia, Hamid R. %D 1994 %T Parallelizations of Computer Vision Algorithms on a Reconfigurable Multiprocessor %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 240-244 %0 Conference Proceedings %A Bigiliardo, M. %A Furnari, M. Mango %T Vision Analysis: A Testbed for Structured Parallelism Programming %J PF-ISCP RT.4 ??? %C Spain? %0 Conference Proceedings %A Bilardi, G. %A Pracchi, M. %A Preparata, F.P. %D 1981 %T A Critique and an Appraisal of VLSI Models of Computation %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 81-88 %0 Conference Proceedings %A Bimbo, A. Del %A Nesi, P. %D 1993 %T Optical Flow Estimation on the Connection-Machine CM-2 %J Workshop on Computer Architectures for Machine Perception %E Bayoumi, Magdy A. %E Davis, Larry S. %E Valavanis, Kimon P. %I IEEE Computer Society %C New Orleans, LA %P 267-274 %0 Conference Proceedings %A Binacardi, A. %A Rubini, A. %D 1994 %T PACCO - A New Approach for an Effective I.P. Environment %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 395-398 %0 Book %A Bindo, K. %D 1978 %T Monte Carlo Methods in Statistical Physics %I Spring-Verlag %0 Conference Proceedings %A Bischof, H. %A Kropatsch, W. G. %D 1993 %T Neural networks versus image pyramids %J Artificial Neural Nets and Genetic Algorithms. Proceedings of the International Conference %P 145-53 %X Neural networks and image pyramids are massively parallel processing structures. In this paper, we exploit the similarities as well as the differences between these structures. The general goal is to exchange knowledge between these two fields. After introducing the basic concepts of neural networks and image pyramids we give a translation table of the vocabulary used in image pyramids and those used in neural networks. Image pyramids which store and process numerical information (e.g. grey values of pixels) are very similar to neural networks. Therefore we concentrate on 'symbolic pyramids'. The main idea is to replace a cell of the pyramid by a small neural network, in order to represent and process symbolic information. We consider local as well as distributed representations for symbolic information. In particular we present a neural implementation of the 2*2/2 curve pyramid. We derive some general rules for implementing symbolic pyramids by neural networks. Finally we briefly discuss the role of learning in image pyramids. %0 Conference Proceedings %A Bischof, Horst %A Bertin, Etienne %A Bertolino, Pascal %D 1994 %T Voronoi Pyramids and Hopfield Networks %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 330-333 %0 Conference Proceedings %A Bisiani, B. %A Foster, M.J. %A Kung, H.T. %A Oflazer, K. %D 1982 %T MISE: Machine for In-System Evaluation of Custom VLSI Chips for Real-Time Systems %J Proceedings of Real-Time Systems Symposium %P 211-220 %0 Journal Article %A Biswas, P. K. %A Chatterji, B. N. %D 1994 %T Surface description in range images-a parallel approach %J Indian Journal of Pure and Applied Mathematics %V 25 %N 1-2 %P 205-30 %K range images; surface description; parallel rule based system ; structural shape; 3-D objects approach; mathematical analysis; qualitative reasoning; special purpose shared memory architecture %X This paper describes a parallel rule based system which obtains a structural shape from range images. The system uses a hierarchical description of 3-D objects approach to obtain higher level surface description from lower level ones. Instead of a detailed mathematical analysis, qualitative reasoning by rule based deduction is used to obtain the surface description. The rule bases are also hierarchical. A special purpose shared memory architecture is suggested which supports parallel application of rules. %0 Journal Article %A Bitz, F. %A Kung, H. T. %D 1988 %T Path planning on the Warp computer: using a linear systolic array in dynamic programming %J International Journal of Computer Mathematics %V 25 %N 3-4 %0 Conference Proceedings %A Blackmer, J. %A Frank, G. %A Kuekes, P. %D 1981 %T A 200 Million Operations per Second (MOPS) Systolic Processor %J Proceedings of SPIE Symposium, Vol. 298, Real-Time Signal Processing IV %P 10-18 %0 Conference Proceedings %A Blank, T. %D 1990 %T The MASPAR MP-1 Architecture %J Thirty-Fifth IEEE Computer Society International Conference - Compcon Spring 90 %C San Francisco, CA %P 20-4 %0 Report %A Blankenship, P.E. %D 1981 %T Restructurable VLSI Program %0 Journal Article %A Blelloch, G. %D 1989 %T Scans as Primitive Parallel Operations %J IEEE Transactions on Computers %V 38 %N 11 %P 1526-1538 %0 Personal Communication %A Blelloch, G. %D 1990 %X Commented that the best algorithm for connected components on the Connection Machine (2) was based on scans and simply propagating labels in multiple directions, not anything fancy. %0 Book %A Blelloch, G. %D 1990 %T Vector Models for Data-Parallel Computing %I MIT Press %0 Conference Proceedings %A Blelloch, G. %A Chatterjee, S. %D 1990 %T VCODE: A data-parallel intermediate language %J IThird Symposium on the Frontiers of Massively Parallel Computing %P 471-80 %0 Journal Article %A Blelloch, G. E. %A W., Sabot G. %D 1990 %T Compiling collection-oriented languages onto massively parallel computers %J Journal of Parallel and Distributed Computing %V 8 %N 2 %P 119-34 %0 Journal Article %A Blelloch, Guy E. %A Hardwick, Jonathan C. %A Sipelstein, Jay %D 1994 %T Implementation of a Portable Nested Data-Parallel Language. %J Journal of parallel and distributed computing %V 21 %N 1 %P 4-14 %0 Journal Article %A Bojanczyk, A. %A Brent, R.P. %A Kung, H.T. %D 1984 %T Numerically Stable Solution of Dense Systems of Linear Equations Using Mesh-Connected Processors %J SIAM Journal on Scientific and Statistical Computing %V 5 %N 1 %P 95-104 %0 Journal Article %A Bolles, R. C. %A Horaud, P. %D 1986 %T 3DPO: A Three-Dimensional Part Orientation System %J International Journal of Robotics Research %V 5 %N 3 %P 3-26 %0 Report %A Bonneau, R.J. %D 1973 %T A Class of Finite Computation Structures Supporting the Fast Fourier Transform %0 Conference Proceedings %A Bono, C. M. %A Webb, J. A. %D 1988 %T Object Recognition on a Systolic Array %J Third International Conference on Supercomputing %E Kartashev, Lana Kartashev and Steven %I International Supercomputing Institute, Inc. %C Boston, MA %0 Report %A Bono, C. M. %A Webb, J. A. %D 1988 %T Object Recognition on a Systolic Array %I Robotics Institute, Carnegie Mellon University %8 1987 %R CMU-RI-TR-87-21 %0 Conference Proceedings %A Borkar, S. %A Cohn, R. %A Cox, G. %A Gleason, S. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Moore, B. %A Peterson, C. %A Pieper, J. %A Rankin, L. %A Tseng, P. S. %A Sutton, J. %A Urbanski, J. %A Webb, J. %D 1988 %T iWarp: An Integrated Solution to High-Speed Parallel Computing %J Proceedings of Supercomputing '88 %C Orlando, Florida %P 330-339 %0 Conference Proceedings %A Borkar, S. %A al., et %D 1990 %T Supporting Systolic and Memory Communication in iWarp %J 17th Annual International Symposium on Computer Architecture %C Seattle, Washington %0 Conference Proceedings %A Borkar, S. %A Cohn, R. %A Cox, G. %A Gross, T. %A Kung, H. T. %A Lam, M. %A Levine, M. %A Moore, B. %A Peterson, C. %A Susman, J. %A Sutton, J. %A Urbanski, J. %A Webb, Jon A. %D 1990 %T Supporting Systolic and Memory Communication in iWarp %J 17th International Symposium on Computer Architecture %C Seattle, WA %0 Conference Proceedings %A Borodin, A. %A von zur Gathen, J. %A Hopcroft, J. %D 1982 %T Fast Parallel Matrix and GCD Computations %J Proceedings of the 23rd Annual Symposium on Foundations of Computer Science %P 65-71 %0 Conference Proceedings %A Boulanger, P. %A Blais, F. %D 1993 %T Range image segmentation, free space determination, and position estimate for a mobile vehicle %J Mobile Robots VII. %I SPIE %C Boston, MA %P 444-55 %X Two processing methods using range data are shown to perform different navigation tasks for a mobile vehicle. The first, a low-level processing method based on mathematical morphology, computes in real time, the free space and is used for collision avoidance. A parallel between this method and polar histogram techniques is drawn. The second method, based on a hierarchical segmentation technique, can extract a multiple resolution description of the range data produced by the sensor. This segmentation is used to describe the immediate environment of the vehicle using simple geometrical primitives, refine the vehicle position estimate, and create a detailed representation of the immediate environment of the vehicle. Experimental results using the BIRIS range sensor are shown. %0 Conference Proceedings %A Bourdon, O. %A Medioni, G. %D 1990 %T Object Recognition Using Geometric Hashing on the Connection Machine %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 596-600 %0 Conference Proceedings %A Bove, V. M. Jr %D 1993 %T Hardware and software implications of representing scenes as data %J Icassp %I IEEE %C Minneapolis, MN %6 5 %P 121-4 %X Digital video is often perceived as valuable for reasons of data compression and robustness against noise, but it is less often considered that a fairly complex computational device mediates between the stored or transmitted bit stream and the display. The author explores some of the possibilities inherent in the source-to-display decoupling made possible in a digital video system, and examines the implications for both the digital video representation and the decoding device. The essential idea is to use the computation involved in both creating and decoding the bit stream to decouple the origination of the imagery from its ultimate viewing. A general-purpose CPU was combined with several specialized coprocessors and a full crosspoint switch, allowing both pipelining and parallel processing to take place between the communications channel and the display. This architecture has been realized in the Cheops Imaging System described by the author and J.A. Watlington (Proc. SPIE-Int. Soc. Opt. Eng., vol. 1605, p. 886-93 of 1991) which comprises a hardware and software architecture for processing image sequence data and structured scene representations in real time. %0 Book %A Bowen, B.A. %A Brown, W.R. %D 1982 %T Signal Processing and Signal Processors %I Prentice-Hall, Inc. %C Englewood Cliffs, New Jersey %V 1 %0 Conference Proceedings %A Box, B. %D 1994 %T Field programmable gate array based reconfigurable preprocessor %J Proceedings Ieee Workshop on FPGAs for Custom Computing Machines %E Buell, D.A. %E Pocek, K.L. %I IEEE Computer Society Press %C Napa Valley, CA %P 40-8 %X Custom hardware implementations of preprocessors are seldom reusable, flexible enough to allow algorithm exploration or quickly realized. The Configurable Hardware Algorithm Mappable Preprocessor (CHAMP) technology is a solution to these problems. Recent developments in FPGA hardware and software have made a reconfigurable preprocessor with custom hardware performance but generic hardware flexibility possible. The key advancements are larger, faster RAM and electrically erasable devices, routers with deadline timers, and synthesis tools which can work with user-definable macros. Ongoing work in the areas of partitioning, synthesis, placement, packaging and compilation will make reconfigurable preprocessors more powerful. The present CHAMP implementation is based on Xilinx FPGAs. Its architecture consists of multiple reconfigurable processing elements connected through both a ring network and a global crossbar network. It is packaged as a VME 6U*160 slave board with two high-speed reconfigurable parallel interfaces. In order to allow development at the algorithm level while retaining preprocessor performance, off-the-shelf development tools have been integrated with a custom library of macros as part of the CHAMP design process. As a verification of the CHAMP technology, an advanced IR missile warning application was mapped onto the CHAMP architecture achieving greater than 1 billion operations/sec of real-time throughput while utilizing 75% of the CHAMP board's processing resources. %0 Journal Article %A Boyer, R. S. %A Moore, J. S. %D 1977 %T A Fast String Searching Algorithm %J Communications of the ACM %V 20 %N 10 %P 762 %0 Journal Article %A Bozkus, Zeki %A Choudhary, Alok %A Fox, Geoffrey %D 1994 %T Compiling Fortran 90D/HPF for Distributed Memory MIMD Computers %J Journal of parallel and distributed computing %V 21 %N 1 %P 15-26 %0 Conference Proceedings %A Brady, M. %A Brint, A. %A Dickson, W. %A Foulkes, P. %A McIvor, A. %A Scott, G. %D 1988 %T Vision and the Oxford AGV %J Image Processing '88 %C London, UK %0 Book Section %A Brady, M. %A Scott, G. %D 1988 %T Parallel Algorithms for Shape Representation %B Parallel Architectures and Computer Vision %E Page, I. %I Oxford Science %P 97-118 %0 Conference Proceedings %A Brady, M. L. %A Yong, W. %D 1992 %T Fast parallel discrete approximation algorithms for the radon transform %J Spaa '92. 4th Annual Acm Symposium on Parallel Algorithms and Architectures %I ACM %C San Diego, CA %P 91-9 %X Addresses fast parallel methods for the computation of the radon (Hough) transform (RT). The RT of an image is a set of projections of the image taken at different angles. Its computation is extremely important in image processing and computer vision, for problems such as pattern recognition and reconstruction of CAT scan images. We present a unique new method for combining partial results which allows us to construct a parallel algorithm which computes an approximation to the RT in O(log N) time for an N*N input array, using O(N/sup 2/) processors. This is a lower processor-time product than all previous techniques. The method appears to be quite simple and practical. In addition, this algorithm appears to be quite well-suited to implementation on strict SIMD array-type computers. We discuss SIMD- parallel mappings of the algorithm for mesh, butterfly, and hypercube architectures. %0 Journal Article %A Brent, R. P. %D 1970 %T On the addition of binary numbers %J IEEE Transactions on Computers %V C-19 %P 758-759 %0 Conference Proceedings %A Brent, R.P. %D 1976 %T The Complexity of Multiple-precision Arithmetic %J The Complexity of Computational Problem Solving %E Anderssen, R.S. and Brent, R.P. %C Brisbane, Australia %P 126-165 %0 Conference Proceedings %A Brent, R.P. %D 1976 %T Analysis of the Binary Euclidean Algorithm %J New Directions and Recent Results in Algorithms and Complexity %E Traub, J.F. %I Academic Press %P 321-355 %0 Journal Article %A Brent, R.P. %D 1980 %T An Improved Monte Carlo Factorization Algorithm %J BIT %V 20 %P 176-184 %0 Journal Article %A Brent, R.P. %A Kung, H.T. %D 1980 %T On the Area of Binary Tree Layouts %J Information Processing Letters %V 11 %N 1 %P 46-48 %0 Conference Proceedings %A Brent, R.P. %A Kung, H.T. %D 1980 %T The Chip Complexity of Binary Arithmetic %J Proceedings of the Twelfth Annual ACM Symposium on Theory of Computing %P 190-200 %0 Journal Article %A Brent, R.P. %A Gustavson, F.G. %A Yun, D.Y.Y. %D 1980 %T Fast Solution of Toeplitz Systems of Equations and Computation of Pade Approximants %J Journal of Algorithms %V 1 %N 3 %P 259-295 %0 Journal Article %A Brent, R.P. %A Kung, H.T. %D 1981 %T The Area-Time Complexity of Binary Multiplication %J Journal of the ACM %V 28 %N 3 %P 521-534 %0 Journal Article %A Brent, R.P. %A Pollard, J.M. %D 1981 %T Factorization of the Eighth Fermat Number %J Math. Comp. %V 36 %P 627-630 %0 Journal Article %A Brent, R.P. %A Kung, H.T. %D 1982 %T A Regular Layout for Parallel Adders %J IEEE Transactions on Computers %V C-31 %N 3 %P 260-264 %0 Report %A Brent, R.P. %A Kung, H.T. %D 1982 %T Systolic VLSI Arrays for Integer GCD Computation %0 Report %A Brent, R.P. %A Luk, F.T. %D 1982 %T A Systolic Architecture for Almost Linear-Time Solution of the Symmetric Eigenvalue Problem %0 Report %A Brent, R.P. %A Luk, F.T. %D 1982 %T A Systolic Architecture for the Singular Value Decomposition %0 Journal Article %A Brent, R.P. %A Luk, F.T. %D 1983 %T A Systolic Array for the Linear-Time Solution of Toeplitz Systems of Equations %J Journal of VLSI and Computer Systems %V 1 %N 1 %P 1-22 %0 Conference Proceedings %A Brent, R.P. , Kung, H.T. %A Luk, F.T. %D 1983 %T Some Linear-Time Algorithms for Systolic Arrays %J Proceedings of the IFIP 9th World Computer Congress %E Mason, R. %P 865-876 %0 Conference Proceedings %A Brent, R.P. %A Luk, F.T. %A Van Loan, C. %D 1983 %T Computation of the Generalized Singular Value Decomposition Using Mesh-Connected Processors %J Proceedings of SPIE Symposium, Vol. 431, Real-Time Signal Processing VI %P 66-71 %0 Journal Article %A Brent, R.P. %A Kung, H.T. %D 1984 %T Systolic VLSI Arrays for Polynomial GCD Computation %J IEEE Transactions on Computers %V C-33 %N 8 %P 731-736 %0 Book %A Brigham, E. %D 1974 %T The Fast Fourier Transform %I Prentice Hall %C Englewood Cliffs, New Jersey %0 Conference Proceedings %A Bromley, K. %A Symanski, J.J. %A Speiser, J.M. %A Whitehouse, H.J. %D 1981 %T Systolic Array Processor Developments %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 273-284 %0 Conference Proceedings %A Bromley, M. %A Heller, S. %A McNerney, T. %A Steele, G., Jr. %D 1991 %T Fortran at Ten Gigaflops: The Connection Machine Convolution Compiler %J ACM SIGPLAN '91 Conference on Programming Language Design and Implementation %C Toronto, Canada %P 145-54 %0 Journal Article %A Bronson, E. C. %A Casavant, T. L. %A Jamieson, L. H. %D 1990 %T Experimental Application-Driven Architecture Analysis of an SIMD/MIMD Parallel Processing System %J Transacation on Parallel and Distributed Systems %V 1 %P 195-205 %0 Journal Article %A Brooks, Rodney A. %D 1986 %T A Robust Layered Control System for a Mobile Robot %J IEEE Journal of Robotics and Automation %V RA-2 %N 1 %P 14-23 %0 Conference Proceedings %A Brown, D.J. %A Rivest, R.L. %D 1981 %T New Lower Bounds for Channel Width %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 178-185 %0 Conference Proceedings %A Brown, Christopher M. %D 1988 %T Parallel Vision with the Butterfly Computer %J Third International Conference on Supercomputing %C Boston, MA %P 54-68 %0 Personal Communication %A Brown, Christopher %D 1994 %T Personal Communication. Comments on active vision and parallel systems. %8 February 23 %9 Electronic mail %0 Journal Article %A Brown, J. %A Crookes, D. %D 1994 %T A high level language for parallel image processing %J Image and Vision Computing %V 12 %N 2 %P 67-79 %X Most published research in the field of parallel image processing has tended to be in the areas of parallel architectures and parallel algorithms. Work on the development of software tools such as languages has generally been less extensive. This paper describes some research which is intended to redress the balance a little, by describing I-BOL-an application-specific high level programming language intended for implementing low-level image processing applications on parallel architectures. In particular, I-BOL has been designed to be capable of implementation on distributed memory parallel machines such as transputer networks. This paper introduces the core concepts of I-BOL: its view of an image as a set of tuples; user-defined neighbourhood functions; and I-BOL's facilities for recursive image processing. Solutions to a number of example problems illustrate particular aspects of the notation, including the distance transform, histogram equalization and the Hough transform. Some consideration is given to the parallel aspects of the current implementation of I-BOL on a pipeline of transputers. A few performance measurements are quoted, giving execution times for the chosen examples on various sizes of transputer work. %0 Generic %A Browning, S. %T Algorithms for the Tree Machine %0 Conference Proceedings %A Bruegge, B. %A Chang, C. %A Cohn, R. %A Gross, T. %A Lam, M. %A Lieu, P. %A Noaman, A. %A Yam, D. %D 1987 %T Programming Warp %J COMPCON Spring '87 %P 268-271 %0 Conference Proceedings %A Bruegge, B. %A Chang, C. %A Cohn, R. %A Gross, T. %A Lam, M. %A Lieu, P. %A Noaman, A. %A Yam, D. %D 1987 %T The Warp Programming Environment %J Proceedings of the 1987 National Computer Conference %P 141-148 %0 Conference Proceedings %A Bruegge, B. %A Gross, T. %D 1988 %T An Integrated Environment for Development and Execution of Real-Time Programs %J Conference Proceedings of 1988 International Conference on Supercomputing %I ACM %C St. Malo, France %P 153-162 %0 Conference Proceedings %A Brunzema, Martin %A Burmeiste, Horst %A Gerogiannis, Dimitris %D 1994 %T Parallelization of an Image Analysis Application: Problems, Results and a Solution Framework %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 406-411 %0 Conference Proceedings %A Brzakovic, D. %A Vujovic, N. %D 1994 %T Development Environment for Designing and Testing Inspection Systems %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 366-369 %0 Conference Proceedings %A Bucher, I. Y. %D 1983 %T The computational speed of supercomputers %J ACM SIGMETRICS Conference on Measurement and Modelling of Computer Systems %0 Journal Article %A Buell, D. A. %A Carlson, D. A. %A Chow, Y.-C. %A Culik, K. %A Deo, N. %A Finkel, R. %A Houstis, E. N. %A Jacobson, E. M. %A Kedem, Z. M. %A Kowalik, J. S. %A Kuekes, P. J. %A Martin, J. L. %A Michael, G. A. %A Ostlund, N. S. %A Potter, J. %A Pardhan, D. K. %A Quinn, M. J. %A Stewart, G. S. %A Stout, Q. F. %A Watson, L. %A Webb, J. %D 1988 %T Parallel algorithms and architectures: report of a workshop %J The Journal of Supercomputing %V 1 %P 301-325 %0 Journal Article %A Bulthoff, H. %A Little, J. %A Poggio, T. %D 1989 %T A Parallel Algorithm for Real-time Computation of Optical Flow %J Nature %V 337 %N 6207 %P 549-53 %0 Conference Proceedings %A Burt, P. J. %A van der Wal, G. S. %D 1987 %T Iconic Image Analysis with the Pyramid Vision Machine (PVM) %J 1987 Workshop on Computer Architecture for Pattern Analysis and Machine Intelligence %C Seattle, WA %P 137-44 %0 Conference Proceedings %A Burt, P. J. %A van der Wal, G. S. %D 1990 %T An Architecture for Multiresolution, Focal, Image Analysis %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 305-11 %0 Journal Article %A Butler, C. S. %A Miller, M. I. %A Miller, T. R. %A Wallis, J. W. %D 1994 %T Massively parallel computers for 3D single-photon-emission computed tomography %J Physics in Medicine and Biology %V 39 %N 3 %P 575-82 %K massively parallel computers ; 3D single photon emission computed tomography; expectation-maximization algorithm; maximum-likelihood estimates; maximum a posteriori estimates; SPECT; 3D reconstruction; computational complexity; 16,000 processor MasPar machine; Siemens Orbiter rotating camera; nuclear medicine; medical diagnostic imaging COMPUTERISED TOMOGRAPHY; IMAGE RECONSTRUCTION; MEDICAL IMAGE PROCESSING ; PARALLEL ALGORITHMS; RADIOISOTOPE SCANNING AND IMAGING %X Since the introduction of the expectation-maximization (EM) algorithm for generating maximum-likelihood (ML) and maximum a posteriori (MAP) estimates in emission tomography, there have been many investigators applying the ML method. However, almost all of the previous work has been restricted to two-dimensional (2D) reconstructions. The major focus and contribution of this paper is to demonstrate a fully three-dimensional (3D) implementation of the MAP method for single-photon-emission computed tomography (SPECT). The 3D reconstruction exhibits an improvement in resolution when compared to the generation of the series of separate 2D slice reconstructions. As has been noted, the iterative EM algorithm for 2D reconstruction is highly computational; the 3D algorithm is far worse. To accommodate the computational complexity, the authors have extended their previous work in the 2D arena and demonstrate an implementation on the class of massively parallel processors of the 3D algorithm. Using a 16,000 processor MasPar machine, the algorithm is demonstrated to execute at 1.24 S/EM iteration for the entire 64*64*64 cube of 64 planar measurements obtained from the Siemens Orbiter rotating camera operating in the high-resolution mode. %0 Book Section %A Buxton, B. F. %A Buxton, H. %A Kashko, A. %D 1988 %T Optimization Regularization and Simulated Annealing in Low-Level Computer Vision %B Parallel Architectures and Computer Vision %E Page, I. %I Oxford Science %P 1-18 %0 Conference Proceedings %A Buzbee, B. %A Golub, G. %A Howell, J. %D 1977 %T Vectorization for the CRAY-1 of Some Methods for Solving Elliptic Difference Equations %J High Speed Computer and Algorithm Organization %E Kuck, D. J., Lawrie, D. H. and Sameh, A. H. %I Academic Press %0 Conference Proceedings %A Bker, Ulrich %A Martsching, Brbel %D 1994 %T A Communication Module for Parallel Image Analysis on the Transputer Image Processing System %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 327-329 %0 Conference Proceedings %A Camahort, Emilio %A Chakravarty, Indranil %D 1993 %T Inegrating Volume Data Analysis and Rendering on Distributed Memory Architectures %J Parallel Rendering Symposium %C San Jose, CA %P 89-96 %0 Journal Article %A Canny, J. %D 1986 %T A Computational Approach to Edge Detection %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 6 %N 6 %P 679-98 %0 Conference Proceedings %A Cantoni, V. %A Griffini, A. %A Lombardi, L. %D 1989 %T Stereo Vision in Multi-Resolution %J 5th International Conference on Image Analysis and Processing. Progress in Image Analysis and Processing %I World Scientific %C Positano, Italy %P 706-13 %0 Journal Article %A Cantoni, V. %A di Gesu, V. %A Ferretti, M. %A Levialdi, S. %A Negrini, R. %A Stefannelli, R. %D 1991 %T The PAPIA System %J Journal of VLSI Signal Processing %V 2 %N 4 %P 195-217 %0 Conference Proceedings %A Cantoni, V. %A Lombardi, L. %A Cinque, L. %A Levialdi, S. %A Guerra, C. %D 1994 %T Recognizing 2D Objects by a Multi-Resolution Approach %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 310-316 %0 Conference Proceedings %A Cappello, P.R. %A K., Steiglitz %D 1981 %T Digital Signal Processing Applications of Systolic Algorithms %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 245-254 %0 Conference Proceedings %A Carlsohn, M. F. %D 1992 %T Near real-time pattern recognition in a special purpose computer with parallel architecture %J Real Time Computing. Proceedings of the Nato Advanced Study Institute %E Halang, W.A. %E Stoyenko, A.D. %C Sint Maarten, Dutch Antilles %P 676-7 %K real-time pattern recognition; special purpose computer; parallel architecture ; image pattern recognition; features; object classification; computational complexity; time consumption; segmentation method; feature extraction FEATURE EXTRACTION; IMAGE PROCESSING EQUIPMENT; IMAGE RECOGNITION; IMAGE SEGMENTATION; PARALLEL ARCHITECTURES; REAL-TIME SYSTEMS; SPECIAL PURPOSE COMPUTERS %X In computer vision the term real-time possesses some uncertainty, because of the demands defined by standard camera sensors and the requirements of the processes under inspection sometimes differ by orders of magnitude. In image pattern recognition, the segmentation of interesting image objects from their image background and the characterization of the object properties by their features are the prerequisites for an object classification. Both process steps are usually of great computational complexity and time consumption, respectively. Consequently, processing in video real-time is only possible by a supporting computer architecture. The presented system is a hybrid hard- and software implementation of a region based and scan line-oriented segmentation method including an inherent feature extraction. A set of concurrent single processes are mapped onto an appropriate parallel processor architecture. %0 Report %A Cater, J. E. %A Sullivan, F. J. M. %D 1981 %T Processing architecture for sonobuoy thinned random array %0 Journal Article %A Caulfield, H.J. %A Rhodes, W.T. %A Foster, M.J. %A Horvitz, S. %D 1981 %T Optical Implementation of Systolic Array Processing %J Optics Communications %V 40 %N 2 %P 86-90 %0 Book %A Cavanagh, J.J.F. %D 1984 %T Digital Computer Arithmetic: Design and Implementation %I McGraw-Hill %C New York %0 Journal Article %A Cecchini, R. %A Bimbo, A. Del %D 1993 %T A Programming Environment for Imaging Applications %J Pattern Recognition Letters %V %P 877-881 %0 Conference Proceedings %A Chakrabarti, C. %A Ja Ja , J. F. %D 1990 %T A Parallel Algorithm for Template Matching on an SIMD Mesh Connected Computer %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 362-7 %0 Conference Proceedings %A Chalmers, Alan G. %A Paddon, Derek J. %D 1991 %T Parallel Processing of Pregressive Refinement Radiosity Methods %J Second Euorgraphics Workshop on Rendering %C Barcelona, Spain %0 Conference Proceedings %A Champeau, J. %A Le Pape, L. %A Pottier, B. %A Rubini, S. %A Gautrin, E. %A Perraudeau, L. %D 1994 %T Flexible parallel FPGA-based architectures with ArMen %J Proceedings of the Twenty Seventh Hawaii Internation Conference on System Sciences %E Mudge, T.N. %E Shriver, B.D. %I IEEE Comput. Soc. Press %C Wailea, HI %P 105-13 %K flexible parallel FPGA-based architectures ; ArMen; parallel machine ; global coprocessors; cellular automata; image processing ; industrial control; MADMACS pattern generator CELLULAR AUTOMATA; IMAGE PROCESSING ; LOGIC ARRAYS; PARALLEL ARCHITECTURES; PARALLEL MACHINES %X ArMen is a parallel machine in which each node is coupled to an FPGA ring. The underlying idea is to complement an MIMD architecture with global coprocessors providing extra control and processing properties. The use of regular hardware patterns such as cellular automata or pipelines allows high level definitions of the coprocessors. The results are fast prototyping possibilities for specific applications such as image processing or industrial control. Basic realizations are described. Changing from an FPGA technology to a VLSI one provider benefits with respect to cost and performance, without any effort at the specification level. The MADMACS pattern generator can be used to fold several FPGA configurations into the same VLSI circuit. %0 Conference Proceedings %A Chan, K. L. %A Tsui, W. M. %A Chan, H. Y. %A Wong, H. Y. %A Lai, H. C. %D 1993 %T Parallelising image processing algorithms %J Proceedings Tencon '93 %E Baozong, Yuan %I IEEE %C Beijing, China %6 5 %P 942-4 %X Multiprocessor machines provide increased computational power and memory capacity that can be used to achieve tasks involving large amounts of data, such as imaging . With multiprocessor machines, many sophisticated operations on image data can be accomplished within reasonable time constraints. In order to efficiently utilize multiprocessor machines, conventional image processing algorithms have to be parallelised. The design of parallel algorithms takes into account many considerations, e.g. interprocessor communication, load balancing, task division, task placement, scalability, network topology, etc. In this paper, the performance of some image processing algorithms running on a loosely-coupled multiprocessor machine is evaluated. The machine consists of a PC host computer and a multiprocessor network consisting of a number of transputers. The configuration of this transputer network is under software control and so different parallelisations of a particular algorithm can be tested on a particular network topology. Three image processing algorithms were selected for parallelisation. They are the Sobel edge operation, the fast Fourier transform and the Hough transform. Parallelism is achieved in various approaches, such as partitioning of tasks or partitioning of data. For a particular network configuration, the performance of different parallelisation approaches for each algorithm was assessed, based on the parallel processing time, overhead time, communication-to-computation ratio, efficiency, etc. %0 Journal Article %A Chanda, B. %A Haralick, R. M. %D 1994 %T Studies on properties of digital objects using mathematical morphology %J Indian Journal of Pure and Applied Mathematics %V 25 %N 1-2 %P 181-203 %K digital objects; mathematical morphology; geometric properties; connectivity; convexity; morphological operations; connectivity number; parallel machines ; image analysis; computer vision ; digital convexity %X Studies the geometric properties like connectivity and convexity of digital objects in terms of mathematical morphology. A new definition of digital convexity is suggested. Connectivity and convexity of digital objects obtained through morphological operations are investigated in the light of this new definition. The paper also presents some morphological algorithms for computing topological properties like connectivity number and genus. Operations are simpler, faster and can be implemented on parallel machines. %0 Generic %A Chang, T.L. %A Fisher, P. David %T Mixed Systolic Arrays: A Reconfigurable Multiprocessor Structure %0 Journal Article %A Charlesworth, A. E. %D 1981 %T An Approach to Scientific Array Processing: The Architectural Design of the AP-120B/FPS-164 Family %J Computer %V 14 %P 18-27 %0 Conference Proceedings %A Chatterjee, S. %A Blelloch, G. E. %A Zagha, M. %D 1990 %T Scan Primitives for Vector Computers %J Supercomputing '90 %C Los Alamitos, CA %P 666-75 %0 Conference Proceedings %A Chatterjee, S. %A Blelloch, G. %A Fisher, A. %D 1991 %T Size and Access Inference for Data-Parallel Programs %J ACM SIGPLAN '91 Conference on Programming Language Design and Implementation %C Toronto, Canada %P 130-44 %0 Thesis %A Chatterjee, S. %D 1991 %T Compiling Data-Parallel Programs for Efficient Execution on Shared-Memory Multicomputers %I Carnegie Mellon University %8 October %0 Journal Article %A Chaudhary, V. %A Aggarwal, J. K. %D 1993 %T A Generalized Scheme for Mapping Parallel Algorithms %J IEEE Transactions on Parallel and Distributed Systems %V 4 %P 328-346 %0 Conference Proceedings %A Chazelle, B.M. %A Monier, L.M. %D 1981 %T A Model of Computation for VLSI with Related Complexity Results %J Proceedings of the 13th Annual ACM Symposium on the Theory of Computing %P 318-325 %0 Conference Proceedings %A Chazelle, B.M. %A Monier, L.M. %D 1981 %T Optimality in VLSI %J First International Conference on Very Large Scale Integration %P 269-278 %0 Conference Proceedings %A Chazelle, B.M. %A Monier, L.M. %D 1981 %T Unbounded Hardware is Equivalent to Deterministic Turing Machines %J First conference on Foundations of Software Technology and Theoretical Computer Science %0 Conference Proceedings %A Chazelle, B.M. %A Monier, L.M. %D 1981 %T Towards More Realistic Models of Computation for VLSI %J Proceedings of the Second Caltech VLSI Conference %0 Report %A Chazelle %A Bernard %D 1982 %T An Improved Algorithm for the Fixed-Radius Neighbor Problem %0 Report %A Chazelle %A Bernard %D 1982 %T Computational Geometry on a Systolic Chip %0 Report %A Chazelle %A Bernard %D 1982 %T The Bottom-Left Bin-Packing Heuristic: An Efficient Implementation %0 Report %A Chazelle %A Bernard %D 1982 %T The Polygon Containment Problem %0 Journal Article %A Chen, W.H. %A Smith, C.H. %A Fralick, S.C. %D 1977 %T A Fast Computational Algorithm for Discrete Cosine Transform %J IEEE Trans. on Communications %V COM-25 %P 1004-1009 %0 Conference Proceedings %A Chen, T.C. %A Lum, V.Y. %A Tung, C. %D 1978 %T The Rebound Sorter: An Efficient Sort Engine for Large Files %J Proceedings of the 4th International Conference on Very Large Data Bases %P 312-318 %0 Conference Proceedings %A Chen, M.C. %A Mead, C.A. %D 1983 %T A Hierarchical Simulator Based on Formal Semantics %J Proceedings of the Third Caltech Conference on Very Large Scale Integration %E Bryant, R. %I Computer Science Press, Inc. %P 207-223 %0 Generic %A Chen, M. %D 1986 %T Talk given at the ONR 1986 Workshop on Systolic Processing %0 Conference Proceedings %A Chen, K. %A Danielsson, P.-E. %A Astroem, A. %D 1990 %T PASIC. A Sensor/Processor Array for Computer Vision %J Application Specific Array Processors %C Princeton, N. J. %P 352-66 %0 Conference Proceedings %A Chen, J.-S. %A Medioni, G. %D 1990 %T Parallel Multiscale Stereo Matching using Adaptive Smoothing %J Computer Vision - ECCV 90: First European Conference on Computer Vision %C Antibes, France %P 99-103 %0 Conference Proceedings %A Chen, Ling Tony %A Davis, Larry S. %D 1991 %T Parallel Processing of Image Contours %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 169-176 %0 Conference Proceedings %A Chen, C. M. %A Lee, S. Y. %A Cho, Z. H. %D 1992 %T 3D PET image reconstruction on a mesh connected multiprocessor %J Conference Record of the IEEE Nuclear Science Symposium and Medical Imaging Conference %I IEEE %C Orlando, FL %P 915-17 %K wrapped-around 2D mesh system; positron emission tomography; nuclear medicine; iterative reconstruction; medical diagnostic imaging ; 3D PET image reconstruction; mesh connected multiprocessor; practical parallel system ; highly efficient parallel algorithms ; medical environment; parallel GTTR algorithm ; EM algorithm; data partitioning; partition-by-view; communication patterns COMPUTERISED TOMOGRAPHY; IMAGE RECONSTRUCTION; MEDICAL IMAGE PROCESSING ; PARALLEL ALGORITHMS; PARALLEL PROCESSING; RADIOISOTOPE SCANNING AND IMAGING %X The authors describe a practical parallel system and highly efficient parallel algorithms for 3-D PET (positron emission tomography) image reconstruction. The proposed parallel system, a wrapped-around 2-D mesh system, is compact enough for the medical environment and scalable for various PET sizes. This system is capable of performing both analytic and iterative reconstructions efficiently. The authors use the GTTR and EM (expectation maximization) algorithms for the analytic and iterative approaches, respectively. For the parallel GTTR algorithm, a wrapped-around 2-D mesh communication pattern is proposed. For parallelization of the EM algorithm, a new task and data partitioning scheme, called partition-by-view, has been developed. The partition-by-view scheme is more efficient than schemes proposed previously since some communication can be overlapped with computation by using a new communication pattern, called the multiple ring. Both communication patterns can be embedded in a wrapped-around 2-D mesh. The parallel GTTR algorithm and the partition-by-view scheme have been implemented using image sizes of 64*64*64 and 40*40*16, respectively. High efficiency, i.e., greater than 90%, has been achieved for most of the cases tested. %0 Journal Article %A Chen, C.-M. %A Lee, S.-Y. %D 1994 %T On Parallelizing the EM Algorithm for PET Image Reconstruction. %J IEEE transactions on parallel and distributed systems %V 5 %N 8 %P 860-873 %0 Journal Article %A Chen, Chung-Ming %D 1994 %T An inhomogeneous partitioning based parallel EM algorithm for 3D PET image reconstruction %J Biomedical Engineering, Applications Basis Communications %V 6 %N 1 %P 34-40 %X One of the problems which prevents PET from being widely used is the long processing time required for reconstruction of a PET image. While the expectation-maximization (EM) reconstruction guarantees to converge to an image with the maximum likelihood, it takes much more time than its counterpart, i.e. the analytic algorithms, e.g. the filtered backprojection algorithm. To make true 3D PET practical the authors present a new parallel EM algorithm for 3D image reconstruction. The proposed parallel EM algorithm is more efficient than others in that it minimizes data sharing overhead by replicating shared data optimally and overlapping integration and broadcasting of shared data with computation. In theory, the authors show that the maximal improvement achievable by the proposed parallel EM algorithm over a parallel EM algorithm using a homogeneous partitioning scheme with the same group size is at least 50%. %0 Conference Proceedings %A Chen, Sarit %A Ginosar, Ran %D 1994 %T Adaptive Sensitivity CCD Image Sensor %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 363-365 %0 Conference Proceedings %A Cheng, Y. %A Jensen, J. R. %A Huntsberger, T. L. %A Huntsberger, B. A. %D 1994 %T Hypercube algorithm for image component labeling %J Proceedings of the Scalable High Performance Computing Conference %I IEEE Computer Society Press %C Knoxville, TN %P 259-62 %K hypercube algorithm; image component labeling; connected regions; digitized image; image analysis; computer vision ; higher level image operations; parallel algorithm ; component labeling algorithm; parallelized hybrid; sequential algorithms; nCUBE/10 hypercube system; time complexity; storage utilization COMPUTER VISION ; DISTRIBUTED MEMORY SYSTEMS; HYPERCUBE NETWORKS; IMAGE PROCESSING ; PARALLEL ALGORITHMS %X Labeling the connected regions of a digitized image is a fundamental computation in image analysis and computer vision . By assigning a unique label to each connected region, higher level image operations can identify, extract, and process different connected regions separately. Because of its primary importance, the problem has attracted research in developing parallel algorithms. Most of the research has been theoretical in nature, with notable exceptions. We present a new component labeling algorithm that is a parallelized hybrid of the sequential algorithms of R.M. Haralick and L.G. Shapiro (1979) and A. Rosenfeld, J. Pfaltz (1966). Experimental studies on the nCUBE/10 hypercube system at the University of South Carolina show that the algorithm has a relatively efficient balance of time complexity and storage utilization. %0 Conference Proceedings %A Chiang, A.M. %D 1981 %T A New CCD Parallel Processing Architecture %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 408-415 %0 Generic %A Choudhary, Alok N. %A narahari, Bhagirath %A Nicol, David M. %A Simha, Rahul %T Optimal Processor Assignment for Series-Parallel Pipelined Computations %0 Book %A Choudhary, A. N. %A Patel, J. H. %D 1990 %T Parallel Architectures and Parallel Algorithms for Integrated Vision Systems %I Kluwer Academic %0 Journal Article %A Choudhary, A. N. %A Patel, J. H. %A Ahuja, N. %D 1993 %T NETRA: A Hierarchical and Partitionable Architecture for Computer Vision %J IEEE Transactions on Parallel and Distributed Systems %V %P 1092-1104 %0 Journal Article %A Choudhary, A. N. %A Narahari, B. %A Nicol, D. M. %A Simha, R. %D 1994 %T Optimal processor assignment for a class of pipelined computations %J Ieee Transactions on Parallel and Distributed Systems %V 5 %N 4 %P 439-45 %K pipelined computations; multitasked parallel architectures ; processor assignment problem; data dependencies; series-parallel partial order ; computer vision ; parallel analysis ; data sets; task structure; series-parallel task system ; series analysis PARALLEL ARCHITECTURES; PIPELINE PROCESSING; RESOURCE ALLOCATION %X The availability of large-scale multitasked parallel architectures introduces the following processor assignment problem. We are given a long sequence of data sets, each of which is to undergo processing by a collection of tasks whose intertask data dependencies form a series- parallel partial order. Each individual task is potentially parallelizable, with a known experimentally determined execution signature. Recognizing that data sets can be pipelined through the task structure, the problem is to find a "good" assignment of processors to tasks. Two objectives interest us: minimal response time per data set, given a throughput requirement, and maximal throughput, given a response time requirement. Our approach is to decompose a series- parallel task system into its essential "serial" and " parallel " components; our problem admits the independent solution and recomposition of each such component. We provide algorithms for the series analysis, and use an algorithm due to Krishnamurti and Ma for the parallel analysis. For a p processor system and a series- parallel precedence graph with n constituent tasks, we give a O(np/sup 2/) algorithm that finds the optimal assignment (over a broad class of assignments) for the response time optimization problem; we find the assignment optimizing the constrained throughput in O(np/sup 2/ log p) time. These techniques are applied to a task system in computer vision . %0 Conference Proceedings %A Chow, E. %A Madan, H. %A Peterson, J. %A Grunwald, D. %A Reed, D. %D 1988 %T Hyperswitch Network for the Hypercube Computer %J Conference Proceedings of the 15th Annual International Symposium on Computer Architecture %P 90-99 %0 Conference Proceedings %A Chuang, H. Y. H. %A Ling Chen, (. ). %A Ching, Chung Li %D 1993 %T A scalable VLSI parallel pipelined architecture for discrete wavelet transform %J Machine Vision Applications, Architectures, and Systems Integration II %I SPIE %C Boston, MA %P 7-9 %K scalable VLSI parallel pipelined architecture ; 1D discrete wavelet transform; signal analysis; image analysis; high frequency components; time resolution; low frequency components; localized contributions; multiscale analysis; parallel pipelined array processor ; multiple levels; speedup IMAGE PROCESSING ; IMAGE PROCESSING EQUIPMENT; PARALLEL ARCHITECTURES; PIPELINE PROCESSING; RECONFIGURABLE ARCHITECTURES; VLSI; WAVELET TRANSFORMS %X The discrete wavelet transform (DWT) provides a new method for signal/image analysis where high frequency components are studied with finer time resolution and low frequency components with coarser time resolution. It decomposes a signal or an image into localized contributions for multiscale analysis. This paper presents a parallel pipelined array processor for 1D DWTs. Unlike other VLSI DWT processors, which processes signal data sequentially in a pipeline, this array processor can process all data in a signal segment in parallel and successive segments in the same pipeline which computes the multiple levels (octaves) of the DWT. The speedup is linearly proportional to the width of the array (or the size of a segment), and thus the architecture is scalable. %0 Journal Article %A Chung, Ming Chen %A Soo-Young Lee %D 1994 %T On parallelizing the EM algorithm for PET image reconstruction %J Ieee Transactions on Parallel and Distributed Systems %V 5 %N 8 %P 860-73 %X The expectation maximization (EM) algorithm is one of the most suitable iterative methods for positron emission tomography (PET) image reconstruction; however, it requires a long computation time and an enormous amount of memory space. To overcome these problems, we present two classes of highly efficient parallelization schemes: homogeneous and inhomogeneous partitionings. The essential difference between these two classes is that the inhomogeneous partitioning schemes may partially overlap the communication with computation by deliberate exploitation of the inherent data access pattern with a multiple-ring communication pattern. In theory, the inhomogeneous partitioning schemes may outperform the homogeneous partitioning schemes. However, the latter require a simpler communication pattern. In an attempt to estimate the achievable performance and to analyze the performance degradation factors without actual implementation, we have derived efficiency prediction formulas for closely estimating the performance for the proposed parallelization schemes. We propose new integration and broadcasting algorithms for hypercube, ring, and n-D mesh topologies, which are more efficient than the conventional algorithms when the link setup time is relatively negligible. The concept of the proposed task and data partitioning schemes, the integration and broadcasting algorithms, and the efficiency estimation methods can be applied to many other problems that are rich in data parallelism, but without balanced exclusive partitioning. %0 Journal Article %A Clark, J.H. %D 1980 %T A VLSI Geometry Processor for Graphics %J Computer %V 13 %N 7 %0 Journal Article %A Clark, J.H. %D 1982 %T The Geometry Engine: A VLSI Geometry System for Graphics %J Computer Graphics %V 16 %N 3 %P 127-133 %0 Conference Proceedings %A Clark, D. W. %D 1987 %T Pipelining and Performance in the VAX 8800 Processor %J Proceedings of Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II) %P 173-177 %0 Book %A Clark, A. %D 1991 %T Image Processing and Interchange (IPI), Part 1: Overview, Architecture, Profiles, Conformance; Working Draft %0 Book Section %A Clementi, E %A Chin, S. %A Corongiu, G. %A Detrich, J. H. %A Dupuis, M. %A Folsom, D. %A Lie, G. C. %A Logan, D. %A Sonnad, V. %D 1988 %T Supercomputing and Super Computers: for Science and Engineering in General and for Chemistry and Biosciences in Particular %B Biological and Artificial Intelligence Systems %I ESCOM Science Publishers B.V. %P 319-424 %0 Conference Proceedings %A Clermont, P. %A Merigot, A. %D 1987 %T Real Time Synchronization in a Multi-SIMD Massively Parallel Machine %J 1987 Workshop on Computer Architecture for Pattern Analysis and Machine Intelligence %C Seattle, WA %P 131-6 %0 Book Section %A Cloud, E. L. %D 1991 %T Geometric Arithmetic Parallel Processor: Architecture and Implementation %B Parallel Architectures and Algorithms for Image Understanding %I Academic Press %P 279-305 %0 Report %A Clune, E. %A Crisman, J. D. %A Klinker, G. J. %A Webb, J. A. %D 1987 %T Implementation and Performance of a Complex Vision System on a Systolic Array Machine %I Robotics Institute, Carnegie Mellon University %R CMU-RI-TR-87-16 %0 Conference Proceedings %A Clune, E. %A Crisman, J. D. %A Klinker, G. J. %A Webb, J. A. %D 1988 %T Implementation and Performance of a Complex Vision System on a Systolic Array Machine %J Future Generations Computer Systems %P 15-19 %0 Book %A Codd, E.F. %D 1968 %T Cellular Automata %I Academic Press %C New York %0 Journal Article %A Cohen, D. %D 1976 %T Simplified Control of FFT Hardware %J IEEE Transactions on Acoustics, Speech, and Signal Processing %V AU-24 %P 577-579 %0 Report %A Cohen, D. %D 1978 %T Mathematical Approach to Computational Networks %0 Conference Proceedings %A Cohen, D. %A Tyree, V.C. %D 1979 %T VLSI System for SAR Processing %J Proceedings of Conference on Very Large Scale Integration: Architecture, Design, Fabrication %0 Conference Proceedings %A Cohen, D. %A Lewicki, G. %D 1981 %T MOSIS -- The ARPA Silicon Broker %J Proceedings of the Second Caltech Conference on VLSI %0 Conference Proceedings %A Cohn, R. %A Kung, H. T. %A Menzilcioglu, O. %A Song, S. %D 1988 %T A Highly Reconfigurable Array of Powerful Processors %J SPIE Symposium, Vol. 975, Advanced Algorithms and Architectures for Signal Processing III %0 Conference Proceedings %A Cohn, R. %A Kung, H. T. %A Menzilcioglu, O. %A Song, S. W. %D 1988 %T A Highly Reconfigurable Array of Powerful Processors %J Proceedings of SPIE Symposium, Vol. 975, Advanced Algorithms and Architectures for Signal Processing III %P 336-343 %0 Conference Proceedings %A Cohn, R. %A Gross, T. %A Lam, M. %A Tseng, P. S. %D 1989 %T Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor %J Proceedings of Third International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS III) %0 Thesis %A Coletti, Neil Boyd %D 1983 %T Image processing on MPP-like arrays %I University of Illinois at Urbana-Champaign %9 Ph.D. %X Covers all the stages in the NASA thematic mapper algorithm -- determining warp, warp, etc. %0 Journal Article %A Collette, T. %A Essafi, H. %A Juvin, D. %A Kaiser, J. %D 1994 %T SYMPATIX: a SIMD computer performing the low and intermediate levels of image processing %J Future Generation Computer Systems %V 10 %N 1 %P 3-13 %K SYMPATIX; SIMD computer; image processing ; interconnection network; open intelligent network; SYMPTI2; hardware description language; VHDL IMAGE PROCESSING ; PARALLEL PROCESSING; PERFORMANCE EVALUATION %X This SIMD processor based system performs with a good efficiency the low level image processing operations, but this efficiency is drastically cut when handling an intermediate level class of algorithms. This study emphasises the drawbacks encountered to perform such operations. The main one is the interconnection between processors. So, a new interconnection network, called the open intelligent network, is proposed and added to SYMPTI2 to form SYMPATIX. This network allows irregular transfers of data between the different processing elements of the new system. Furthermore, this network allows the efficient interconnection of specific modules. The architecture is evaluated on representative algorithms of image processing . A behavioural model of SYMPATIX is described using a hardware description language, the VHDL. The SIMD computer efficiency has been considerably upgraded for the low and intermediate levels of image processing . Furthermore its application area is extended. The last part of the paper describes the performance obtained with simulations. %0 Book Section %A Condon, J.H. %A Thompson, K. %D 1982 %T Belle Chess Hardware %B Advances in Computer Chess 3 %E Clarke, M.R.B. %I Pergamon Press %P 45-54 %S Pergamon Chess Series %0 Journal Article %A Conway, L. %A A., Bell %A Newell, M.E. %D 1980 %T MPC79: The Large-Scale Demonstration of a New Way to Create Systems in Silicon %J LAMBDA %V 1 %N 2 %P 10-19 %0 Journal Article %A Cook, S.A. %A Sethi, R. %D 1976 %T Storage Requirements for Deterministic Polynomial Time Recognizable Languages %J J. Comp. and Sys. Sci. %V 13 %P 25-37 %0 Journal Article %A Copty, Nawal %A Ranka, Sanjay %A Fox, Geoffrey %D 1994 %T A Data Parallel Algorithm for Solving the Region Growing Problem on the Connection Machine %J Journal of parallel and distributed computing %V 21 %N 1 %P 160- %0 Conference Proceedings %A Corrie, Brian %A Mackerras, Paul %D 1993 %T Parallel Volume Rendering and Data Coherence %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, CA %P 23-26 %0 Conference Proceedings %A Corry, A. %A Patel, K. %D 1983 %T A CMOS/SOS VLSI Correlator %J Proceedings of 1983 International Symposium on VLSI Technology, Systems and Applications %P 134-137 %0 Conference Proceedings %A Cova, G. %A Griffini, A. %A Lombardi, L. %D 1989 %T Object Recognition Strategy in a Multi-Resolution System %J 5th International Conference on Image Analysis and Processing. Progress in Image Analysis and Processing %I World Scientific %C Positano, Italiy %P 729-33 %0 Generic %A Cox, G. %D 1991 %T Directions for iWarp Technology %C iWarp Forum, Hyatt Regency, Crystal City, Maryland %8 September 11, 1991 %9 Lecture %0 Conference Proceedings %A Cox, Michael %A Hanrahan, Pat %D 1993 %T Pixel Merging for Object-Parallel Rendering: A Distributed Network Snooping Algorithm %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, CA %P 49-56 %0 Journal Article %A Crisman, J. D. %A Webb, J. A. %D 1991 %T The Warp Machine on Navlab %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 13 %N 5 %P 451-65 %0 Book Section %A Crisman, J. D. %A Webb, J. A. %D 1991 %T The Warp Machine on Navlab %B Vision and Navigation: The Carnegie Mellon Navlab %E Thorpe, C. %I Kluwer %0 Conference Proceedings %A Crockett, Thomas W. %A Orloff, Tobias %D 1993 %T A MIMD Rendering Algorithm for Distributed Memory Architectures %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, CA %P 35-42 %0 Journal Article %A Crookes, D. %A Morrow, P. J. %A Scott, N. S. %A Kilpatrick, P. L. %D 1987 %T Notes on Implementing a Language for transputer Networks %J Microprocessing and Microprogramming %V 21 %P 558-66 %0 Report %A Crooks, P. %A Herrott, R. H. %D 1993 %T Language Constructs for Data Partitioning and Distribution %I Department of Computer Science, Queen's University of Belfast %0 Conference Proceedings %A Crowther, W. %A Goodham, J. %A Starr, E. %A Thomas, R. %A Milliken, W. %A Blackaden, T. %D 1985 %T Performance Measurements on a 128-Node Butterfly Parallel Processor %J International Conference on Parallel Processing %P 531-40 %0 Conference Proceedings %A Cuhadar, A. %A Downton, A. C. %D 1994 %T Scalable Parallel Processing Design for Real Time Handwritten OCR %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 339-341 %0 Journal Article %A Curd, J.R. %A Kirkham, C.C. %A Watson, I. %D 1985 %T The Manchester Prototype Dataflow Computer %J Communications of the ACM %V 28 %N 1 %P 34-52 %0 Journal Article %A Cypher, R. %A Sanz, J. %A Snyder, L. %D 1990 %T Algorithms for Image Component Labelling on SIMD Mesh-Connected Computer %J IEEE Transactions on Computers %V 39 %N 2 %P 276-81 %0 Conference Proceedings %A Cytron, R. %D 1986 %T Doacross: Beyond Vectorization for Multiprocessors %J 1986 International Conference on Parallel Processing %C St. Charles, Illinois %P 836-844 %0 Conference Proceedings %A apin, Tolga K. %A Aykanat, Cevdet %A zg, Blent %D 1993 %T Progressive Refinement Radiosity on Ring-Connected Multicomputers %J Parallel Rendering Symposium %C San Jose, CA %P 71-76 %0 Conference Proceedings %A Dacic, S. %A Frecaut, J. M. %A Zavidovique, B. %D 1990 %T Software Environment for Complex Machine Programming %J COMPEURO '90:1990 IEEE International Conference on Computer Systems and Software Engineering %C Tel-Aviv, Israel %P 312-9 %0 Journal Article %A Dally, W. J. %A Seitz, C. L. %D 1986 %T The Torus Routing Chip %J Distributed Computing %V 1 %N 4 %P 187-196 %0 Book %A Dally %A J., William %D 1987 %T A VLSI Architecture for Concurrent Data Structures %I Kluwer Academic Publishers %0 Journal Article %A Dally, W.J. %A Seitz, C.L. %D 1987 %T Deadlock-Free Message Routing in Multiprocessor Interconnection Networks %J IEEE Transactions on Computers %V C-36 %N 5 %P 547-553 %0 Conference Proceedings %A Damianakis, Adam C. %A Orphanoudakis, Stelios C. %D 1991 %T The Influence of Image Content and Architectural Features on the Performance of Parallel Implementations %J Computer Architectures for Machine Perception %E Zavidovique, Bertrand %E Wendel, Pierre-Louis %I D.G.A./E.T.C.A., C.N.R.S./I.E.F. and M.E.N./D.R.E.D. %C Paris, France %P 573-580 %0 Conference Proceedings %A Danielsson, P.-E. %A Lindskog, B. %A Segerstrom, J. %D 1988 %T PICAP3-A Coarse-Grain Linear SIMD-Array %J IAPR Workshop on Computer Vision: Special Hardware and Industrial Applications %C Tokyo, Japan %0 Journal Article %A Davidson, S. %A Landskov, D. %A Shriver, B.D. %A Mallett, P.W. %D 1981 %T Some Experiments in Local Microcode Compaction for Horizontal Machines %J IEEE Trans. on Computers %V C-30 %N 7 %P 460 - 477 %0 Conference Proceedings %A Deguchi, K. %A Tago, K. %A Morishita, I. %D 1990 %T Integrated Parallel Image Processings on a Pipelined MIMD Multi-Processor System PSM %J 10th International Conference on Pattern Recognition %C Atlantic City, NJ %P 442-4 %0 Journal Article %A Delingette, H. %A Hebert, M. %A Ikeuchi, K. %D 1992 %T Shape represenation and image segmentation using deformable surfaces %J Image and Vision Computing %V 10 %N 3 %P 132-144 %0 Conference Proceedings %A Delosme, J.-M. %A Ipsen, I. C. F %D 1986 %T Design Methodology for Systolic Arrays %J Proceedings of SPIE Symposium, Vol. 696, Advanced Algorithms and Architectures for Signal Processing %C San Diego, California %P 245-259 %0 Conference Proceedings %A Denneau, M. %D 1982 %T The Yorktown Simulation Engine %J Proceedings of the 19th Design Automation Conference %P 55-59 %0 Report %A Deutch, J. %A Maulik, P. C. %A Mosur, R. %A Printz, H. %A Ribas, H. %A Senko, J. %A Tseng, P. S. %A Webb, J. A. %A Wu, I-C. %D 1987 %T Performance of Warp on the DARPA Architecture Benchmarks %I Computer Science Department, Carnegie-Mellon University %R CMU-CS-87-148 %0 Conference Proceedings %A Deutch, J. %A Maulik, P. C. %A Mosur, R. %A Printz, H. %A Ribas, H. %A Senko, J. %A Tseng, P. S. %A Webb, J. A. %A Wu, I-C. %D 1988 %T Performance of Warp on the DARPA Architecture Benchmarks %J International Conference on Parallel Processing for Computer Vision and Display %C Leeds, England %0 Generic %A Dew, P. %A Chang, C.H. %D 1984 %T Passive Navigation by a Robot on the CMU Warp Machine %0 Conference Proceedings %A Dew, P. M. %A Wang, H. %D 1988 %T Data Parallelism and the Processor Farm Model for Image Processing and Synthesis on a transputer Array %J SPIE Symposium 977, Real Time Signal Processing XI %P 212-20 %0 Conference Proceedings %A Dew, P. M. %A Wang, H. %A Webb, J. A. %D 1989 %T APPLY: Machine independent image processing language and its implementation on a meiko computing surface %J Fifth Alvey Vision Conference %C Reading, England %0 Journal Article %A Dhond, U R %A Aggarwal, J K %D 1989 %T Structure from stereo - A review %J IEEE Transactions on Systems, Man, and Cybernetics %V 19 %N 6 %P 1489-1510 %0 Journal Article %A Dhond, U. R. %A Aggarwal, J. K. %D 1989 %T Structure from stereo - A review %J IEEE Transactions on Systems, Man, and Cybernetics %V 19 %N 6 %P 1489-1510 %0 Conference Proceedings %A Di Sciasco, E. %A Guzzardi, R. %A Marino, D. %D 1992 %T Proposal of a real time reconstruction processor for 3-D positron emission tomography %J Conference Record of the IEEE Nuclear Science Symposium and Medical Imaging Conference %I IEEE %C Orlando, FL %P 921-3 %K 3D positron emission tomography; single-instruction multiple-data parallel line processor ; nuclear medicine; medical diagnostic imaging ; real time reconstruction processor; bit-serial approach; application-specific integrated circuit; reconstruction processing time; address-encoding time; SILOS II simulator; 256 ns COMPUTERISED TOMOGRAPHY; IMAGE RECONSTRUCTION; MEDICAL IMAGE PROCESSING ; RADIOISOTOPE SCANNING AND IMAGING ; REAL-TIME SYSTEMS %X A specialized real-time reconstruction processor for three-dimensional positron emission tomography is proposed. It is based on an expandible SIMD (single-instruction multiple-data) parallel line processor. It is completely parallel and pipelined, and it is based on a bit-serial approach. The architecture, extremely suitable for ASIC (application-specific integrated circuit) implementation, has been designed to be compatible with existing tomograph prototypes, but it is easily scalable towards foreseen new solutions. The reconstruction processing time of the single coincidence line is of the order of the address-encoding time (at present 256 ns). The silicon design, in the SOLO 2030+41 environment with ES2 standard cells, is in progress, and it has been validated by simulations performed using the SILOS II simulator. %0 Conference Proceedings %A Diamantaras, K. %A Chihoub, A. %A Zawadski, A. %D 1993 %T Scalable architectures for image processing %J Machine Vision Applications, Architectures, and Systems Integration II %I SPIE %C Boston, MA %P 7-9 %K scalable architectures; image processing ; real time processing; parallel architectures ; low-level vision; 1-D array; wrap-around; 2-D array; ring; torus; hypercube; convolution; mathematical morphology; Fourier transform; topologies; histogram; image translation; rotation; zooming; edge-enhancement operators; SES/workbench simulation package; interconnection topology DIGITAL SIMULATION; FILTERING AND PREDICTION THEORY; FOURIER TRANSFORMS; IMAGE PROCESSING ; MATHEMATICAL MORPHOLOGY; PARALLEL ARCHITECTURES; SOFTWARE PACKAGES; TOPOLOGY %X In recent years scalable parallel architectures have emerged as a cost-efficient solution to addressing the problem of ever-increasing computational demands. Such architectures provide the flexibility of increasing the performance while preserving the substantial investment in the software and hardware of a given machine. The authors propose to present the results of their investigation of the scalability of a selected number of low-level vision operations on three topologies: (a) 1-D array with wrap-around (ring) (b) 2-D array with wrap-around (torus), and (c) the hypercube. In particular the authors present the scalability results of the following algorithms: convolution, mathematical morphology, Fourier transform, DCT, histogram, image translation, rotation, zooming, edge-enhancement operators (e.g. Canny, Sobel, Kirsch, Nevatia-Babu), median filtering, point-wise operations (e.g. thresholding, dithering) on the three topologies. In addition, the authors present preliminary results of the design of a scalable parallel processor that performs optimally (performance increases linearly or close to linear in terms of the number of processing elements in the machine) on these operators. The authors' study consists of three phases: mapping the algorithms on the three topologies, simulating the execution of these algorithms, and design of the array. The authors mapping follows the standard methodology proposed for the design of systolic arrays, since their application domain is very specific and the selected algorithms very regular. After the mapping is done the authors simulate the algorithms using the SES/workbench simulation package which allows them to collect statistics on the execution time and efficiency of their mappings and evaluate the performance of the three topologies in their application domain using different array and problem sizes. For each algorithm and topology the range of scalability is determined as a function of image size. In the design phase the authors propose an SIMD array with 2-D torus interconnection topology as a cost-efficient solution to the scalable implementation of the selected algorithms. Considerations entering the design phase are performance as determined by simulations, cost of implementation, and ease of scaling the machine size. %0 Journal Article %A Dijkstra, E. %D 1959 %T A note on two problems in connexion with graphs %J Numerische Mathematik %V 1 %P 269-71 %0 Report %A Dinda, Peter %A Gross, Thomas %A O'Hallaron, David %A Segall, Edward %A Stichnoth, James %A Subhlok, Jaspal %A Webb, Jon %A Yang, Bwolen %D 1994 %T The CMU Task Parallel Program Suite %I Computer Science Department, Carnegie Mellon University %8 March %9 Technical Report %R CMU-CS-94-131 %0 Conference Proceedings %A Director, S.W. %A Parker, A.C. %A Siewiorek, D.P. %A Thomas, D.E. %D 1982 %T A Design Methodology and Computer Aids for Digital VLSI Systems %J CMU Computer Science Research Review 1980-81 %I Carnegie-Mellon University, Computer Science Department %P 39-73 %0 Conference Proceedings %A Doctor, D. P. %A Sudborough, H. %D 1993 %T Parallel algorithm for quadtree medial axis transform %J Proceedings Icci '93. Fifth International Conference on Computing and Information %E Abou-Rabia, O. %E Chang, C.K. %E Koczkodaj, W.W. %C Sudbury, Ont., Canada %P 266-71 %X The quadtree medial axis transform (QMAT) representation of a binary image is a very useful scheme for computer graphics and image processing applications. We present an efficient algorithm for QMAT on the shared memory EREW-PRAM model. For an image of size n*n, using n*n processors, we compute QMAT in O(log n) time. Since image sensors provide image data as a two-dimensional array, a mesh connected computer (MCC) is a popular architecture for image processing applications. Previously known parallel algorithms for QMAT require O(log/sup 2/ n) and O(log n) time on a pyramid model, and a simulation of these two algorithms takes O(n log n) time on an MCC. However, our algorithm can be executed on an MCC in O(n) time, which is optimal for that model due to the size of its diameter. %0 Report %A Dohi, Y. %A Fisher, A. %A Kung, H. T. %A Monier, L. %D 1982 %T PSC Architecture %0 Conference Proceedings %A Dohi, Y. %A Fisher, A.L. %A Kung, H.T. %A Monier, L.M. %D 1982 %T The Programmable Systolic Chip: Project Overview %J Proceedings of Workshop on Algorithmically-specialized Computer Organizations %0 Conference Proceedings %A Dohi, Y. %D 1983 %T Sorter using the PSC Linear Array %J Proceedings of 1983 International Symposium on VLSI Technology, Systems and Applications %P 255-259 %0 Journal Article %A Dohi, H. %A Ishizuka, M. %D 1993 %T Realtime synthesis of moving anthropomorphous agent's image employing small-scale parallel processors %J Journal of the Institute of Image Electronics Engineers of Japan %V 22 %N 3 %P 240-6 %K anthropomorphous agent; visual software agent; 3-D human face image; texture mapped images; transputer network; realtime synthesis; tracking; speech synthesizer GRAPHICAL USER INTERFACES; IMAGE TEXTURE; REAL-TIME SYSTEMS; STEREO IMAGE PROCESSING ; TRANSPUTERS; VISUAL PROGRAMMING %X An anthropomorphous agent which has a realistic human-like face, communication ability and intelligence is expected to play an important role toward advanced interfaces between computer and human. In the visual software agent (VSA) the user communicates with the computer through a realistic 3-D human face image which moves in realtime on a monitor. To perform realtime generation of texture mapped images a prototype of the VSA is implemented in a transputer network and executed in parallel . This paper describes realtime synthesis employing four parallel microprocessors. The VSA can turn his/her face tracking a cursor position on a window, wink his/her eyes, and talk to a user synchronized with a speech synthesizer. %0 Book %A Dongarra, J.J. %A Bunch, J.R. %A Moler, C.B. %A Stewart, G.W. %D 1979 %T LINPACK Users' Guide %I Society for Industrial and Applied Mathematics %C Philadelphia %0 Conference Proceedings %A Downton, A. C. %A Tregidgo, R. W. S. %A Cuhadar, A. %D 1994 %T Top-down structured parallelisation of embedded image and vision applications %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 5/1-6 %K processor farming; image processing ; structured top-down design; parallel embedded systems ; embedded signal processing systems; sequential software structure; generalized parallel architecture ; data parallelism; algorithmic parallelism; temporal multiplexing; input data sets COMPUTER VISION ; IMAGE PROCESSING ; PARALLEL ARCHITECTURES %X The authors propose an architecture-independent structured top-down design methodology for parallel embedded systems. This methodology proceeds from the observation that embedded signal processing systems may be characterized as consisting of series of independent processing stages. The methodology proposes mapping this sequential software structure to a generalized parallel architecture for embedded systems based upon a pipeline of stages with well-defined data communication patterns between them. Each stage of the pipeline then exploits parallelism in the most appropriate way, for example data parallelism applied at various different levels, algorithmic parallelism, or temporal multiplexing of complete input data sets. Processor farming, which is easily adapted to all of these models of parallelism, has been proposed as a general implementation method, because it allows indefinite incremental scaling of any stage and results in a single tractable analytical model. %0 Conference Proceedings %A Drucker, Steven M. %A Schrder, Peter %D 1992 %T Fast Radiosity Using a Data Parallel Architecture %J Third Eurographics Workshop on Rendering %C Barcelona, Spain %P 247-258 %0 Journal Article %A Duda, R. O. %A Hart, P. E. %D 1972 %T Use of the Hough transform to detect lines and curves in pictures %J Communications of the ACM %V 15 %N 1 %0 Book %A Duda, R. O. %A Hart, P. E. %D 1973 %T Pattern Classification and Scene Analysis %I Wiley %0 Conference Proceedings %A Duler, A. W. G. %A Storer, R. H. %A Thomson, A. R. %A Pout, M. R. %A Dagless, E. L. %D 1990 %T A Heterogeneous Vision Architecture %J Computer Vision - ECCV 90. First European Conference on Computer Vision Proceedings %C Antibes, France %P 576-8 %0 Journal Article %A Duller, A. W. G. %A Storer, R. H. %A Thomson, A. R. %A Dagless, E. L. %D 1989 %T An Associative Processor Array for Image Processing %J Image and Vision Computing %V 7 %N 2 %P 151-8 %0 Conference Proceedings %A Dykes, S. G. %A Xiaodong, Zhang %A Yan, Zhou %A Yang, Haixu %D 1994 %T Communication and computation patterns of large scale image convolutions on parallel architectures %J Proceedings Eighth International Parallel Processing Symposium %E Siegal, H.J. %I IEEE Comput. Soc. Press %C Cancun, Mexico %P 926-31 %K computation patterns; large scale image convolutions; parallel architectures ; imag segmentation; image processing operations ; convolution calculations; memory access demand; texture segmentation application; convolution; CM-5; iPSC/860; PVM distributed memory multicomputers; parallel algorithms ; execution time; large kernel convolutions; fast memory store; processor power; communication overhead DISTRIBUTED MEMORY SYSTEMS; IMAGE SEGMENTATION; IMAGE TEXTURE; PARALLEL ALGORITHMS; PARALLEL MACHINES %X Segmentation and other image processing operations rely on convolution calculations with heavy computational and memory access demands. The article presents an analysis of a texture segmentation application containing a 96*96 convolution. Sequential execution required several hours an single processor systems with over 99% of the time spent performing the large convolution. 70% to 75% of execution time is attributable to cache misses within the convolution. We implemented the same application on CM-5, iPSC/860 and PVM distributed memory multicomputers, tailoring the parallel algorithms to each machine's architecture. Parallelization significantly reduced execution time, taking 49 seconds on a 512 node CM-5 and 6.5 minutes on a 32 node iPSC/860. The results indicate for large kernel convolutions the size and bandwidth of the fast memory store is more important than processor power or communication overhead. %0 Journal Article %A Eager, D. L. %A Zahorjan, J. %A Lazowska, E. D. %D 1989 %T Speedup versus efficiency in parallel systems %J IEEE Transactions on Computers %V 38 %N 3 %P 408-23 %0 Generic %A Ebeling, C. %T The Design of Implementation of a Chess Move Generator %0 Report %A Ebeling, C. %A Frank, E.H. %D 1981 %T Saffron: A Programmable Simulator for Digital Systems %0 Report %A Ebeling, C. %D 1981 %T Generating Hierarchical Wirelists with SIL and Analyze %0 Report %A Ebeling, C. %A Frank, E.H. %D 1981 %T Primitives for Simulation %0 Report %A Ebeling, C. %A Frank, E.F. %D 1982 %T SAFFRON User's Manual %0 Conference Proceedings %A Ebeling, C. %A Zajicek, O. %D 1983 %T Validating VLSI Circuit Layout by Wirelist Comparison %J Proceedings of 1983 IEEE International Conference on Computer-Aided Design %P 172-173 %0 Thesis %A Ebeling, C. %D 1986 %T All the Right Moves: A VLSI Architecture for Chess %0 Book %A Eggleston, H.G. %D 1957 %T Problems in Enclidean Space: Application of Convexity %I Pergamon Press %C New York %0 Conference Proceedings %A El-Ghazawi, T. A. %A Flachs, G. M. %D 1991 %T Design of pipelined processors architectures for optimal implementation of difference equations %J Proceedings of the Fourth Ismm/iasted International Conference Parallel and Distributed Computing and Systems %E Ammar, R. A. %C Washington, DC %P 51-2 %K pipelined processors architectures; optimal implementation; difference equations; optimal multiprocessor realizations; maximum concurrency; real-time applications DIFFERENCE EQUATIONS; PARALLEL ARCHITECTURES; PERFORMANCE EVALUATION; PIPELINE PROCESSING %X Difference equations have a wide range of applications including signal processing, image processing , and digital control systems. The real-time nature of such applications require high-speed implementations. Therefore, optimal multiprocessor realizations of difference equations have been targeted by many research efforts. The high-performance provided by these methods was achieved by finding the optimal number of iterations that can be run in an overlapped fashion. Each iteration is, then, scheduled to run on a separate processor. A modified design scheme, which starts with exploiting the maximum concurrency within a single iteration, is presented. It is shown that this modified design strategy results in cost effective difference equations implementations with faster responses, which is essential for real-time applications. %0 Book %A Electrotechnical Laboratory %D 1983 %T SPIDER (Subroutine Package for Image Data Enhancement and Recognition) %I Joint System Development Corp. %C Tokyo, Japan %0 Conference Proceedings %A Ellsworth, David %D 1993 %T A Multicomputer Polygon Rendering Algorithm for Interactive Applications %J Parallel Rendering Symposium %I IEEE Computer Society %C San Jose, CA %P 43-48 %0 Conference Proceedings %A Elmirghani, J. M. H. %D 1994 %T Optical computing techniques for parallel image processing %J Iee Colloquium on 'Parallel Architectures for Image Processing' %I IEE %C London, UK %P 6/1-4 %K optical signal processing; optical computing; parallel image processing ; real time image processing ; image feature estimation; background noise IMAGE PROCESSING ; OPTICAL INFORMATION PROCESSING; PARALLEL PROCESSING %X Optical signal processing (OSP) offers numerous advantages in real time image processing applications. OSP inherently offers parallelism in the processing of data at speeds much higher than those achievable using electrical digital signal processing (DSP). A review of the available OSP techniques for image processing is given. Particular attention is given to image feature estimation in background noise while the necessary OSP implementations are demonstrated. %0 Journal Article %A Elphinstone, A. C. %A Heron, A. P. %A Hobson, G. S. %A Houghton, A. D. %A Powell, A. R. %A Seed, N. L. %A Tozer, R. C. %D 1988 %T The RAPAC Image Processing System %J Microcomputer Applications %V 7 %N 1 %P 17-21 %0 Journal Article %A Erenyi, I. %A Fazekas, Z. %D 1994 %T Image processing applications and their parallel aspects %J Computing & Control Engineering Journal %V 5 %N 2 %P 71-4 %K image processing applications ; parallel aspects ; VEGA project; HW/SW platforms; intelligent microscopy; industrial quality control; analysis/simulation; parallel architectures IMAGE PROCESSING ; PARALLEL ALGORITHMS; PARALLEL ARCHITECTURES; RESEARCH INITIATIVES; VIRTUAL MACHINES %X Image processing activities at KFKI Research Institute for Measurement and Computing Techniques are summarised. First, KFKI's contribution to the VEGA project is described. Then two HW/SW platforms are mentioned (together with applications in intelligent microscopy, industrial quality control). Finally, the analysis/simulation of promising parallel architectures-to achieve considerable speed-up for image processing primitives-is outlined. This inevitably involves the modification/parallelisation of algorithms to exploit parallel capabilities of the architectures. %0 Journal Article %A Erenyi, I. %A Vassanyi, I. %D 1994 %T Mapping strategies for signal and image processing algorithm parallelization %J Journal on Communications %V 45 %P 50-2 %X The paper discusses some aspects of the fine grain size formal mapping methods aided with some heuristics. The use of a 'slightly configurable' processing elements array is proposed that seems to suffice for a wide range of image processing problems and simultaneously offers a feasible VLSI realization. Further research is needed on the desirable hardware characteristics of such arrays. Also the available VLSI components' impact on the mapping process should be thoroughly investigated. %0 Conference Proceedings %A Ernoult, C. %D 1988 %T Performance of Backpropagation on a Parallel transputer-based Machine %J Neuro-Nimes '88: International Workshop on Neural Networks and their Applications %C Nimes, France %P 311-24 %0 Book Section %A Eshaghian, M. M. %A Lee, S. H. %A Shaaban, M. E. %D 1991 %T Parallel Image Computing with Optical Technology %B Parallel Architectures and Algorithms for Image Understanding %I Academic Press %P 29-58 %0 Journal Article %A Evanczuk, S. %D 1982 %T Researchers Pump Up Systolic Approach %J Electronics %V %P 46-47 %0 Conference Proceedings %A Evans, R.A. %A Wood, D. %A Wood, K. %A McCanny, J.V. %A McWhirter, J.G. %A McCabe, A.P.H. %D 1983 %T A CMOS Implementation of a Systolic Multi-Bit Convolver Chip %J VLSI '83 %E Anceau, F. and Aas, E.J. %I North-Holland %P 227-235 %0 Book Section %A Faiss, Rudolf O. %D 1985 %T Landsat-4 Thematic Mapper Data Processing with the Massively Parallel Processor %B The Massively Parallel Processor %E Potter, Jerry L. %I MIT Press %C Cambridge, MA %P 62-84 %0 Conference Proceedings %A Faugeras, O. D. %A Toscani, G. %D 1986 %T The calibration problem for stereo %J Proceedings of the IEEE International Conference on Computer Vision and Pattern Recognition %P 15-20 %0 Book %A Faugeras, O. D. %D 1993 %T Three-Dimensional Computer Vision: A Geometric Viewpoint %I MIT Press %0 Book %A Faux, I. D. %A Pratt, M. J. %D 1979 %T Computational Geometry for Design and Manufacture %I Ellis Horwood %0 Conference Proceedings %A Feda, Martin %A Purgathofer, Werner %D 1991 %T Progressive Refinement Radiosity on a Transputer Network %J Second Eurographics Workshop on Rendering %C Barcelona, Spain %0 Conference Proceedings %A Fejes, S. %A Vajda, F. %D 1994 %T Simplified Adaptive Approach to Efficient Morphological Image Analysis %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 257-261 %0 Journal Article %A Feo, J. T. %D 1988 %T An Analysis of the Computational and Parallel Complexity of the Livermore Loops %J Parallel Computing %V 7 %N 2 %P 163-186 %0 Conference Proceedings %A Fernandez, C. %A Campoy, P. %A Platero, C. %A Sebastian, J. M. %A Aracil, R. %D 1993 %T On-line surface inspection for continuous cast aluminum strip %J Computer Vision for Industry. %I SPIE %C Munich, Germany %P 24-25 %S Proceedings of the Spie The International Society for Optical Engineering %K surface inspection; continuous cast aluminum strip; visual information; expert system; surface image analysis; parallel architecture ; image processing ; lighting system; image acquisition; texture algorithms; defect detection; formal language theory AUTOMATIC OPTICAL INSPECTION; EXPERT SYSTEMS; IMAGE PROCESSING ; IMAGE TEXTURE; PARALLEL ARCHITECTURES %X A general architecture for detecting and analyzing surface defects in aluminum strip is described. Information concerning visual information from the aluminum surface, surface temperature and strip dimensions-profile thickness-is processed jointly by means of an expert system in order to determine the quality level of each aluminum coil produced; control actions over the casting process, derived from this information, are also suggested by an expert system. The paper shows work related to surface image analysis. The data volume to be processed, up to 20 Mbytes/s, has forced up the development of a high parallel architecture for high-speed image processing . An especially suitable lighting system has been developed for enhancing matricial image acquisition from metallic surfaces that includes reflect avoidance as well as uniform incident angle of light along the scanned portion of surface -about 120000 square mm-. Similarity-based algorithms as well as texture algorithms have been developed and hardware-implemented for defect detection. On-line defect classification is attempted by means of formal language theory. %0 Journal Article %A Ferreira, A. %A Ubeda, S. %D 1994 %T Ultra-fast parallel contour tracking, with applications to thinning %J Pattern Recognition %V 27 %N 7 %P 867-78 %K ultra-fast parallel contour tracking ; thinning; binary pictures; exclusive read exclusive write parallel random access machine ; EREW PRAM; work-optimal parallel thinning algorithm ; skeleton contour IMAGE PROCESSING %X This paper proposes a parallel algorithm for contour tracking of binary pictures. Given an object contour composed by O(N) pixels, our algorithm computes in constant time the next layer of the contour of that object, using the weakest parallel model, i.e. an exclusive read exclusive write (EREW) parallel random access machine (PRAM). As an application of the technique we show a work-optimal parallel thinning algorithm for binary pictures, based on Pavlidis' characterization of a skeleton (1980). Our algorithm improves on previous solutions by producing a list of coordinates corresponding to the skeleton contour in O(N) time with O(N) processors in an EREW PRAM, where N is the width of the picture. %0 Conference Proceedings %A Feynman, C. R. %A Voorhees, H. L. %A Tucker, L. W. %D 1988 %T A Massively Parallel Approach to Object Recognition %J Intelligent Robots and Computer Vision %I SPIE %C Cambridge, MA %P 324-9 %0 Report %A Fischer, M. J. %A Paterson, M. S. %D 1974 %T String Matching and Other Products %0 Journal Article %A Fisher, J.A. %D 1981 %T Trace Scheduling: A Technique for Global Microcode Compaction %J IEEE Trans. on Computers %V C-30 %N 7 %P 478-490 %0 Journal Article %A Fisher, A.L. %D 1982 %T Systolic Algorithms for Running Order Statistics in Signal and Image Processing %J Journal of Digital Systems %V VI %N 2/3 %P 251-264 %0 Conference Proceedings %A Fisher, A.L. %A Kung, H.T. %D 1982 %T Special-Purpose VLSI Architectures: General Discussions and a Case Study %J VLSI and Modern Signal Processing %I Prentice-Hall %0 Conference Proceedings %A Fisher, A.L. %A Kung, H.T. %A Monier, L.M. %A Walker, H. %A Dohi, Y. %D 1983 %T Design of the PSC: A Programmable Systolic Chip %J Proceedings of the Third Caltech Conference on Very Large Scale Integration %E Bryant, R. %I Computer Science Press, Inc. %P 287-302 %0 Journal Article %A Fisher, A.L. %A Kung, H.T. %A Monier, L.M. %A Dohi, Y. %D 1984 %T The Architecture of a Programmable Systolic Chip %J Journal of VLSI and Computer Systems %V 1 %N 2 %P 153-169 %0 Conference Proceedings %A Fisher, A.L. %A Kung, H.T. %A Sarocky, K. %D 1984 %T Experience with the CMU Programmable Systolic Chip %J Proceedings of SPIE Symposium, Vol. 495, Real-Time Signal Processing VII %0 Journal Article %A Fisher, A.L. %A Kung, H.T. %D 1985 %T Synchronizing Large VLSI Processor Arrays %J IEEE Transactions on Computers %V C-34 %N 8 %P 734-740 %0 Conference Proceedings %A Fisher, A. J. and Highnam, P. T. %D 1987 %T Computing the Hough transform on a scan-line array processor %J Computer Architecures for Pattern Analysis and Machine Intelligence %C Seattle, Washington %0 Conference Proceedings %A Fisher, A. %A Highnam, P. T. %D 1988 %T Communication and Code Optimization in SIMD Programs %J International Conference on Parallel Processing %C University Park, PA %0 Journal Article %A Fisher, A. L. and Highnam, P. T. %D 1989 %T Computing the Hough Transform on a Scan Line Array Processor %J IEEE Transactions on Pattern Analysis and Machine Intelligence %V 11 %N 3 %P 262-65 %0 Conference Proceedings %A Fisher, A. %A Highnam, P. T. %A Leon, J. %D 1990 %T Design and Performance of a SIMD Optimizing Compiler %J Third Symposium on the Frontiers of Massively Parallel Computing %0 Conference Proceedings %A Fitzpatrick, D.T. %A Foderaro, J.K. %A Katevenis, M.G.H. %A Landman, H.A. %A Patterson, D.A. %A Peek, J.B. %A Peshkess, Z. %A Sequin, C.H. %A Sherburne, R.W. %A Van Dyke, K.S. %D 1981 %T VLSI Implementations of a Reduced Instruction Set Computer %J VLSI Systems and Computations %E Kung, H.T., Sproull, R.F., and Steele, G.L., Jr. %I Computer Science Press, Inc. %P 326-336 %0 Journal Article %A Flanders, P. M. %A Parkinson, D. %D 1987 %T Data mapping and routing for highly parallel processor arrays %J Future Computing Systems %V 2 %N 2 %P 183-224 %0 Journal Article %A Flanders, P. M. %A Hellier, R. L. %A Jenkins, H. D. %A Pavelin, C. J. %A van den Berghe, S. %D 1991 %T Efficient High-Level Programming on the AMT DAP %J Proceedings of the IEEE %V 79 %N 4 %P 524-36 %0 Journal Article %A Fleisher, H. %A Maisel, L.I. %D 1975 %T An Introduction to Array Logic %J IBM Journal of Research and Development %V %P 98-109 %0 Conference Proceedings %A Fleury, Martin %A Clark, Adrian F. %D 1994 %T Performance Prediction for Parallel Reconfigurable Low-level Image Processing %J International Conference on Pattern Recogntion D: Parallel Computing %I International Association for Pattern Recognition %C Jerusalem, Israel %6 3 %P 349-351 %0 Conference Proceedings %A Floyd, R. W. %D 1967 %T Assigning Meanings to Programs %J Proceedings of the American Mathematical Society Symposium in Applied Mathematics %P 19-31 %0 Conference Proceedings %A Floyd, R.W. %D 1972 %T Permuting Information in Idealized Two-Level Storage %J Complexity of Computer Computations %E Miller, R.E. and Thatcher, J.W. %I Plenum Press %C New York %P 105-109 %0 Journal Article %A Floyd, R. and Steinberg, L. %D 1975 %T An Adaptive Algorithm for Spatial Grey Scale %J Society for Information Display Digest %V %P 36-7 %0 Conference Proceedings %A Floyd, R.W. %A Ullman, J.D. %D 1980 %T The Compilation of Regular Expressions into Integrated Circuits %J Proceedings of 21st Annual Symposium on Foundations of Computer Science %P 260-269 %0 Book Section %A Flynn, M.J.