Date: Mon, 02 Dec 1996 15:10:31 GMT Server: NCSA/1.4.2 Content-type: text/html CSE567 Homework Assignment #5

CSE 567: Principles of Digital Systems Design

Carl Ebeling, Fall 1996

Homework 5

Distributed: Wednesday. Nov. 6 Due Friday Nov. 15, in class


You are to work together as teams on this homework. Please look at the problems individually first and sketch possible solutions and questions. Then meet together and formulate solutions to each if you can, and assign the writeup to one or more team members. Then meet again to collate and review your solutions before you hand them in. The whole team is responsible for understanding the solution to all problems.

For problems involving Verilog code, hand in your code and your simulation log (or at least part of it if it's really long).

  1. Design two modules, one to do run-length encoding on an input stream of bytes and another to do the corresponding run-length decoding. By plugging your two modules back-to-back, you should reconstruct the original byte-stream. You must design your own protocol for this - there are optimizations you can try based on the image compression context. One of the things you must worry about is the fact that the compressed stream is not the same length as as the original stream. Although it's generally shorter, it might be longer depending on your run-length coding. Your circuits must handle any possibility of course.

    Design your circuits using Verilog and use the simulator to show that it works.

  2. Design a circuit that performs a one-level 2D wavelet transform on a 16x16 image. The image and the resulting transform are stored in two different memory modules. You should store the sub-images you produce as four 8x8 images in the 16x16 output image.

    The memories you should use are simple static RAMs with an 8-bit address, an 8-bit data input for writes, an 8-bit data output for reads and a single R/W control signal which is asserted high when reading and asserted low for writing. You should write a Verilog model for this memory. Note that it has no clock input. If R/W is asserted (read) then the data output should be what the address selects. (If the address changes, so does the data out.) If R/W is unasserted (write), then nothing happens until R/W changes to high again, at which time the data on the input is written into the memory.

  3. In this problem, you will design and test a simple cache controller using Verilog simulation. This cache is a direct-mapped, read-allocate, write-through cache. The controller sits between the processor and the cache memory and generates the control signals needed by the processor and the memory. The cache controller has the following I/O signals:

    Inputs:
    1. Read - Processor asserts to request a read.
    2. Write - Processor asserts to request a write. (Only one of Read/Write can be asserted at once)
    3. Address - Processor provides the memory address of word being read or written.
    4. Hit - The cache tag memory asserts Hit if the memory address is in the cache.
    5. Reset - Resets the cache controller into an initial state.

    Outputs:

    1. Ready - Signal to the processor indicating data is present and processor can continue.
    2. MemRead - Asserted to tell memory to perform a read operation
    3. MemWrite - Asserted to tell memory to perform a write operation. Only one of MemRead and MemWrite can be asserted at a time.
    4. MemAddress - Address to main memory of word being read/written.

    Addresses are word addresses with 4 words per cache line. On each cycle, the processor asserts a read or write request (or neither) to the cache controller along with the memory address of a word. It then waits for the Ready signal to be asserted. A cache tag module checks to see if the address is in the cache. If so, it asserts Hit in the next cycle after the Read/Write request is asserted. (You do not have to design the cache tag module - assume it's there and the Hit signal is asserted appropriately.) Different things happen depending on whether a Read or Write has been asserted:

    Write a Verilog description for this cache controller and use Verilog-XL to test your design. We will provide a driver for your design in a couple days. 


ebeling@cs.washington.edu