Date: Wed, 15 Jan 1997 00:27:27 GMT Server: Apache/1.1.1 Content-type: text/html Content-length: 10981 Last-modified: Mon, 19 Feb 1996 17:25:13 GMT Dr. Pradhan

Name: Dhiraj K. Pradhan

Title: COE Endowed Chair in Computer Science

EDUCATION:

Ph.D. Electrical Engineering, University of Iowa, 1972

M.S. Electrical Engineering, Brown University, 1970

B.S. Electrical Engineering, Annamalai University, 1969

EXPERIENCE:

Educational: COE Endowed Chair Professor, Computer Science, Texas A&M University, January 1992-present; Professor, Department of Electrical and Computer Engineering, University of Massachusetts, January 1983-January 1992; Associate Professor, School of Engineering, Oakland University, September 1978-December 1982; Research Associate Professor, Stanford University, June 1979-August 1979; Associate Professor, Department of Computer Science, University of Regina, September 1973-July 1978.

Industrial: Staff Engineer, IBM, Systems Development Laboratory, October 1972-August 1983.

Consulting: Consultant to Mitre, CDC, IBM, AT&T, DEC and Data General, 1982-present.

HONORS & PROFESSIONAL ACTIVITIES:

Professional Activities: Program Chair, 1st and 2nd IEEE International On-Line Testing Workshop, 1995-96; Program Committee Member, Fault-Tolerant Computing Symposium and Computer Architecture Conference and VLSI Test Design, 1995; Editor, IEEE Transactions on Computers, 1991-present; Editor, IEEE Computer Society Press, 1990-present; Associate Editor, Journal of Circuits, 1989-present; Editor, Journal of Electronic Testing, 1988-present; Workshop Chair, IEEE Workshop on Fault-tolerant Parallel and Distributed Systems, 1994; General Chair, IEEE Workshop on Fault-Tolerant Parallel and Distributed Systems, 1994; Program Chair, 10th and 11th IEEE VLSI Test Symposium, 1992 and 1993; IEEE Distinguished Visitor, Computer Society, 1990-93; ACM Lecturer, 1990-92; Advisory Committee, IEEE Technical Committee on Parallel Processing, 1992; Conference Chair, 22nd International Symposium on Fault-Tolerant Computing, 1992;

Awards: IEEE Meritorious Computer Society Service Award, 1994; Best Paper Award, VLSI Design Conference, 1994; Humboldt Distinguished Senior Scientist Award, Germany, 1990, Fellow of IEEE, l987.

RESEARCH INTERESTS/AREAS OF EXPERTISE: Fault-Tolerant Computing, VLSI Testing, Computer Architecture, Computer Aided Design

RESEARCH SUPPORT: NRC 1973-79, AFOSR, 1985-95 , multiple grants; NSF, 1982-92 , multiple grants' NSF, 1992-95; ONR, 1991-96; NSF, 1994-95; NSF, 1994-97; Texas 1994-96; Texas , 1994-95.

TEXT BOOKS:

Fault-Tolerant Systems Design, Prentice-Hall, Inc. April 1996.

IC Manufacturability: The Art of Process and Design Integration, (with J. de Gyvez), IEEE Press, 1996.

Fault-Tolerant Computing: Theory and Techniques , (Editor and Co-Author), Vol. I and II, Prentice-Hall, Inc., May l986 (Second Edition to appear 1991).

SELECTED PUBLICATIONS:

Journals:

"Issues in Fault Tolerant Memory Management," (with N. Bowen), IEEE Transactions on Computers, to appear.

"On-Line Detection Circuit in Built-in Self-Test for Achieving Zero Aliasing," (with S. Gupta), IEEE Transactions on Computers, accepted.

"Can Concurrent Checkers Help BIST?", (with S. Gupta), IEEE Transactions on Computers, to appear.

"Efficient Logic Verification in a Synthesis Environment," (with W. Kunz, and S. Reddy), IEEE Transactions on Computer-Aided Design, accepted.

"A Scheme to Reduce Test Application Time in Circuits with Full Scan," (with J. Saxena), IEEE Transactions on Computer-Aided Designs,, accepted.

"The Effect of Program Behavior on Fault Observability," (with N. Bowen), IEEE Transactions on Computers, accepted.

"Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Non-Cubic Allocation," (with D. Das Sharma), IEEE Transactions on Parallel and distributed Systems, to appear.

"The Hierarchical Full-Map Directory Scheme: Protocol and Performance," (with Y.C. Maa and D. Thiebault), IEEE Transactions on Computers, to appear.

"A Fault Tolerant Hybrid Memory Structure & Memory Management Algorithm," (with N. Bowen), IEEE Transactions on Computers, Vol 44(3) pp. 408-418, March 1995.

"Static and Dynamic Location Management in Distributed Mobile Environments," (with P. Krishna, and N.H. Vaidya), Computer Communication(special issue on Mobile Computing), 1995.

"A Survey of Fault-Injection Experimentation for Validating Computer System Dependability," (with J. Clark), COMPUTER, June 1995, pp. 47-56.

"Degradable Byzantine Agreement," (with N.H. Vaidya), IEEE Transactions on Computers, Vol. 44(1), pp. 146-150, January 1995.

"Safe System Level Diagnosis," (with N. Vaidya), IEEE Transactions, Vol. 43(3) pp. 367-370, March l994.

"Recursive Learning: A Precise Implication Procedure and its' application to Test Verification and Optimization," (with W. Kunz ), IEEE Transactions on Computer-Aided Design, September 1994.

"Roll Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture," (with N. Vaidya), IEEE Transactions on Computers, Vol. 43(10), pp. 1163-1174, October 1994.

"Yield Optimization of Redundant Multimegabit RAM's Using the Center-Satellite Model," (with D. Das Sharma and F. Meyer), IEEE Transactions on VLSI systems, December 1993.

"Communication Structures in Fault-Tolerant Distributed Systems," (with F. J. Meyer) NETWORKS, vol. 23, pp. 379-389, 1993.

"The Hyper-deBruijn Networks: Scalable Versatile Architecture," (with E. Ganesan), Transactions on Parallel and Distributed Systems, Vol. 4(9), pp. 962-978, September 1993.

"The Effect of Memory-Management Policies on System Reliability," (with N. Bowen), IEEE Transactions on Reliability, Vol. 42(3), pp. 375-383, September 1993.

"Processor and Memory Based Checkpoint and Rollback Recovery," (with N. Bowen), COMPUTER, pp. 22-31, February 1993.

"Modeling Live and Dead Lines in Cache Memory Systems," (with D. Thiebault and A. Mendelson), IEEE Transactions on Computers, Vol. 2(1), pp. 1-14, January 1993.

"A New Algorithm for Rank-Order Filtering and Sorting," (with B. Kar), IEEE Transactions on ASSP, vol. 41(8), pp. 2688-2694, August 1993.

"Survey of Checkpoint and Rollback Recovery Techniques," (with N. Bowen) COMPUTER, Vol. 26(2), pp. 22-31, February 1993.

"Accelerated Dynamic Learning for Test Pattern Generation in Combinational Circuits," (with W. Kunz), IEEE Transactions on Computer-Aided Design, " Vol., 12(5), pp. 684-694, May 1993.

"Fault-Tolerant Design Strategies for High Reliability and Safety," (with N. Vaidya), IEEE Transactions on Computers, Vol. 42(10), pp. 1195-1206, October l993.

CONFERENCES:

"LOT: Logic Optimization with Testability - New Transformations using Recursive Learning," (with M. Chatterjee and Wolfgang Kunz), ICCAD'95. San Jose, CA, November 5-9, l995.

"Performance and Reliability Assessment of I/0 Subsystems," (with F. Meyer and N. Vaidya), 4th International Workshop on Evaluation Techniques for Dependable Systems, October 2-3, l995.

Enhanced Tool for Evaluating the Dependability of Fault-Tolerant Computing Systems, 4th International Workshop on Evaluation Techniques for Dependable Systems, October 2-3, l995.

"Routing in Mobile Wireless Networks," (with P. Krishna, M. Chatterjee and N. Vaidya), USENIX Symposium on Mobile and Location-Independent Computing, April l995.

"On Improving OBDD-Based Verification in a Synthesis Environment," (with S. Reddy and W. Kunz), 32nd Design automation Conference, June l995.

"A Cluster-based Approach for Routing in Ad-Hoc Networks, ," (with P. Krishna, M. Chatterjee and N.H. Vaidya) USENIX Symposium on Location Independent and Mobile Computing, pp. 1-10, April 1995.

"Modified Tree Structure for Location Management in Mobile Environments," (with S. Dolev), IEEE Infocom'95 , Special Topics, April 2-6, 1995.

"Providing Seamless Communications in Mobile Wireless Networks," (with P. Krishna, B. Bakshi and N. Vaidya), 1st International Conference on Mobile Computers and Networking, Berkeley, CA, November 14-15, 1995.

"Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment," (with S. Reddy, and W. Kunz), 32nd Design Automation Conference, San Francisco, CA, pp. 414-419, June 12-16, 1995.

"Design Methodology for Test Synthesis in BIST," (with M. Chatterjee), IEEE BIST/DFT Workshop, March 1995.

"A Novel Pattern Generator for NearPerfect Fault Coverage," (with M. Chatterjee), IEEE VLSI Test Symposium, pp. 417-425, April 1995.

"ATPG-based Transformations for Random-Pattern Testable Logic Synthesis," (with M. Chatterjee and W. Kunz), IEEE/ACM Intl. conference on CAD, November l995.

"Functional Learning: A New Approach to Learning in Digital Circuits," (with Mukherjee and Jain), l2th IEEE VLSI Test Symposium, April l994.

"Location Management in Distributed Mobile Environment," (with P. Krishna, and N.H. Vaidya), Proc. of 3rd Intl. Conf. on Parallel and Distributed Information Systems, pp. 81-88, September 1994.

"New Pseudo-Random Test Pattern Generators for Stuck-at and Transition Faults," (with M. Chatterjee), 12th IEEE VLSI Test Symposium, April 25-29, 1994.

"Bit-Serial Generalized Median Filters," (with K. Bar), IEEE International Symposium for Computer-Aided Systems, 1994.

"Job Scheduling in Mesh Multicomputers," (with D. Das Sharma), 1994 International Conference on Parallel Processing, Vol. II, pp. 251-258.

"Subcube Level Time-Sharing in Hypercube Multicomputers," (with D. Das Sharma, and G. Holland), 1994 International Conference on Parallel Processing, Vol. II, pp. 134-142.

"GLFSR-A New Test Pattern Generator for BIST," (with M. Chatterjee), 1994 International Test Conference, pp. 481-490.

"Recovery in Multicomputers with Finite Error Detection Latency," (with P. Krishna, and N.H. Vaidya), Proc. of Intl. Conference on Parallel Processing, pp. 206-210, August 1994.

Patents

"Easily Testable High Speed Architectures for Large RAMs", U. S. Patent No. 4,833,677, May 23, 1989.

"Method of Circuit Verification and Multi-Level Circuit Optimization Based on Structural Implications, "U.S. Patent No. 08,263,721, June 21, 1994.