Date: Mon, 11 Nov 1996 02:14:25 GMT Server: NCSA/1.5 Content-type: text/html
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Kewal K. Saluja |
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Professor4611 Engineering Hall1415 Engineering Drive Madison, WI 53706 Tel: 608-262-6490 Fax:
E-mail: saluja@engr.wisc.edu
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We are investigating techniques to make the test generation and fault simulation process efficient for both combinational and sequential circuits. Data compression and compaction methods applicable in design for testability and built-in self-test environment are being investigated.
In the area of built-in self-test we are concentrating on regular structures such as programmable logic arrays and RAMs. We are investigating self-test algorithms which can be implemented in hardware with little performance and area penalty. In another project we are investigating ways to use built-in self-test hardware to test a system while it is performing its normal operation. The goal is that the system is tested continuously as it operates with little or no impact on system performance.
Much of our work is performed using facilities of the VLSI digital system laboratory. The laboratory houses a number of SUN stations with color monitors and terminals for programming and design.
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Last Modified: Friday, 03-May-96 16:26:43 CDT
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