Date: Mon, 11 Nov 1996 17:25:08 GMT Server: NCSA/1.5 Content-type: text/html Last-modified: Wed, 10 Apr 1996 21:32:19 GMT Content-length: 1745
UNIVERSITY OF WISCONSIN-MADISON
Computer Sciences Department | ||
CS 537
Spring 1996 | Bart Miller | |
Quiz #7
Wednesday, April 10 |
Add a TLB to the memory mapping architecture that is described above. This cache should be 2-way set associative and have 64 rows.
On every context switch.
Why?
TLB's contain mappings from virtual to physical addresses. If you do not flush the TLB, then the current process may use the mappings from the previous one, causing it to access the wrong page frames.