Date: Wed, 20 Nov 1996 20:12:52 GMT Server: Apache/1.1.1+ Content-type: text/html Content-length: 5675 Last-modified: Thu, 03 Oct 1996 19:19:33 GMT
The goal of the Avalanche project is to enable the
construction of usable and truly scalable parallel computing platforms
that are not exorbitantly expensive, yet are still capable of
achieving peta-op performance levels.
Low communication latency is the key to achieving
performance scalability for both of the common parallel computation models,
namely Message Passing and Distributed Shared Memory.
Toward this end, we are developing a memory architecture that tightly
integrates the processor, the entire memory hierarchy, and the
interconnect fabric.
The core of the effort is the development of a new
Cache and Communication Controller Unit
(CCCU) for the
Hewlett-Packard
PA 8000 CPU and the Myrinet network fabric (from
Myricom Inc).
The CCCU will inject incoming data traffic into the "appropriate level"
of the memory hierarchy to minimize message latency and cache miss
penalties. Furthermore, it supports a flexible suite of cache
coherence protocols for DSM applications
In order to achieve reasonable cost it is necessary to adopt an
approach that takes advantage of the significant performance
advantages and momentum already provided by commercial microprocessor
and interconnect fabric development efforts.
The target for the project is a 64 processing element prototype
which will be constructed in the final year of the
ARPA
(CSTO)
/ SPAWAR
supported project duration.