Date: Tue, 05 Nov 1996 00:26:19 GMT Server: NCSA/1.5 Content-type: text/html Last-modified: Fri, 12 Jul 1996 15:15:08 GMT Content-length: 3428
High-Bandwidth Address Translation for Multiple-Issue Processors,
T. M. Austin and G. S. Sohi, to appear in
23rd Annual International Symposium on Computer Architecture, May 1996.
An appendix of
detailed results
is also available.)
Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency T. M. Austin and G. S. Sohi, 28th Annual International Symposium on Microarchitecture (MICRO-28), 1995.
The Microarchitecture of Superscalar Processors J. E. Smith and G. S. Sohi, in Proceedings of the IEEE.
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References M. Franklin and G. S. Sohi, in IEEE Transactions on Computers.
Multiscalar Processors, G. S. Sohi, S. Breach, and T. N. Vijaykumar, 22th International Symposium on Computer Architecture, 1995.
Streamlining Data Cache Access with Fast Address Calculation, T. M. Austin, D. N. Pnevmatikatos, and G. S. Sohi, 22th International Symposium on Computer Architecture, 1995.
The Anatomy of the Register File in a Multiscalar Processor, S. Breach, T. N. Vijaykumar, and G. S. Sohi, 27th Annual International Symposium on Microarchitecture (MICRO-27), 1994.
The Multiscalar Architecture Manoj Franklin, Ph.D. thesis, December 1993,
Control Flow Prediction for Dynamic ILP Processors, D. Pnevmatikatos, M. Franklin and G. S. Sohi, 26th Annual International Symposium on Microarchitecture (MICRO-26), 1993.
The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism, M. Franklin and G. S. Sohi, 19th International Symposium on Computer Architecture, 1992.
Register Traffic Analysis for Streamlining Inter-operation Communication in Fine-Grain Parallel Processors, M. Franklin and G. S. Sohi, 25th Annual International Symposium on Microarchitecture (MICRO-25), 1992.