MIME-Version: 1.0 Server: CERN/3.0 Date: Tuesday, 07-Jan-97 15:58:08 GMT Content-Type: text/html Content-Length: 2435 Last-Modified: Tuesday, 09-May-95 21:15:55 GMT
In this paper, we present a layer assignment method for high-performance multi-chip module environments. In contrast with treating global routing and layer assignment separately, our method assigns nets to layers while considering preferable global routing topologies simultaneously. We take transmission line effects into account to avoid noise in high-speed circuit packages. The problem is formulated as a quadratic Boolean programming problem and an algorithm is presented to solve the problem after linearization. Our method is applied to a set of benchmark circuits to demonstrate the effectiveness.Contact: chao@cs.utexas.edu
With the increasing density of VLSI circuits, the interconnection wires are getting packed even closer. This has increased the effect of interaction between these wires on circuit performance and hence, the importance of controlling crosstalk. We consider the gridded channel routing problem where, specifically, the channel has 3 routing layers in the VHV configuration. Given a horizontal track assignment for the nets, we present an optimal algorithm for minimizing the crosstalk between vertical wiring segments in the channel by finding an optimal vertical layer assignment for them. We show an algorithm that minimizes total crosstalk between between wires on the same V layer on adjacent columns of the grid in O(v log v) time using O(v) memory, where the channel has v columns. We then extend this algorithm to consider crosstalk between wires in non-adjacent columns and between wires on different layers.Contact: thakur@cs.utexas.edu