Server: Netscape-Enterprise/2.0a Date: Wed, 13 Nov 1996 23:15:10 GMT Content-type: text/html
Lab exercises 1 to 5 in Module 2 -- pages 2-59 to 2-74
Lab exercises 1 to 4 in Module 3 -- pages 3-59 to 3-82
You need not submit this work.
Lab exercises in Module 1 -- pages 1-32 to 1-45
Lab exercises in Module 7 -- pages 7-30 to 7-42
Lab exercises in Module 8 -- pages 8-30 to 8-41
You need not submit this work.
The clock signal has a period of 100ns and it is low from 0 to 50ns and high from 50 to 100ns. All input signals, namely the signals associated with the input digits and the reset signal, change only in the window +/- 0.1ns of the rising edge of clock. The output det must go high as soon as the last 1 of the pattern arrives (i.e., well before the next falling edge of the clock) and remain high till the falling edge of the clock.
Design your circuit with appropriate state assignment. Use fewest number of states and state-variables to complete your design. Remember that the circuit is fully synchronous and the reset input does not reset the flip-flops asynchronously.
Assume that the flip-flops have a small non-zero setup time and a zero hold time. In your submission include the state table, provide the sate assignment, schematic, force files showing your test sequence, and a well commented Quicksim output for your test sequence. Also submit a clear documentation explaining the steps you used to arrive at the design.
Your work that is to be submitted for this problem should be no more than five pages. Thus provide all the necessary information in reasonably compact manner with appropriate comments.