Date: Wed, 20 Nov 1996 19:17:28 GMT Server: Apache/1.1.0 Content-type: text/html Last-modified: Thu, 26 Sep 1996 14:20:45 GMT Design Automation Research Group

Design Automation Research Group


Design Automation Research Group is an inter-departmental and inter-disciplinary group composed faculty from Computer Science Department and Electrical Engineering Department. The research focus is to promote productivity of engineering system design using rapidly improving information technology. It includes how to model the design, manage the design/ manufacturing process, validate the correctness of design, and support the life cycle of the product. Research projects have been supported by Government such as NSF, Air Force and Industries such as Ford.


Faculty


Research Projects


Principal Investigators: Moon Jung Chung and Anthony Wojcik
As the complexity of products increases, companies need to develop solid and effective process management for various aspects of production, allowing them to promote productivity and to fully utilize the rapid progress in information technology. Effective design process management is crucial to the survival of industries in global competition, especially for the Michigan automotive industry. Our approach is based on formal modeling of design process using process grammar. This research work has been supported by the Air Force Wright Patterson Laboratory, and System Engineering Research Institute.
Principal Investigator: Moon Jung Chung
Simulation is a bottleneck in a design process. The focus of the research is on Parallel VHDL Performance Simulation. With the support from DoD HPC Modernization Program, we are developing a parallel simulation engine targeted for the SP2 machine which can achieve a speed-up up to 100 times compare to sequential simulation.
Principal Investigators: Anthony Wojcik, Moon Jung Chung, Bill Punch and Jon Sticklen
Of considerable interest in the design automation community is the problem of reengineering, or redesign, of electronic circuits. The basic problem is to take a given design and to respecify or remanufacture an electronic part, board, or system. The key problem is that original design information may be missing or incomplete. Hence, redesign starts with only partial knowledge of the target system and must infer original specifications. Our approach to this problem incorporates the use of formal methods. Formal methods refers to the collection of approaches based on mathematical logic and formal proof techniques used for the design and analysis of hardware and software systems. Our work includes the use of a variety of formal methods including automated reasoning, genetic algorithms, and knowledge- based systems.
Principal Investigator: Anthony Wojcik
As systems become ever more complex, it becomes increasingly important to be able to verify properties about systems. Clearly, one property is that the system functionally implements the intended specification. However, there are other properties of interest, including fault-tolerance and security. A critical problem is the modeling of properties of systems and then the verification of the properties. It is clear that simulation alone cannot be used to verify properties. For that reason, the use of formal methods continues to be of great importance. Formal methods refers to the collection of approaches based on mathematical logic and formal proof techniques used for the design and analysis of hardware and software systems. Our work is concerned both with the use of appropriate representations for modeling systems and properties of systems, and the application of techniques incorporating automated reasoning systems, Prolog and other approaches in order to prove properties of systems.
Principal Investigator: Michael Shanblatt
Graduate Student: Manuel Jimenez

Reducing the amount of power dissipated by integrated circuits has become an issue of major concern in the design of digital VLSI systems. Among the factors pushing for power efficient circuits are the tight energy budgets of portable computing and commu-nication devices, the reliability concerns of the circuits themselves, and the packaging and cooling costs associated with power hungry devices. This project involves the development of a new placement approach in very large scale integration (VLSI) designs aimed at producing layouts of circuits with reduced power dissipation. More specifically, a placement methodology for digital VLSI circuits is under development, whose objectives include minimizing the power dissipation of the resulting circuit while maintaining the estimated wire length and layout within pre-established bounds.