Date: Tue, 05 Nov 1996 00:16:21 GMT Server: NCSA/1.5 Content-type: text/html Last-modified: Fri, 13 Sep 1996 15:33:22 GMT Content-length: 18153 Andy Glew's Resume

Andy Glew

412 West Shore Drive
Madison, WI 53715

Home: 503-693-9830
glew@cs,wisc.edu glew@ichips.intel.com

Career Goals

Skills

Performance Tuning and Analysis
Hardware
Software

Education

Employment

January 1991-date: Intel Corporation, Hillsboro, Oregon

August 1996-date: Student
Although I continue to be affiliated with Intel's Microcomputer Research Labs - e.g. I am still covered by the Intel NDA, and will work at Intel on breaks - I am now mainly a full time student pursuing my Ph.D.
November 1995-August 1996: Computer Architect/Researcher, Microcomputer Research Labs; Leader, Intel Architecture CPU Research Group

Manager: Richard Wirt (Intel Fellow).

I agreed tp spend approximately one year (prior to returning to school to finish my Ph.D.) helping to get this research group off the ground, defining the research directions hiring 5 Ph.D. level researchers (and trying to hire more), and budgetting and arranging capital purchases of approximately 500,000$ in computer equipment and services.

January 1991-November 1995: Computer Architect, P6.

Managers: Bob Colwell (1991-1993), Dave Papworth (1993-1995).

  • One of five architects involved in the Original P6 Microarchitecture Definition (in 1991) and supported design by providing oversight and making global tradeoffs throughout the life of the project.
    • Defined top-level interface between subsystems.
    • Defined execution unit "uop" instruction set.
    • Defined microcode format.
    • Significant contributions to design of non-blocking cache.
    • Defined and performed initial RTL coding of branch mechanism, including interfaces between BTB and execution units.
    • Simulation studies to simplify logic involved in retirement of branches.
    • Defined global control register bus.
  • After initial definition phase led P6 HW/SW Codevelopment team (up to 3 full time engineers, 3 students)
    • Wrote P6 External Architecture Specification. Defined all new architecturally visible features (Machine Check, mechanisms for reducing TLB invalidations, memory types) and new instructions (conditional moves, fast system calls).
    • Liaison between P6 Architecture and software groups: compilers, OSes (Intel and Microsoft), assembly language applications such as multimedia, video, 3D graphics, and games developers.
    • Wrote P6 Code Tuning Guide.
    • Defined new memory types that increase memory to framebuffer performance by 4-7X.
    • Defined and supervised block memory fill and copy optimizations, including inventing a new cache protocol that reduces memory traffic by 50-30%.
    • Tuned code, including a single, notorious, optimization that improved iSPEC92 by approximately 25%. Supervising recent work improving branch predictability. Supervising much work improving performance analysis tools for code tuning.
    • Defined P6 Performance Monitoring hardware (EMON). Defined and supervised development of software (UNIX and Windows) to perform EMON profiling, a new method of performance analysis involving statistical sampling of code locations associated with particular performance problems.
    • Defined and supervised development of Priviliged Mode Execution (PMX) device driver, on UNIX on Microsoft OSes, permitting access to many hardware priviliged facilities from user code, facilitating automation of many performance and validation testing procedures.
    • Initially defined and supervised development of API Profiling device drivers on Windows 3.1, which permitted investigation of performance issues not just by flat code location, but also according to call tree. Supervised first application of this tool to tuning computer games and 3D graphics applications.
  • Acted as an x86 architecture expert, frequently representing P6 to Intel's Compatibility Architecture Review Team (CART).
    • Creator and keeper of the official Intel x86 Instruction Set Definition, on behalf of CART.
    • CART expert on APIC (interrupt controller) architecture.
    • CART expert on SMM (System Management Mode).
  • Original investigator of x86 instruction set enhancements to support multimedia, video, and graphics; P6 representative on MMX definition effort; key inventions that permit instruction set enhancement without OS changes.
  • P6 representative in evaluation of future instruction set architectures.
  • Future x86 microarchitectures.
  • Member of Intel Research Council's Natural Datatypes Technical Committee, supervising research in multimedia, graphics, speech and handwriting recognition, etc.

January 1990-May 1990: Teaching Assistant Foundations for VLSI Design Automation

Course CS497-LGJ taught by Professor Larry Jones, at AT&T Bell Labs Naperville (Indian Hill). University of Illinois at Urbana-Champaign, Department of Computer Science.

December 1985-November 1989: OS Developer

From December 15 1985 to November 15 1989 I was a member of the technical staff at 1101 E. University, Urbana, IL 61801. Before October 7, 1988, the site was owned by Gould CSD. On October 7, 1988, the site was sold to Motorola MCD. On November 15, 1989, I left to take a vacation before returning to full-time studies in January 1990.

1986: Programmer, Systemes Videotex FORMIC, Saint Laurent, Quebec.
1982-1986: UNIX System Manager,
Electrical Engineering Undergraduate Computer Lab, McGill University. PDP-11/40 and CODATA MC68000 based machines running UNIX V7, Matrox graphics and image processing systems.
1981-1984: Computer Operator/Programming Consultant,
McConnell Computing Facility, McGill University. IBM 370 assembly, COBOL, FORTRAN, PASCAL, PL/1.
Summer 1979: Student Programming Assistant, Concordia University.
FORTRAN graphics programming of wireframe aircraft models on a PDP-11/40 running RT-11v4, and on CDC NOS.

Other Training

Publications

Awards

Intel Acheivement Award, 1996
for the Pentium Pro Processor Dynamic Execution microarchitecture; shared with Bob Colwell, Dave Papworth, Glenn Hinton, and Mike Fetterman.
Divisional Recognition Award, 1996
Intel Israel Design Center (IDC), for the creativity and driving of Intel Architecture Microprocessor Multimedia Extension (IA-MMX) Architecture definition; shared with many other members of the MMX team led by Alex Peleg and Uri Weiser.

Patents

Co-inventor on more than 100 Intel patent disclosures filed and approved for submission to patent office, more than 40 of which have been submitted to patent office. At last count 7 patents have been awarded by US patent office.

Personal

References

The following is a coworker in Intel's Microcomputer Research Labs, who also worked with me through much of P6:

The following were my managers at Intel during P6:

Both are at: Intel Corporation, 2111 NE 25th Ave mailstop JF1-19 Hillsboro, OR 97124-5961.

My MS advisor:

The following Intel luminaries have agreed to provide phone references as to my character. They're too busy and not allowed to write to write letters of reference, but I wanted to include their names here as blatant name dropping:

Previous employer:


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