Date: Mon, 11 Nov 1996 02:14:25 GMT Server: NCSA/1.5 Content-type: text/html Saluja, Kewal K.
College of Engineering
University of Wisconsin - Madison

ECE

Kewal K. Saluja

Kewal K. Saluja

Professor

4611 Engineering Hall
1415 Engineering Drive
Madison, WI 53706
Tel: 608-262-6490
Fax:

E-mail: saluja@engr.wisc.edu
Portrait: 9K JPG


Departments
Electrical and Computer Engineering
Computer Science

Education
PhD 1973, University of Iowa

Research Interests
design for testability, computer architecture, data compression, integrated circuits (VLSI), fault-tolerant computing


My general area of research interest is test generation and testable and reliable design of digital systems. To carry out research in this area we make extensive use of VLSI CAD and analysis tools. The research involves modeling of faults, designing digital circuits, test generation, design modification for enhancing testability, built-in self-testing designs, fabrication of circuits and test application.

We are investigating techniques to make the test generation and fault simulation process efficient for both combinational and sequential circuits. Data compression and compaction methods applicable in design for testability and built-in self-test environment are being investigated.

In the area of built-in self-test we are concentrating on regular structures such as programmable logic arrays and RAMs. We are investigating self-test algorithms which can be implemented in hardware with little performance and area penalty. In another project we are investigating ways to use built-in self-test hardware to test a system while it is performing its normal operation. The goal is that the system is tested continuously as it operates with little or no impact on system performance.

Much of our work is performed using facilities of the VLSI digital system laboratory. The laboratory houses a number of SUN stations with color monitors and terminals for programming and design.


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