Date: Mon, 25 Nov 1996 23:58:23 GMT Server: NCSA/1.5.1 Last-modified: Fri, 08 Nov 1996 18:40:52 GMT Content-type: text/html Content-length: 4192 Rocket

The Rocket Project

Principal Investigators:

Current Graduate Students:

Current Undergraduates:

Description:

The goals of the Rocket project are to develop a retargetable compiler for instruction-level parallel architectures and to develop scheduling and register allocation algorithms for said architectures. This project intimately is entwined with the Memoria project. Current research efforts include software pipelining, register-sensitive scheduling, and register allocation and scheduling for partitioned register files.

Publications:

S. J. Beaty, S. Colcord, P.H. Sweany."Using Genetic Algorithms to Fine-Tune Instruction-Scheduling Heuristics", In Proceedings of MCPS '96.

M.J. Bourke III, P.H. Sweany, S.J. Beaty."Extending List Scheduling to Consider Execution Frequency", In Proceedings of the 29th Annual Hawaii International Conference on System Sciences.

S. Carr, C. Ding and P. Sweany, "Improving Software Pipelining with Unroll-and-Jam", In Proceedings of the 29th Annual Hawaii International Conference on System Sciences.

T. Brasier, P. Sweany, S. Beaty and S. Carr, "CRAIG: A Practical Framework for Combining Instruction Scheduling and Register Assignment", 1995 International Conference on Parallel Architectures and Compiler Techniques.

P.H. Sweany, S.J. Beaty."Dominator-Path Scheduling: A Global Scheduling Method", Proceedings of the 25th International Symposium on Microarchitecture (MICRO-25).

P.H. Sweany, S.J. Beaty."Post-Compaction Register Assignment in a Retargetable Compiler", In Proceedings of the 23rd Microprogramming Workshop (MICRO-23).

Research Grants:

"Generating Efficient Code for Horizontal Micro-Architectures With Partitioned Register Files", Texas Instruments, 1995-1996, $23,715.

"Hiding the Latency Between Level-1 and Level-2 Cache on the Alpha 21164", Digital Equipment Corporation, 1995-1997, $83,500.

Masters' Theses:

M.J. Bourke. "Frequency-Based List Scheduling: List Scheduling to Incorporate Frequency Information", Michigan Technological University, Department of Computer Science, May 1993.

T.S. Brasier. "FRIGG: A New Approach to Combining Register Assignment and Instruction Scheduling", Michigan Technological University, Department of Computer Science, August 1994.

B.L. Huber. "Path-Selection Heuristics for Dominator-Path Scheduling", Michigan Technological University, Department of Computer Science, October 1995.

C. Ding. "Improving Software Pipelining with Unroll-and-Jam and Memory-Reuse Analysis", Michigan Technological University, Department of Computer Science, June 1996.

Q. Wu. "Register Allocation via Hierarchical Graph Coloring", Michigan Technological University, Department of Computer Science, August 1996.