Newsgroups: sci.image.processing
From: simon@sdixon.demon.co.uk (simon fowler-dixon)
Path: cantaloupe.srv.cs.cmu.edu!das-news2.harvard.edu!news2.near.net!news.mathworks.com!udel!gatech!howland.reston.ans.net!news.sprintlink.net!peernews.demon.co.uk!sdixon.demon.co.uk!simon
Subject: Re: Morphology ICs?
References: <m8902994.22.00FC50A8@chudich.cse.rmit.edu.au>
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Date: Sun, 26 Feb 1995 21:34:37 +0000
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Grey-level morphology is normally performed in hardware using rank 
value filter devices, selecting least in rank for erosion, greatest for 
dilation and centre value for median. Binary morphology can be 
performed using a LUT taking pixel values within a neighborhood as 
input and loaded with appropriate result values for all possible 
combinations of input. It can also be performed using a binary 
correlator device which outputs a result based on neighborhood 
operations using a matrix of '1','0', and 'dont care' values.
I think available RVFs are ASICs - I dont know who does them but I'll 
look. LUTs are memory but require some means of generating a 
neighborhood, probably involving line buffers and shift registers - and 
binary correlation could well be best done using programmable logic.
This does quite answer your question but i hope its of use.

simon fowler-dixon

