Newsgroups: comp.robotics
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From: gcouger@olesun.okstate.edu (Gordon Couger)
Subject: Re: 68HC11 performance question
Message-ID: <gcouger.747699582@olesun.agen.okstate.edu>
Keywords: 68HC11 timing interrupt
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Organization: Oklahoma State University Computer Center, Stillwater OK
References: <geoCD5JoK.8J1@netcom.com>
Date: Fri, 10 Sep 1993 22:19:42 GMT
Lines: 36

geo@netcom.com (George Pontis) writes:

>Hello,
>Can someone answer a few questions regarding HC11 execution speed ?

>I'm considering a design for an embedded system that needs to control
>4 stepper motors, two of them microstepped at a 5KHz rate. If I were to
>implement a system using an HC11 that had a hardware interrupt rate at
>5 KHz, how much processor bandwidth would remain for computation ?

>I'm looking for a very rough %, or approximate # clocks that an ISR 
>could spend on useful work after stack mangement and other overhead.
 
 Martin McCormick wrote a bucket brigade delay line
with 68HC11 with a 2MHz E clock that put a byte to
and output port, do an A/D conversion store at the 
same location as the byte he output and increment 
the pointer to the next byte. He was able to get this
to operate at 8 KHz. With out seeing his code I think
it takes 48 clock cycles not counting interrupt over head.

If you could do the setting to the stepper motor port in 
10 clock cycles you would use 40 cycles.  Using the
example above I think it should take 53% of your time
to service the interrupts. Doing 4 steppers in 40 clocks
will be challenging.

Good luck
Gordon

Gordon Couger 
Biosystems & Agricultural Engineering
Oklahoma State University
114 Ag Hall, Stillwater, OK  74074
gcouger@olesun.agen.okstate.edu 405-744-9763 day 624-2855 evenings 

