\section{Register Descriptions}
\label{sec-reg-desc}

{\sc This section is under reconstruction.}

A register \emph{class} is a group of registers sharing the same physical
capabilities.  For each register candidate, there is a set of classes
describing the registers to which the candidate could feasibly be assigned.
The number of classes and the way they are ascribed to register candidates
differ from machine to machine.  On a simple RISC machine, there might be a
class for the general-purpose register bank and another for the
floating-point bank.  Conceivably, no candidate would have both classes.
On the Motorola 68000, the data registers and the address registers might
each form a class.  Some candidates could be assignable to either class,
and so their associate class sets would contain both.

<<declarations for register selection>>=
typedef unsigned long RegClassMask;	// set of register classes
typedef NatSetDense RegCells;		// set of register cells

const RegClassMask ALL_CLASSES = ULONG_MAX;
typedef Vector<RegClassMask> RegClassMap;
@

\subsection{Query functions for register descriptions}

The first three of these produce vectors that you index by abstract register
number.

\begin{itemize}
\item [[reg_names]] returns a vector giving the assembler name for each
      register.

\item [[reg_widths]] returns a vector giving the size in bits of each
      register.

\item [[reg_models]] returns a vector giving the resource model for each
      register.  A \emph{model} is a [[NatSet]] whose elements, called
      \emph{cells} represent physical resources in a register bank.  Their
      interpretation is completely target-specific.

\item [[reg_lookup]] returns the abstract register number for a given
      assembler name.

\item [[reg_maximal]], returns the maximal-width register that subsumes the
      register given as its argument.

\item [[reg_allocatables]] returns the set of abstract numbers for all
      registers that are available for register allocation.  When called
      with its optional argument [[true]], it returns the subset that have
      maximal width. 

\item [[reg_caller_saves]] returns the subset of allocatable registers that
      obey a \emph{caller-saves} convention, i.e., that may be changed and
      not restored by a called procedure.  With optional argument [[true]],
      it returns only the maximal-width caller-saves registers.

\item [[reg_callee_saves]] returns the subset of allocatable registers that
      obey a \emph{callee-saves} convention, i.e., that must re restored by
      a called procedure if it changes them.  With optional argument [[true]],
      it returns only the maximal-width callee-saves registers.

\item [[reg_freedom]] translates a set of register classes to a ``degree of
      freedom'', i.e., the number of available registers for any candidate
      that can be satisfied with a register in that class set.  The third,
      [[reg_classify]], analyzes an instruction and associates
      register-class sets with its operands, identifying each operand by
      its number in a given operand catalog.  The fourth, [[reg_choice]],
      chooses and returns one register that is a feasible home for a value
      satisfying several criteria. Its arguments are a register class set,
      the width in bits of the value, a set of register grains that must
      not overlap the chosen register, and a flag indicating whether to use
      a round-robin policy.  A negative result from [[reg_choice]] means
      that no acceptable register exists.

\item [[reg_classify]] scans the operands of an instruction, an uses an
      operand catalog to obtain an integer identifier for each register
      candidate.  It updates a map giving the feasible register classes for
      each operand.

\item [[reg_choice]] tries to select one register that is consistent with
      constraints on its class, its convention, a set of excluded physical
      resources, and the width of the value it must hold.  Flag [[rotate]]
      indicates that successive choices satisfying similar criteria should
      be scattered.

\item [[reg_info_print]] prints a description of the registers of teh
      current target.
\end{itemize}

<<register query functions>>=
const Vector<const char*>& reg_names();
const Vector<int>& reg_widths();
const Vector<RegCells>& reg_models();

int reg_lookup(const char *name);

const NatSet* reg_allocatables(bool maximal = false);
const NatSet* reg_caller_saves(bool maximal = false);
const NatSet* reg_callee_saves(bool maximal = false);
int reg_maximal(int reg);
int reg_freedom(RegClassMask);
void reg_classify(Instr*, OpndCatalog*, RegClassMap*);
int reg_choice(const NatSet *pool, RegClassMask classes, 
	       const RegCells &excluded, int width, bool rotate = false);
void reg_info_print(FILE*);
@



\subsection{Header file for module [[reg_info.h]]}

The interface file has the following layout:

<<reg\_info.h>>=
/* file "machine/reg_info.h" */

<<Machine-SUIF copyright>>

#ifndef MACHINE_REG_INFO_H
#define MACHINE_REG_INFO_H

#include <machine/copyright.h>

#ifndef SUPPRESS_PRAGMA_INTERFACE
#pragma interface "machine/reg_info.h"
#endif

#include <machine/substrate.h>
#include <machine/machine_ir.h>
#include <machine/nat_set.h>
#include <machine/opnd.h>

<<declarations for register selection>>

<<register query functions>>

#endif /* MACHINE_REG_INFO_H */
@