| Class | Date | Day | Topic | Reading | Homework | Who |
| 1 | 9/15 | Tu | Performance & Technology | H&P Ch. 1 | #1 Out | TCM |
| 2 | 9/17 | Th | Alpha/DLX Programming | H&P Ch. 2 | TCM | |
| 3 | 9/22 | Tu | Instruction Set Comparison | H&P App. C & D | TCM | |
| 4 | 9/24 | Th | Pipelined Implementation | H&P Ch. 3 | #1 Due, #2 Out | TCM |
| 5 | 9/29 | Tu | Advanced Pipelining | H&P Ch. 4 | TCM | |
| 6 | 10/1 | Th | Instr. Level Parallelism | TCM | ||
| 7 | 10/6 | Tu | Computer Arithmetic | H&P App. A | REB | |
| 8 | 10/8 | Th | Cache Memory | H&P Ch. 5 | #2 Due, #3 Out | REB |
| 9 | 10/13 | Tu | Virtual Memory | REB | ||
| 10 | 10/15 | Th | Alpha 21264 Case Study | Gwennap | REB | |
| 11 | 10/20 | Tu | Multimedia Integration | REB | ||
| 12 | 10/22 | Th | Input/Output & Storage | H&P Ch. 6 | #3 Due | REB |
| 13 | 10/27 | Tu | Network Mechanisms | H&P Ch. 7, Keshav | ALF | |
| 14 | 10/29 | Th | Midterm, Network Protocols | Keshav | #4 Out | ALF |
| 15 | 11/3 | Tu | Multiprocessor Arch. Overview | H&P Ch. 8, CSG Ch. 1 | TCM | |
| 16 | 11/5 | Th | Parallel Programming | CSG Ch. 2 & 3 | #4 Due, #5 Out | TCM |
| 17 | 11/10 | Tu | Cache Coherence | CSG Ch. 5, 6, & 8 | TCM | |
| 18 | 11/12 | Th | Mem. Consistency & Latency Hiding | CSG Ch. 9.2 & 11 | TCM | |
| 19 | 11/17 | Tu | Cache Protocol Verification | Clarke | REB | |
| 20 | 11/19 | Th | Multiprocessor Interconnects | H&P Ch. 8, CSG Ch. 10 | #5 Due, #6 Out | TCM |
| 21 | 11/24 | Tu | Synchronization, Origin Case Study | CSG Ch. 7, Laudon97 | TCM | |
| 11/26 | Th | Thanksgiving | ||||
| 22 | 12/1 | Tu | Future Technology | REB | ||
| 23 | 12/3 | Th | Application Case Study | #6 Due | REB | |
| 12/9 | We | Final Exam (1-4pm) | ||||
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Todd C. Mowry