15-740 Fall '01
In-Class Discussions

Uniprocessors, Part 0: Wednesday, October 2, 2001

We scheduled this first discussion session early to provide an example of what we have in mind for future discussion sessions.
• Prefetching Pointer-Based Applications:
  • Chi-Keung Luk and Todd C. Mowry. Compiler-Based Prefetching for Recursive Data Structures, in Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, pages 222-233, October 1996.
  • Amir Roth and Gurindar S. Sohi. Effective Jump Pointer Prefetching for Linked Data Structures, in Proceedings of the 26th Annual International Symposium on Computer Architecture, May 1999.
  
  

Topic	Time Slot	Discussion Leader
Prefetching Pointer-Based Applications	11:30-11:50	Todd C. Mowry

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Uniprocessors, Part 1: Friday, October 5, 2001

NOTE: people who lead discussions on this date will get a 3 day extension on Assignment 2.
• Branch Prediction:
  • Cliff Young, Nicolas Gloy, and Michael D. Smith. A Comparative Analysis of Schemes for Correlated Branch Prediction, in Proceedings of the 22nd Annual International Symposium on Computer Architecture, May 1995.
  • Timothy Heil, Zak Smith, and James E Smith. Improving Branch Predictors by Correlating on Data Values, in Proceedings of the 32nd Annual International Symposium on Microarchitecture, November 1999.
  • Joel Emer and Nikolas Gloy. A Language for Describing Predictors and its Application to Automatic Synthesis, in Proceedings of the 24th Annual International Symposium on Computer Architecture, June 1997.
• Trace Caches:
  • Eric Rotenberg, Steve Bennett, and James E. Smith. A Trace Cache Microarchitecture and Evaluation, in IEEE Transactions on Computers, 48(2):111-120, February 1999.
  • Bryan Black, Bohuslav Rychlik, and John Paul Shen. The Block-based Trace Cache, in Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 196-207, May 1999.
• Value Prediction:
  • Mikko H. Lipasti and John Paul Shen. Exceeding the Dataflow Limit via Value Prediction, in Proceedings of 29th Annual International Symposium on Microarchitecture, November 1996.
  • Avinash Sodani and Gurindar S. Sohi. Understanding the Differences Between Value Prediction and Instruction Reuse, in Proceedings of the 31st Annual International Symposium on Microarchitecture, November 1998.
• Transmeta and Dynamic Code Optimization:
  • Alexander Klaiber. The Technology Behind Crusoe Processors, Transmeta Corporation, http://www.transmeta.com/crusoe/technology.html.
  • Yuan Chou and John Paul Shen. Instruction Path Coprocessors, in Proceedings of the 27th International Symposium on Computer Architecture, June 2000.

 

Topic	Time Slot	Discussion Leaders
Branch Prediction	10:30-10:50	Shuchi Chawla, Aditya Akella & Jia-Yu Pan
Trace Caches (notes)	10:50-11:10	Takayuki Osogami & Maverick Woo
Value Prediction (slides)	11:10-11:30	Amit Manjhi & Brian Potetz
Dynamic Code Optimization (slides [PPT])	11:30-11:50	Mahim Mishra, Matt Rosencrantz & Ashwin Bharambe

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Uniprocessors, Part 2: Monday, October 8, 2001

• Database Performance:
  • Luiz André Barroso, Kourosh Gharachorloo, and Edouard Bugnion. Memory System Characterization of Commercial Workloads, in Proceedings of the 25th Annual International Symposium on Computer Architecture, June 1998.
  • K. Keeton, D. A. Patterson, Y. Q. He, R. C. Raphael, and W. E. Baker. Performance Characterization of a Quad Pentium Pro SMP Using OLTP Workloads, in Proceedings of the 25th International Symposium on Computer Architecture, June 1998.
  • A. Ailamaki, D. J. DeWitt, M. D. Hill, and D. A. Wood, DBMSs on a Modern Processor: Where Does Time Go? in Proceedings of the 25th International Conference on Very Large Data Bases (VLDB), Edinburgh, UK, September 1999.
• Multimedia Support:
  • Parthasarathy Ranganathan, Sarita Adve, and Norman P. Jouppi, Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions, in Proceedings of the 26th International Symposium on Computer Architecture, May 1999.
  • Linley Gwennap. Digital, MIPS Add Multimedia Extensions, Microprocessor Report, 10(15), November 18, 1996.
  • Keith Diefendorff. Pentium III = Pentium II + SSE, Microprocessor Report, 13(3), March 8, 1999.
• Predication and IA-64:
  • David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, and Wen-mei W. Hwu. Integrated Predicated and Speculative Execution in the IMPACT EPIC Archtecture, in Proceedings of the 25th International Symposium on Computer Architecture, July 1998.
  • Peter Christy. IA-64 and Merced--What and Why, Microprocessor Report, 10(17), December 30, 1996.
  • Peter Song. Demystifying EPIC and IA-64, Microprocessor Report, January 28, 1998.
  • Linley Gwennap. Intel Discloses New IA-64 Features, Microprocessor Report, 13(3), March 8, 1999.
  • Linley Gwennap. IA-64: A Parallel Instruction Set, Microprocessor Report, 13(7), May 31, 1999.
• Reconfigurable Computing:
  • Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, Ronald Laufer. PipeRench: A Coprocessor for Streaming Multimedia Acceleration, in Proceedings of the 26th Annual International Symposium on Computer Architecture, May 1999.
  • R. Razdan and M.D. Smith. A High-Performance Microarchitecture with Hardware-Programmable Functional Units , in Proceedings of the 27th International Symposium on Microarchitecture (Micro-27), pages 172-180, November 1994.
  • João M. P. Cardoso and Mário P. Véstias. Architectures and Compilers to Support Reconfigurable Computing, ACM Crossroads, August 1999.

 

Topic	Time Slot	Discussion Leaders
Database Performance	10:30-10:50	Rose Hoberman, Muralidhar Talupur & Bianca Schroeder
Multimedia Support (slides [PPT])	10:50-11:10	Jernej Barbic & Luis von Ahn
Predication & IA-64	11:10-11:30	Mike Ferdman, Susmit Sarkar & Dan Blandford
Reconfigurable Computing (slides part1 [PPT], part2)	11:30-11:50	Kaustuv Chaudhuri, Bartosz Przydatek & Anton Likhodedov

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Multiprocessors: Monday, November 5, 2001

• Memory Consistency Models:
  • S. V. Adve, V. S. Pai, and P. Ranganathan. Recent Advances in Memory Consistency Models for Hardware Shared-Memory Systems, in Proceedings of the IEEE, special issue on distributed shared-memory, March 1999, 445-455.
  • Chris Gniady, Babak Falsafi, and T. N. Vijaykumar. Is SC + ILP = RC?, in Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 162-171, May 1999.
  • Mark D. Hill. Multiprocessors Should Support Simple Memory Consistency Models,, in IEEE Computer, August 1998.

• Simultaneous Multithreading:
  • Susan Eggers, Joel Emer, Henry Levy, Jack Lo, Rebecca Stamm, and Dean Tullsen. Simultaneous Multithreading: A Platform for Next-generation Processors, in IEEE Micro, September/October 1997, pages 12-18.
  • Jack Lo, Susan Eggers, Joel Emer, Henry Levy, Rebecca Stamm, and Dean Tullsen. Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multithreading, in ACM Transactions on Computer Systems, August 1997, pages 322-354.

• Speculative Multiprocessing:
  • Lance Hammond, Mark Willey, and Kunle Olukotun. Data Speculation Support for a Chip Multiprocessor, in Proceedings of the Eighth ACM Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, October 1998.
  • J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai and Todd C. Mowry. A Scalable Approach to Thread-Level Speculation, in Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 1-12, June 2000.

• Parallel Applications:
  • Dongming Jiang and Jaswinder Pal Sing. Scaling Application Performance on a Cache-coherent Multiprocessor, in Proceedings of the 26th Annual International Symposium on Computer Architecture, pages 305-316, May 1999.
  • Hongzhang Shan and Jaswinder Pal Singh. A Comparison of the MPI, SHMEM and Cache-coherent Shared Address Space Programming Models on the SGI Origin2000, in Proceedings of the International Conference on Supercomputing, June 1999.
  • Chris Holt, Jaswinder Pal Singh and John Hennessy. Application and Architectural Bottlenecks in Distributed Shared Memory Multiprocessors, in Proceedings of the 22nd International Symposium on Computer Architecture, pages 134-145, May 1996.

 

Topic	Time Slot	Discussion Leaders
Memory Consistency Models (slides)	10:30-10:50	Lucian Lita, Monica Rogati & Doug Vail
Simultaneous Multithreading (slides [PPT])	10:50-11:10	Ting Liu, Liu Ren & Hua Zong
Speculative Multiprocessing (slides [PPT])	11:10-11:30	Rong Yan & Minglong Shao
Parallel Applications (slides1, slides2 [PPT])	11:30-11:50	Mukesh Agrawal & Xinghua An