|Instructor:||Todd C. Mowry, WeH 8123, 268-3725, email@example.com, Thu 10:30-11:30am|
|TA:||Mahim Mishra, WeH 8203, 268-3562, firstname.lastname@example.org, Tue 1:30-2:30pm|
|Class Admin:||Maury Burgwin, WeH 8124, 268-4740, email@example.com|
|Hardcopies: In bins outside WeH 8124.|
The following textbook is required for the course:
The goal of this course is to provide a deep understanding of the fundamental principles and engineering tradeoffs involved in designing modern parallel computers (aka ``multiprocessors''), as well as the programming techniques to effectively utilize these machines. Parallel machines are already ubiquitous from desktops to supercomputers, and the expectation is that they will become even more commonplace in the future. However, very few people exploit the potential processing power of these machines because they do not understand how to write efficient parallel programs. Because one cannot design a good parallel program without understanding how parallel machines are built and vice-versa, this course will cover both parallel hardware and software design, as well as the impact that they have on each other.
Course topics include naming shared data, synchronizing threads, and the latency and bandwidth associated with communication. Case studies on shared-memory, message-passing, data-parallel and dataflow machines will be used to illustrate these techniques and tradeoffs. Programming assignments will be performed on one or more commercial multiprocessors, and there will be a significant course project.
This is a relatively unique course since this material is rarely offered to undergraduates. Because parallel processing has become such an important and mainstream technology, the time has come to integrate this material into the undergraduate systems curriculum. This is the first time that this course has been offered at Carnegie Mellon. Assuming that all goes well, the current plan is to offer it again this coming Fall.
15-213 (Intro to Computer Systems) is a strict prerequisite for this course. We will build directly upon the material presented in 15-213, including memory hierarchies, memory management, basic networking, etc.
While 18-347 (Intro to Computer Architecture) would be helpful for understanding the material in this course, it is not a prerequisite.
To complete your programming assignments and course projects, you will be receiving accounts on machines at some of the supercomputing centers: mostly likely either the National Center for Supercomputing Applications (NCSA) or the Pittsburgh Supercomputing Center (PSC). Details will be provided later.
Important: please note that the class will be allocated a finite (and not particularly large) amount of time on these machines, so please be careful not to waste time unnecessarily.
Grades will be based on homeworks, a project, two exams, and class participation.
Your overall grade is determined as follows:
|Exams:||40% (20% each)|
Late assignments will not be accepted without prior arrangement.
Table 1 shows the tentative schedule. Since this is the
first time that this class is being taught, it is likely that there may be
some significant variations.
|1||1/15||Tue||Why Study Parallel Architecture?||1.1|
|2||1/17||Thu||Evolution of Parallel Architecture||1.2|
|3||1/22||Tue||Fundamental Design Issues||1.3-4|
|4||1/24||Thu||Parallel Programming: Overview||2.1-4|
|5||1/29||Tue||Parallel Programming: Performance||3.1-4||L1 Out|
|6||1/31||Thu||Parallel Programming: Case Studies||3.5|
|7||2/5||Tue||Implications for Programming Models||3.6-7|
|8||2/7||Thu||Scaling Workloads and Machines||4.1||L1 Due, L2 Out|
|9||2/12||Tue||Evaluating Machines and Ideas||4.2-5|
|10||2/14||Thu||Shared Memory Multiprocessors I||5.1-3|
|11||2/19||Tue||Shared Memory Multiprocessors II||5.4||L2 Due, L3 Out|
|12||2/21||Thu||Snoop-Based Multiprocessor Design I||6.1-4|
|13||2/26||Tue||Snoop-Based Multiprocessor Design II||6.5-7|
|14||2/28||Thu||Scalable Distributed Memory MPs||7.1-8||L3 Due|
|3/7||Thu||No Class: Mid-Semester Break|
|15||3/12||Tue||Directory-Based Cache Coherence I||8.1-5|
|16||3/14||Thu||Directory-Based Cache Coherence II||8.6-7, 8.9-11||Project Proposal|
|17||3/19||Tue||Relaxed Memory Consistency Models||9.1|
|18||3/21||Thu||Cache-Only Memory Architectures||9.2.2, 9.4|
|19||3/26||Tue||Synchronization||5.5, 7.9, 8.8|
|20||3/28||Thu||Interconnection Network Design I||10.1-4||Project Milestone 1|
|21||4/9||Tue||Interconnection Network Design II||10.5-10|
|22||4/11||Thu||Latency Tolerance: Overview||11.1-5|
|23||4/16||Tue||Latency Tolerance: Prefetching||11.6||Project Milestone 2|
|24||4/18||Thu||Latency Tolerance: Multithreading||11.7-9|
|25||4/25||Thu||Terascale Computing System at PSC||N/A|
|26||4/30||Tue||Earthquake Simulation Case Study||N/A||Project Due|
|5/2||Thu||Project Poster Session|
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