Class | Date | Day | Topic | Reading | Assignments |
1 | 1/15 | Tue | Why Study Parallel Architecture? | 1.1 | |
2 | 1/17 | Thu | Evolution of Parallel Architecture | 1.2 | |
3 | 1/22 | Tue | Fundamental Design Issues | 1.3-4 | |
4 | 1/24 | Thu | Parallel Programming: Overview | 2.1-4 | |
5 | 1/29 | Tue | Parallel Programming: Performance | 3.1-4 | L1 Out |
6 | 1/31 | Thu | Parallel Programming: Case Studies | 3.5 | |
7 | 2/5 | Tue | Implications for Programming Models | 3.6-7 | |
8 | 2/7 | Thu | Scaling Workloads and Machines | 4.1 | L1 Due, L2 Out |
9 | 2/12 | Tue | Evaluating Machines and Ideas | 4.2-5 | |
10 | 2/14 | Thu | Shared Memory Multiprocessors I | 5.1-3 | |
11 | 2/19 | Tue | Shared Memory Multiprocessors II | 5.4 | L2 Due, L3 Out |
12 | 2/21 | Thu | Snoop-Based Multiprocessor Design I | 6.1-4 | |
13 | 2/26 | Tue | Snoop-Based Multiprocessor Design II | 6.5-7 | |
14 | 2/28 | Thu | Scalable Distributed Memory MPs | 7.1-8 | L3 Due |
3/5 | Tue | Exam I | |||
3/7 | Thu | No Class: Mid-Semester Break | |||
15 | 3/12 | Tue | Directory-Based Cache Coherence I | 8.1-5 | |
16 | 3/14 | Thu | Directory-Based Cache Coherence II | 8.6-7, 8.9-11 | Project Proposal |
17 | 3/19 | Tue | Relaxed Memory Consistency Models | 9.1 | |
18 | 3/21 | Thu | Cache-Only Memory Architectures | 9.2.2, 9.4 | |
19 | 3/26 | Tue | Synchronization | 5.5, 7.9, 8.8 | |
20 | 3/28 | Thu | Interconnection Network Design I | 10.1-4 | Project Milestone 1 |
Spring Break | |||||
21 | 4/9 | Tue | Interconnection Network Design II | 10.5-10 | |
22 | 4/11 | Thu | Latency Tolerance: Overview | 11.1-5 | Project Milestone 2 |
23 | 4/16 | Tue | Latency Tolerance: Prefetching | 11.6 | |
24 | 4/18 | Thu | Latency Tolerance: Multithreading | 11.7-9 | |
4/23 | Tue | Exam II | |||
25 | 4/25 | Thu | Earthquake Simulation Case Study | N/A | Project Due |
26 | 4/30 | Tue | Terascale Computing System at PSC | N/A | |
5/2 | Thu | Project Poster Session |
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