Explanation of Microcode Bit Meanings			Jean Schutty 4/29/91
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CC:
	If set to 1, condition codes will be stored in the flip flops.
	If set to 0, they will not be stored.
	Is connected to the clock pulse line of the Z, N, and V flip flops.

MARld:
	Load line for the MAR.  When set to 1, the 'in' value will be
	loaded into the register on the positive clock edge.

MARen:
	The enable line for the MAR.
	When set to 0 (is active low), will allow the register to start driving
	the output in 15 time units.
	When set to 1, sets the output to high impedence within 5 time units.

MARsel:
	The select line for a 2:1 mux which when set to:
		0  ALUout
		1  rs1 (one of 2 outputs of the rfile setup)
	will be used as the in line of the MAR.

Msel:
	The select line for a 2:1 mux which if set to:
		0	will send MAR out
		1	will send PC out
	into the address_in line of the RAM.

mrq:
	The memory request signal used in the RAM which initiates a memory
	operation.
	When set to 1, a memory operation will take place.
	When set to 0, one will not take place.

rnw:
	The read_notwrite line for the RAM.  Is the operation to be performed.
		1 = read
		0 = write.

Templd:
	Load line for Temp register.  When set to 1, the 'in' value will be
	loaded into the register on the poitive clock edge.

Tempen:
	The enable line for the Temp register.
	When set to 0 (is active low), will allow the register to start driving
	the output in 15 time units.
	When set to 1, sets the output to high impedence within 5 time units.

PCld:
	The load line for the PC register.  When set to 1, the 'in' value will
	be loaded into the register on the poitive clock edge.

PCen:
	The enable line for the PC register.
	When set to 0 (is active low), will allow the register to start driving
	the output in 15 time units.
	When set to 1, sets the output to high impedence within 5 time units.

PCs  (2 bits):
	The select line for a 4:1 mux which chooses what value will be used for
	the in line of the PC register.  When set to:
		00  PC_out + disp22<<2
		01  PC_out + 4
		10  disp30<<2
		11  ALU out
	will be sent into the PC register.

Asel1:
	The select line for a 2:1 mux choosing
		rs1 if set to 0
		Temp_out if set to 1.
	rs1 is one of the two outputs of the rfile.
	The result will be sent to the below mux.

Asel2:
	The select line for a 2:1 mux choosing
		the output of the above mux if set to 0
		MAR_out if set to 1.
	The result will be sent to the ALU as the in1 line.

ALUci:
	The carry_in line of the ALU.  It is used for the adder.

ALUfunc (4 bits):
	A 4 bit number designating what operation the ALU is to perform.
		0000  output is zero + carry_in
		0001  pass in2 to output
		0010  addition
		0011  2's complement subtract
		0100  bitwise and
		0101  bitwise or
		0110  bitwise xor
		0111  bitwise nand
		1000  bitwise nor
		1001  pass in1 to output
		1010  increment in2
		1011  ""
		1100  ""
		1101  ""
		1110  ""
		1111  ""

Dsel : 
	The select line for a 2:1 mux selecting between:
		0 ALUout
		1 Mout (i.e. Memory out)
	The selected item will go into the following mux...

Dsel2:
	The select line for a 2:1 mux selecting between:
		0 PCout
		1 the output from the above mux
	These 2 muxes will send either ALUout, Mout, or PCout into 
	datain line of all 3 rfiles.

Rsel2:
	The select line for a 2:1 mux selecting between:
		0 IR[29:25] (rd)
		1 15
	The selected item will go through the following equation:
		((n-8) + (window*16)) 
	taken from sparc.v to calculate the correct register to use 
	according to which window you are in. 
	Then, the lower 5 bits will go into wr_sel of the 2 nonglobal rfiles, 
	and the greatest bit will be used in deciding which of the 2 nonglobal
	rfiles should be written to (i.e. in deciding the value of en_write for
	both nonglobal rfiles).

Rsel3:
	The select line for a 2:1 mux selecting between:
		0 IR[18:14] (rs1)
		1 14
	The selected item will go through the following equation:
		((n-8) + (window*16)) 
	taken from sparc.v to calculate the correct register to use 
	according to which window you are in. 
	Then, the lower 5 bits will go into asel of the 2 nonglobal rfiles, 
	and the greatest bit will be used as one of 2 select lines of a mux
	which decides which of the 3 rfile's aouts will be used as the value 
	of reg1.

Rwr:
	One of the inputs into 3 reduct-or gates which decide which bank of
	registers will be written to in the rfile setup.  (The en_write line of
	each rfile is active low.)  When Rwr is set to 0, one of the rfiles
	will be written to.  When it is set to 1, none of the rfile will be
	written to.

	For Reference:
	==============
	reg.#	what used for			where
	----------------------------------------------
	0-7	global				rfile0
	8-15	window1 in			rfile1
	16-23	window1 local 			rfile1
	24-31	window1 out, window2 in		rfile1
	32-39	window2 local			rfile2
	40-47	window2 out, window3 in		rfile2
	48-55	window3 local			rfile2
	56-63	window3 out			rfile2

Ren:
	The enA and enB for all 3 rfiles.  When set to:
		0 output is passed,
		1 output is high impedence.

IRload:
	Load line for IR.  When set to 1, the 'in' value will be loaded
	into the register on the poitive clock edge.

IRen:
	The enable line for the IR.
	When set to 0 (is active low), will allow the register to start driving
	the output in 15 time units.
	When set to 1, sets the output to high impedence within 5 time units.

usel (3 bits) :
	The selects for an 8:1 mux, selecting the cond_test for useq:
		000 contains 0 for branch never (to get to next instr.)
		001 contains 1 for branch always (to get to and from fetch)
		010 contains WINTRAP 
		011 contains MWait
		100 contains Z or (N xor V)
		101-111 contain zeros - will not be selected.

usel2 :
	The select line for a 2:1 mux, selecting the branch address for useq:
		0 from the ustore ROM
		1 from the translation ROM

WIMld:	
	The load line for the WIM counter.
		
WIMc:
	The count line for the WIM counter.

WIMdu:
	The down/up line for the WIM counter.

CWPld:
	The load line for the CWP counter.

CWPc:
	The count line for the CWP counter.

CWPdu:
	The down/up line for the CWP counter.