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From: ccb8m@onyx.cs.Virginia.EDU (Charles C. Bundy)
Subject: Re: Flip-Flop....
Message-ID: <CKIJLH.5sr@murdoch.acc.Virginia.EDU>
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Organization: University of Virginia Computer Science Department
References: <CKEEA7.Bv8@ecf.toronto.edu> <pplanteCKH7Iy.5r9@netcom.com>
Date: Mon, 31 Jan 1994 21:27:17 GMT
Lines: 27

In article <pplanteCKH7Iy.5r9@netcom.com> pplante@netcom.com (P. Plantec) writes:
>CHENG  BENJAMIN (chengb@ecf.toronto.edu) wrote:
>: Hello,
>
>:      Does anyone know any configuration to make an JK flip-flop's
>:      outputs (i.e. Q and Q') be the same state (i.e. both 0 or both 1)?
>
>:      Any suggestions will be appreciated.
>
>: 						     Benjamin Cheng
>: 						  (University of Toronto)
>: 						  chengb@ecf.utoronto.ca
>
>Ben, 
>	The very nature of a JK flip-flop is to flip-flop states.  I 
>suspect if you got one to do what you ask, it would develop a perminant 
>personality crisis and become quite unstable.  If you find this 
>necessary, I suspect you need a diferent kind of circuit.
>PMP 8-)>
>-- 

Put a NOT gate on either output? <GRIN> I couldn't resist, Hee...

As PMP asked, Why do you want the same output on Q & Q'??

Charles
ccb8m@virginia.edu
