Newsgroups: comp.lang.lisp,comp.lang.scheme,comp.arch
Path: cantaloupe.srv.cs.cmu.edu!nntp.club.cc.cmu.edu!goldenapple.srv.cs.cmu.edu!rochester!udel-eecis!netnews.com!ix.netcom.com!tgm
From: tgm@netcom.com (Thomas G. McWilliams)
Subject: Re: Switching (was: Will Java VM kill Lisp?  How to fight it.)
Message-ID: <tgmE8F7p6.7tn@netcom.com>
Followup-To: comp.lang.lisp,comp.lang.scheme,comp.arch
Organization: Jot-Em-Down Store and Library
X-Newsreader: TIN [version 1.2 PL2]
References: <5ifjsj$qdc@news-rocq.inria.fr>
Date: Thu, 10 Apr 1997 11:53:30 GMT
Lines: 35
Sender: tgm@netcom21.netcom.com
Xref: glinda.oz.cs.cmu.edu comp.lang.lisp:26593 comp.lang.scheme:19468 comp.arch:76575

Robert Harley (harley@pauillac.inria.fr) wrote:
: My former advisor, Pr. Alain Martin, and his group have fabbed
: asynchronous microprocessors and filters in silicon and gallium
: arsenide.  They work quickly and reliably over a huge range of
: voltages with little power.  These designs haven't made it to the big
: time just yet but people like IBM are working on that aspect, at least
: for DSPs.


See EE TIMES (April 7, 1997, page 14):

"ARM warms to 32-bit asynch-logic RISC core

 The launch of Amulet-3, an asynchronous-logic implementation of the ARM
 32-bit RISC architecture ahs been set for sometime in 1999. Availability
 of such a core could mark the first significant use of asynchronous
 logic in a large commercial design.
 
 . . . [ snip ]

 Such a core is expected to offer benefits over clocked equivalents
 in terms of Mips/W and low power consumption in portable application,
 particularly where frequent halts of the microprocessor may be required.

 Expectations are supported by Amulet-2e, which was manufactured for
 Manchester University by VLSI Technology Inc. (San Jose, Calif) using
 a 3.3-V. 0.5 micron three-layer metal CMOS process. It achieved a
 room-temperature performance of 40 Mips while consuming 140 mW. In
 standby mode that was reduced to 3 uW (see EE TIMES October 28, 1996).

 . . . [ snip ]

 Amulet-3 will be implemented in a 0.35-micron, 3-V three-layer-metal
 CMOS process."

