Newsgroups: comp.robotics
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From: lye@fraser.sfu.ca (Bill Lye)
Subject: Major Problem: 80C186 & 82C51A
Message-ID: <lye.734465494@sfu.ca>
Sender: news@sfu.ca
Organization: Simon Fraser University, Burnaby, B.C., Canada
Date: Sat, 10 Apr 1993 18:11:34 GMT
Lines: 64

For our mobile robotics project here at SFU, we're using an 80C186 as the
main processor, and for communications to the outside world, we're using
an 82C51A.  Or at least we're trying to.

I've been arguing with this combination for two weeks now and my hair is
getting pretty white at the roots, trying to get the 82C51A to initialize
correctly.

Has anyone out there had experience with this combination, and/or has any
ideas that might be able to help me out figuring out what is going wrong?

Just for the record, I am trying to get 9600bps 8N1 async communications,
using a 16x clock TxC/RxC clock (6 high, 7 low) generated from Timer 1 of
the 80C186.  The CLK input is a 2 MHz square wave, and is active during
the reset pulse (which is very long right now, about 10ms).  DTR is
connected to DSR, and RTS is connected to CTS.  The chip select line is
connected up to PCS1, programmed for 3 wait states, and the C/D line is
connected to PCS5/LA1 programmed to act as latched A1.  The sequence of write 
operations is as follows:


	MOV	DX, USART_CONTROL	;PCS1+2
	MOV	AL, 0			;INITIAL THREE ZEROES
	OUT	DX, AL
	OUT	DX, AL
	OUT	DX, AL
	MOV	AL, 01000000b		;RESET
	OUT	DX, AL
	MOV	AL, 01001110b		;MODE
	OUT	DX, AL
	MOV	AL, 00110111b		;COMMAND

All this is as for the Intel Data Books, as well as the OKI data book
(the actual chip we got) and for something else (Siemens or Signetics maybe)
who also produce the chip.

I have verified that all the data bus, power, and clock connections are
correct.  (Numerous times.  I've had three other people check it over as
well).

I have replaced the chip (twice).  Both times with the OKI device (can't
find an Intel part).

Using the logic analyzer, I have traced the sequence of write operations,
and they appear to be correct, (i.e. RD, WR, CS, and C/D lines are correct).

The RTS, DTR, TxE and TxRDY go active after the COMMAND write.  The
RxRDY line goes high five rising edges of the RxC clock after the COMMAND
write.  This implies that the device is in 5-bit synchronous mode.  This
has been verified by replacing the initial three zero writes with different
values (specifically 0Ch).  The second write of zero appears to be being
interpreted as the mode, because replacing it with a write of 0Ch makes the
RxRDY go active after eight rising edges of RxC.  This would mean that
the third zero and my RESET are being interpreted as the two SYN characters.
However my MODE should then be interpreted as a RESET and the COMMAND
would then be a MODE.  That doesn't appear to be happening, since my COMMAND
still affects DTR and RTS.  Confusing as hell.  Also very frustrating.

Any ideas?  Please e-mail me.  If you have any better ideas of where I could
seek help, please also e-mail me.  
-- 
| Bill Lye, lye@sfu.ca    |  I can finally see a light at the end of |
| 5th year ENSC Undergrad |  the tunnel.  I just hope it's the end   |
| Simon Fraser University |  of the tunnel, not an oncoming train!   |
