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From: hbaker@netcom.com (Henry Baker)
Subject: Re: Garbage collection cost (was Re: Parenthesized syntax challenge)
Message-ID: <hbaker-2710950838100001@10.0.2.15>
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References: <44aa9a$j5h@miso.cs.uq.edu.au> <LUDEMANN.95Oct6140930@expernet26.expernet.com> <DGApp8.J41@undergrad.math.uwaterloo.ca> <MAD.95Oct13123618@tanzanite.math.keio.ac.jp> <45ksdk$7gr@jive.cs.utexas.edu> <DGJp8o.7nF@Cadence.COM> <MAD.95Oct18040436@tanzanite.math.keio.ac.jp> <hbaker-1710952127200001@10.0.2.15> <46jb8v$sm8@news.parc.xerox.com> <hbaker-2510951016220001@10.0.2.15> <vrotneyDH17B3.29q@netcom.com> <QOBI.95Oct26104628@qobi.ai>
Date: Fri, 27 Oct 1995 16:38:10 GMT
Lines: 17
Xref: glinda.oz.cs.cmu.edu comp.lang.lisp:19741 comp.lang.dylan:5656 comp.lang.java:2934

In article <QOBI.95Oct26104628@qobi.ai>, Qobi@CS.Toronto.EDU wrote:

> I'm told that on DEC ALPHAs, which use 64 bit points, that memory requirements
> are doubled yet again.
> 
> Data structure size affects not only paging performance but also caching
> performance. Has anybody done a study to see what the tradeoffs are between
> the increased instruction cost of CDR coding vs the potential decreased
> cache-miss ratio? How would that change if minimal CDR-coding hardware were
> added to RISC processors?

I would believe that some sort of 'pointer-swizzling' idea might work better
than checking the pointers on every access.

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