Newsgroups: comp.constraints
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From: pesant@nil.IRO.UMontreal.CA (Gilles Pesant)
Subject: Post-doctoral position - University of Montreal, Canada
Message-ID: <PESANT.95Jan27114805@nil.IRO.UMontreal.CA>
Sender: news@IRO.UMontreal.CA
Organization: Universite de Montreal -- Laboratoire Incognito
Date: Fri, 27 Jan 1995 16:48:05 GMT
Lines: 28

We have a position available for a post-doctoral fellow, applying
constraint programming to the area of gate-level timing verification.

The candidate should have background in either gate-level timing
simulation or timing verification (not necessarily at the gate level),
and have basic knowledge of logic gate networks (e.g., logic design
course). Awareness of test-generation algorithms for gate networks
and/or constraint solving techniques would be an asset. Working
knowledge of Unix and programming in C++ is required.

Background information on the area of work: 
E. Cerny and J. Zejda, "Gate-level timing verification using waveform 
narrowing", Proc. EuroDAC'94 Conf. Grenoble, Sept. 1994.

Earliest starting date: January 1995.
Salary: 27.5K $CAN/year.

Please, send a CV to the address below, a postscript file by e-mail is
also accepted.


-- 
Prof. Eduard Cerny, Dep. d'informatique et de recherche operationnelle (IRO);
Pavillon Andre-Aisenstadt, #2143;  Universite de Montreal; 
2900, boul.Edouard-Montpetit; C.P. 6128, Succ.CENTRE-VILLE; 
Montreal, Que., H3C 3J7 Canada 
Tel: (514) 343-7472  e-mail: cerny@iro.umontreal.ca  FAX: (514)-343-5834

