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From: RedKnight@tseserv (RedKnight)
Subject: Re: Are floating gates as synapses practical?
Message-ID: <D0Ep79.EpI@pts.mot.com>
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Date: Tue, 6 Dec 1994 20:35:33 GMT
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In article <3bvkdm$n2e@ics.uci.edu>, coultrip@ics.uci.edu (Robert Coultrip) writes:
> 
> (1) a single chip with a self-contained learning algorithm/circuitry
>     for floating gates is not yet practical and

Check out a recent paper by Axel Thomsen et al. in IEEE Circuits and Systems I,
the July 94 issue give or take a few.  Also, if you haven't already, look at the
Intel ETANN which is probably the best-known commercial neural chip and uses
programmable differential floating gates for weight storage.  Papers on this by
Mark Holler et al. can be found in various IEEE, INNS proceedings (and are
referenced by many papers related to this topic).


> (2) due to pin count limitations, only a few hundred synapses per chip
>     are possible since each synapse consumes a pin.

Multiplexing and address schemes can be/are used in lieu of a suitable on-chip
learning controller to increase array size.


Hope this helps.

-- 

  \ /      RedKnight               | Chris McCarley
 --O===<|  mccarley@pts.mot.com    | Motorola, Paging Products Group
  / \      "I have seen the future |
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