ADVANCE PROGRAM HPCA'95 First International Symposium on High Performance Computer Architecture Sponsor: IEEE Computer Society Technical Committee on Computer Architecture Jan 22 - Jan 25, 1995 Sheraton Inn, Raleigh, North Carolina ----------------------------------------------------------------------------- General Chair: Yale N. Patt, University of Michigan, patt@eecs.umich.edu, Tel. (313) 936-1602 Program Chair: Laxmi N. Bhuyan, Texas A&M University, hpca@cs.tamu.edu, Tel. (409) 845-5534 Program Committee: Tilak Agerwala, IBM Arvind, Massachusetts Institute of Technology Ken Batcher, Kent State University Anton T. Dahbura, Motorola Doug DeGroot, Texas Instrument Michel Dubois, University of Southern California Michael J. Flynn, Stanford University V. Carl Hamacher, Queen's University Wen-mei Hwu, University of Illinois J. Robert Jump, Rice University and NSF Dan Moldovan, Southern Methodist University Trevor Mudge, University of Michigan Lionel Ni, Michigan State University Bruce Shriver, Consultant James E. Smith, Cray Research Earl Swartzlander, University of Texas, Austin Nian-Feng Tzeng, University of Southwestern Louisiana Pen-Chung Yew, University of Minnesota Local Arrangement Chair: Teressa Dahlberg, IBM Finance Chair: Ed Gehringer, North Carolina State University Publications Chair: Qing Yang, University of Rhode Island Publicity Chair: Philip McKinley, Michigan State University Registration Chair: James M. Conrad, University of Arkansas Ex officio: Dharma Agrawal, North Carolina State University IEEE CS TCCA Chair ----------------------------------------------------------------------------- Conference Site --------------- Money Magazine has ranked Raleigh area as the best place to live in America. Nestled between the Blue Ridge mountains and the Atlantic Ocean, this area along with the Research Triangle park has become a booming industrial and research heaven. The HPCA meeting will be held at the Crabtree Sheraton Inn, Raleigh that offers a variety of entertainments and guest services. The hotel is located next to the most important commercial district, United States' largest regional shopping complex - the Crabtree Valley Mall. The hotel is about 10 miles from the Raleigh (RDU) airport served by many domestic and international airlines with non-stop flights from many US and some European cities. Complimentary shuttle service between the airport and hotel is provided. The shuttle runs on the hour and on call. Other complimantary services include coffee, newspaper, indoor pool and excercise facilities. ------------------------------------------------------------------------------ Hotel Reservation: ------------------ A block of rooms has been reserved untill Dec. 26, 1994 at the rate of $68 single; $70 double. Please call for reservation at (919) 787-7111; fax (919) 783-0024. Ask for IEEE meeting to get the group rate. ------------------------------------------------------------------------------ Registration Information ------------------------ Symposium Workshop* Tutorial 1* Tutorial 2* -------------- -------------- -------------- -------------- Upto After Upto After Upto After Upto After 1/1/95 1/1/95 1/1/95 1/1/95 1/1/95 1/1/95 1/1/95 1/1/95 ------ ------ ------ ------ ------ ------ ------ ------ ACM/IEEE Member US$300 US$350 US$60* US$75* US$120 US$150 US$120 US$150 Non-member US$370 US$420 US$75* US$90* US$150 US$200 US$150 US$200 Student US$150 US$200 US$50* US$60* US$100 US$130 US$100 US$130 *If you are registered for HPCA, you will receive a $10 credit on your registration for the workshop. The organizers reserve the right to cancel a tutorial due to low attendance. NOTE: Do not send credit card information via email! The symposium registration includes the attendance at the symposium, symposium proceedings, reception, and luncheon. Student registration does not include the luncheon. Please send the completed registration form (below), with your payment to Dr. James M. Conrad University of Arkansas Computer Systems Engineering Dept. 313 Engineering Hall Fayetteville, AR 72701-1201 Tel: (501) 575-6039 Fax: (501) 575-5339 e-mail: jmc3@engr.engr.uark.edu Registration Form: ------------------ Last Name:____________________ First Name:___________________ Middle Initial:__ Organization:__________________________________________________________________ Address:_______________________________________________________________________ City:___________________________ State:_________________ Zip Code:_____________ Country:__________________ Telephone:________________ Fax:_____________________ Email Address: _________________________________ IEEE Member: ___ Non-member: ___ Student: ___ IEEE Member #: ___________ Symposium: US$_____ Tutorial(s): US$_____ Specify choice of tutorial(s)_______ Workshop: US$_____ Total: US$_____ Check, payable to HPCA, drawn on US Bank only: ____________________________ Credit Card: VISA___ or MasterCard___ Credit Card # _______________________ Expiration date: ___________ Signature ______________________ ------------------------------------------------------------------------------ CONFERENCE AT A GLANCE --------------------- ______________________________________________________________________________ | | Sunday Jan 22 | Monday Jan 23 | Tuesday Jan 24 | Wednesday Jan 25| |_______|________________|________________|________________|_________________| | 8:00 | | T | | | | | | | U | |________________|_________________| | 8:30 | | T | |Session|Session |Session |Session | | |_______| O |________________| IIIA | IIIB | VIA | VIB | | 9:00 | W | R | Inauguration & |Cache |Modeling|Special |Code | | | O | I | Keynote Speech |Memory |& Perf. |Purpose |Optimi- | | 9:30 | R | A | | |Eval. |Arch. |-zation | | | K | L | Harold Stone, |_______|________|________|________| | 10:00 | S | | NEC Research | Coffee Break | Coffee Break | | | H | 1 |________________|________________|_________________| | 10:30 | O | | Coffee Break |Session|Session | Invited Session | | | P | |________________| IVA | IVB | II | | 11:00 | | |Session|Session |Synchr.|Cache |Uniprocessor | | | | | IA | IB |& Sched|Coheren-|Architectures for| | 11:30 | | |Regist.|Interco-| |-ce |High Performance | | |_______|________|Manage-|nnection|_______|________|_________________| | 12:00 | Lunch Break |-ment |Networks| Luncheon & | | | |_______|________| Award | | 12:30 | | Lunch Break | Presentation | | |________________| | | | 1:00 | W | T | | H. Troy Nagle | | | O | U | | President, | | 1:30 | R | T | | IEEE | | | K | O |________________|________________| | 2:00 | S | R |Invited Session |Session|Session | | | H | I | I | VA | VB | | 2:30 | O | A | Commercial |Memory |Multith-| | | P | L | Multiprocessor |Manage-|-readed | | 3:00 | | | Architectures |-ment |Arch. | | | c | 2 |________________|_______|________| | 3:30 | o | | Coffee Break | Coffee Break | | | n | |________________|________________| | 4:00 | t | |Session|Session | Panel Session | | | d | | IIA | IIB | | | 4:30 | | |Latency|Routing | | | |_______|________|Reductn|in Mesh | | | 5:00 | |Technq.| | | | | |_______|________|________________| | 5:30 | | Break | Break | | | | | | | 6:00 | | | | | | |________________| | | 6:30 | | Reception | | | | | Hors d'oeuvres | | | 7:00 | | & Cash Bar | | | | | | | | 7:30 | | | | | | | |________________| | 8:00 | | | TCCA Meeting | | | | | | | 8:30 | | | | |_______|________________|________________|________________| ------------------------------------------------------------------------------ TECHNICAL PROGRAM ----------------- JAN 22 (Sunday) --------------- WORKSHOP on Computer Architecture Education Organizer: David Kaeli, Northeastern University 9AM - 5PM This workshop focuses on issues related to undergraduate and graduate Computer Architecture education. The workshop is intended for both Computer Engineering and Computer Science faculty members. The full-day workshop will provide a forum for disseminating information on the current state-of-the-art in Computer Architecture education. The participants will come away from the workshop with new teaching tools and improved teaching methods, that can be used in their Computer Architecture curriculum. For more information on the workshop, contact kaeli@nuvlsi.coe.neu.edu, (617) 373-5413. TUTORIAL 1: SCI-based Local Area Multiprocessors by Qiang Li and David Gustavson, Santa Clara University. 8AM - 12noon Local Area Multiprocessor (LAMP) is a novel concept for achieving MPP-like performance with a cost comparable to that of clusters of workstations. It can be highlighted by its hardware supported shared memory and cache coherence among workstations. This tutorial will cover the architectural model, the Scalable Coherent Interface (ISO/ANSI/IEEE Standard), the implementation issues, and current status of various developments. TUTORIAL 2: Multigranular Computing by Umakishore Ramachandran, Georgia Institute of Technology. 1PM - 5PM The topics to be covered include architectural examples from discrete points in the granularity spectrum (including Maspar MP-2, KSR-1, and CM-5); application domains that could benefit from such a multigranular environment; analysis of kernels of applications to identify types of parallelism; determining the match between algorithms and architectures; performance metrics for making the right architectural choice for algorithms; and several case studies drawn from reconfigurable architectures to networked parallel computers of different granularities. JAN 23 (Monday) --------------- **************************************************************************** *********************** Inauguration -- 9am - 10.30am ***************** ************************************************************************** Keynote speaker - Harold Stone, NEC Research "Image Processing and its Impact on Architecture" **************************************************************************** *********************** COFFEE BREAK -- 10.30am - 11.00am ***************** ************************************************************************** **************************************************************************** *********************** SESSION IA ***************** *********************** 11.00 - 12.30 **************** *********************** Register Management *************** ************************************************************************ "The Named-State Register File: Implementation and Performance" by Peter R. Nuth, Hewlett-Packard Laboratories, and William J. Dally, MIT Artificial Intelligence Lab. "Implementing Register Interlocks in Parallel-Pipeline, Multiple Instruction Queue, Superscalar Processors" by Shlomo Weiss, Tel Aviv University. "Non-consistent Dual Register Files to Reduce Register Pressure" by Josep Llosa, Mateo Valero, and Eduard Ayguade, Universitat Politecnica de Catalunya. **************************************************************************** *********************** SESSION IB ***************** *********************** 11.00 - 12.30 **************** *********************** Interconnection Networks *************** ************************************************************************ "Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems" by Rami Melhem, University of Pittsburgh, and Chunming Qiao, State University of NY at Buffalo. "Toward High Communication Performance through Compiled Communications on a Circuit Switched Interconnection Network" by F. Cappello and C. Germain, University of Paris. "Abstracting Network Characteristics and Locality Properties of Parallel Systems" by Anand Sivasubramaniam, Aman Singla, H. Venkateswaran, and Umakishore Ramachandran, Georgia Tech. ************************************************************************** *********************** LUNCH -- 12.30pm - 2.00pm *************** ************************************************************************ **************************************************************************** *********************** INVITED SESSION I ***************** *********************** 2.00 - 3.30 **************** ******************** Commercial Multiprocessor Architectures ************ ************************************************************************ Architecture of IBM SP-2 by Tilak Agerwala, IBM Corp. Architecture of Cray T3D by Rick Kessler, Cray Research Inc. **************************************************************************** *********************** COFFEE BREAK -- 3.30pm - 4.00pm ***************** ************************************************************************** **************************************************************************** *********************** SESSION IIA ***************** *********************** 4.00 - 5.30 **************** *********************** Latency Reduction Techniques *************** ************************************************************************ "Effectiveness of Hardware-based Stride and Sequential Prefetching in Shared-Memory Multiprocessors" by Fredrick Dahlgren and Per Stenstrom, Lund University. "How Useful Are Non-blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?" by Keith Farkas and Paul Chow, Univ. of Toronto and Norman Jouppi, Western Research Lab. "Creating a Wider Bus Using Caching Techniques" by Daniel Citron and Larry Rudolph, The Hebrew University of Jerusalem. **************************************************************************** *********************** SESSION IIB ***************** *********************** 4.00 - 5.30 **************** *********************** Routing in Mesh *************** ************************************************************************ "Origin-Based Fault-Tolerant Routing in the Mesh" by Ran Libeskind-Hadas and Eli Brandt, Harvey Mudd College. "Efficient and Balanced Adaptive Routing in Two-Dimensional Meshes" by J. Upadhyay, V. Varavithya, and P. Mohapatra, Iowa State University. "Fault Tolerant Adaptive Routing for Two-Dimensional Meshes" by C. Cunningham and D. Avresky, Texas A&M University. **************************************************************************** *********************** CONFERENCE RECEPTION ****************** *********************** HORS D'OEUVRES & CASH BAR ***************** *********************** 6.30 - 9.00 **************** ************************************************************************ JAN 24 (Tuesday) ---------------- **************************************************************************** *********************** SESSION IIIA ***************** *********************** 8.30 - 10.00 **************** *********************** Cache Memory *************** ************************************************************************ "DASC Cache" by Andre Seznec, IRISA. "A Unified Framework for On-Chip Cache Design for High-Performance Architectures" by K. B. Theobald, McGill University, H. H. J. Hum, Concordia University, and G. R. Gao, McGill University. "Investigating Software-Assisted Data Caches" by O. Temam, University of Versailles, France. **************************************************************************** *********************** SESSION IIIB ***************** *********************** 8.30 - 10.00 **************** *********************** Modeling & Performance Evaluation *************** ************************************************************************ "Modeling Virtual Channel Flow Control in Hypercubes" by Younes M. Boura and Chita R. Das, Pennsylvania State University. "An Initial Evaluation of the Convex SPP-1000 for Earth and Space Science Applications" by T. L. Sterling, P. R. Merkey, and D. F. Savarese, Goddard Space Flight Center, and J. P. Gardner, University of Washington. "Simulation Study of Cached RAID5 Designs" by Kent Treiber and Jai Menon, IBM Research Division, Almaden Research Center. **************************************************************************** *********************** COFFEE BREAK -- 10.00am - 10.30am ***************** ************************************************************************** **************************************************************************** *********************** SESSION IVA ***************** *********************** 10.30 - 12.00 **************** *********************** Synchronization & Scheduling *************** ************************************************************************ "Fast Barrier Synchronization in Wormhole k-ary n-cube Networks with Multidestination Worms" by D. K. Panda, Ohio State University. "Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors" by Stuart Fiske and William J. Dally, Massachusetts Institute of Technology. "Scalability of Atomic Primitives on Distributed Shared Memory Multiprocessors" by Maged Michael and Michael Scott, University of Rochester. **************************************************************************** *********************** SESSION IVB ***************** *********************** 10.30 - 12.00 **************** *********************** Memory Management *************** ************************************************************************ "Improving Performance by Cache Driven Memory Management" by Karl Westerholz, Stephan Honal, Josef Plankl, and Christian Hafer, Siemens AG Corporate Research and Development, Munich, Germany. "U-cache:A Cost-effective Solution to the Synonym Problem" by Jesung Kim, Sang Lyul Min, Sanghoon Jeon, Byoungchul Ahn, Deog-Kyoon Jeong, and Chong Sang Kim, Seoul National Univ., Korea. "Access Ordering and Memory-Conscious Cache Utilization" by Sally A. McKee and Wm. A. Wulf, University of Virginia. ***************************************************************************** *********************** CONFERENCE LUNCHEON & AWARDS ****************** *********************** 12.00 - 2.00 ***************** ************************************************************************** Awards Presentation by H. Troy Nagle, President of the IEEE. ***************************************************************************** *********************** SESSION VA ****************** *********************** 2.00 - 3.30 ***************** *********************** Cache Coherence **************** ************************************************************************* "Two Techniques for Improving Performance on Bus-based Multiprocessors" by Craig Anderson and Jean-Loup Baer, University of Washington. "Simple Cache Only Memory Architectures" by Ashley Saulsbury, Swedish Institute of CS, Tim Wilkinson, Systems Architecture Research Centre, John Carter, University of Utah, and Anders Landin, Swedish Institute of CS. "Software Cache Coherence for Large Scale Multiprocessors" by Leonidas I. Kontothanassis and Michael L. Scott, Univesity of Rochester. **************************************************************************** *********************** SESSION VB ***************** *********************** 2.00 - 3.30 **************** *********************** Multithreaded Architecture *************** ************************************************************************ "Design and Performance Evaluation of a Multithreaded Architecture" by R. Govindarajan, S. S. Nemawarkar, and Phiip LeNir, McGill University. "Fine-grain Multi-thread Processor Architecture for Massively Parallel Processing" by Tetsuo Kawano, Shigeru Kusakabe, Rin-ichiro Taniguchi, and Makoto Amamiya, Kyushu University. "The Effects of STEF in Finely Parallel Multithreaded Processors" by Yamin Li and Wanming Chu, The University of Aizu, Japan. ***************************************************************************** *********************** COFFEE BREAK -- 3.30pm - 4.00pm ****************** *************************************************************************** **************************************************************************** *********************** PANEL SESSION ***************** *********************** 4.00 - 5.30 **************** ************************************************************************* "How Can Computer Architecture Researchers Avoid Becoming the Society for Irreproducible Results?" ....Moderator: Trevor Mudge, University of Michigan **************************************************************************** ************************ TCCA MEETING ******************* ************************ 8.00 pm - 9.00 pm ****************** ************************************************************************* JAN 25 (Wednesday) ------------------ **************************************************************************** *********************** SESSION VIA ***************** *********************** 8.30 - 10.00 **************** *********************** Special Purpose Architectures *************** ************************************************************************ "A VLSI Architecture for Computing the Tree-to-Tree Distance" by Raghu Sastry and N. Ranganathan, University of South Florida. "Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation" by Youngmin Hur and Stephen A. Szygenda, University of Texas at Austin. "Architectural Support for Inter-Stream Communication in MSIMD Systems" by David Schimmel and Vivek Garg, Georgia Tech. **************************************************************************** *********************** SESSION VIB ***************** *********************** 8.30 - 10.00 **************** *********************** Code Optimization *************** ************************************************************************ "Optimizing Instruction Cache Performance for Operating System Intensive Workloads" by Josep Torrellas, Chun Xia, and Russell Daigle, University of Illinois. "Program Balance and its Impact on High Performance Architectures" by Lizy Kurian and Vinod Reddy, University of South Florida Paul T. Hulina and Lee D. Coraor, Pennsylvania State University. "Memory Access Reordering in Vector Computers" by De-Lei Lee, York University, Ontario. **************************************************************************** *********************** COFFEE BREAK -- 10.00am - 10.30am ***************** ************************************************************************** ************************************************************************* ****************** INVITED SESSION II ********* ****************** 10.30 - 12.00 ******** ************** Uniprocessor Architectures for High Performance ***** ********************************************************************* Organizer: Yale Patt, University of Michigan ********************************************************************